[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>

#include <video/omapdss.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>
#include "common.h"

#include "iomap.h"
#include "mux.h"
#include "control.h"
#include "display.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
{
	u32 reg;
	u16 control_i2c_1;

	omap_mux_init_signal("hdmi_cec",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_scl",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_sda",
			OMAP_PIN_INPUT_PULLUP);

	/*
	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	 * internal pull up resistor.
	 */
	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
		control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
		reg = omap4_ctrl_pad_readl(control_i2c_1);
		reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
			OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
			omap4_ctrl_pad_writel(reg, control_i2c_1);
	}
}

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	return 0;
}

int __init omap_hdmi_init(enum omap_hdmi_flags flags)
{
	if (cpu_is_omap44xx())
		omap4_hdmi_mux_pads(flags);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static struct platform_device *create_dss_pdev(const char *pdev_name,
		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	struct omap_device *od;
	struct omap_hwmod *ohs[1];
	struct omap_hwmod *oh;
	int r;

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		r = -ENODEV;
		goto err;
	}

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	ohs[0] = oh;
	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	if (!od) {
		pr_err("Could not alloc omap_device for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = omap_device_register(pdev);
	if (r) {
		pr_err("Could not register omap_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
		int pdev_id, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	int r;

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = platform_device_add(pdev);
	if (r) {
		pr_err("Could not register platform_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct platform_device *pdev;
	int i, oh_count;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;
	struct platform_device *dss_pdev;

	/* create omapdss device */

	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;

	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create devices for dss hwmods */

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	/*
	 * First create the pdev for dss_core, which is used as a parent device
	 * by the other dss pdevs. Note: dss_core has to be the first item in
	 * the hwmod list.
	 */
	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
			curr_dss_hwmod[0].id,
			curr_dss_hwmod[0].oh_name,
			board_data, sizeof(*board_data),
			NULL);

	if (IS_ERR(dss_pdev)) {
		pr_err("Could not build omap_device for %s\n",
				curr_dss_hwmod[0].oh_name);

		return PTR_ERR(dss_pdev);
	}

	for (i = 1; i < oh_count; i++) {
		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id,
				curr_dss_hwmod[i].oh_name,
				board_data, sizeof(*board_data),
				dss_pdev);

		if (IS_ERR(pdev)) {
			pr_err("Could not build omap_device for %s\n",
					curr_dss_hwmod[i].oh_name);

			return PTR_ERR(pdev);
		}
	}

	/* Create devices for DPI and SDI */

	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
			board_data, sizeof(*board_data), dss_pdev);
	if (IS_ERR(pdev)) {
		pr_err("Could not build platform_device for omapdss_dpi\n");
		return PTR_ERR(pdev);
	}

	if (cpu_is_omap34xx()) {
		pdev = create_simple_dss_pdev("omapdss_sdi", -1,
				board_data, sizeof(*board_data), dss_pdev);
		if (IS_ERR(pdev)) {
			pr_err("Could not build platform_device for omapdss_sdi\n");
			return PTR_ERR(pdev);
		}
	}

	return 0;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

#define MAX_MODULE_SOFTRESET_WAIT	10000
int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
b7ee79ab	26
a0b38cc4	27	#include <video/omapdss.h>
cf07f531 SG	28	#include <plat/omap_hwmod.h>
cf07f531 SG	29	#include <plat/omap_device.h>
700dee78	30	#include <plat/omap-pm.h>
deee6d53	31	#include "common.h"
b7ee79ab	32
ee0839c2	33	#include "iomap.h"
ee9dfd82	34	#include "mux.h"
dc35835c	35	#include "control.h"
b923d40d AT	36	#include "display.h"
	37
	38	#define DISPC_CONTROL 0x0040
	39	#define DISPC_CONTROL2 0x0238
	40	#define DISPC_IRQSTATUS 0x0018
	41
	42	#define DSS_SYSCONFIG 0x10
	43	#define DSS_SYSSTATUS 0x14
	44	#define DSS_CONTROL 0x40
	45	#define DSS_SDI_CONTROL 0x44
	46	#define DSS_PLL_CONTROL 0x48
	47
	48	#define LCD_EN_MASK (0x1 << 0)
	49	#define DIGIT_EN_MASK (0x1 << 1)
	50
	51	#define FRAMEDONE_IRQ_SHIFT 0
	52	#define EVSYNC_EVEN_IRQ_SHIFT 2
	53	#define EVSYNC_ODD_IRQ_SHIFT 3
	54	#define FRAMEDONE2_IRQ_SHIFT 22
	55	#define FRAMEDONETV_IRQ_SHIFT 24
	56
	57	/*
	58	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	59	* reset before deciding that something has gone wrong
	60	*/
	61	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	62
b7ee79ab SS	63	static struct platform_device omap_display_device = {
	64	.name = "omapdss",
	65	.id = -1,
	66	.dev = {
	67	.platform_data = NULL,
	68	},
	69	};
	70
179e0453 AT	71	struct omap_dss_hwmod_data {
	72	const char *oh_name;
	73	const char *dev_name;
	74	const int id;
	75	};
	76
	77	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
	78	{ "dss_core", "omapdss_dss", -1 },
	79	{ "dss_dispc", "omapdss_dispc", -1 },
	80	{ "dss_rfbi", "omapdss_rfbi", -1 },
	81	{ "dss_venc", "omapdss_venc", -1 },
	82	};
	83
	84	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
	85	{ "dss_core", "omapdss_dss", -1 },
	86	{ "dss_dispc", "omapdss_dispc", -1 },
	87	{ "dss_rfbi", "omapdss_rfbi", -1 },
	88	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	89	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	90	};
	91
	92	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
	93	{ "dss_core", "omapdss_dss", -1 },
	94	{ "dss_dispc", "omapdss_dispc", -1 },
	95	{ "dss_rfbi", "omapdss_rfbi", -1 },
	96	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96 TV	97	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	98	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	99	{ "dss_hdmi", "omapdss_hdmi", -1 },
	100	};
	101
e8a30b25	102	static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
ee9dfd82	103	{
9a901683 M	104	u32 reg;
	105	u16 control_i2c_1;
	106
ee9dfd82 M	107	omap_mux_init_signal("hdmi_cec",
ee9dfd82 M	108	OMAP_PIN_INPUT_PULLUP);
ee9dfd82 M	109	omap_mux_init_signal("hdmi_ddc_scl",
	110	OMAP_PIN_INPUT_PULLUP);
	111	omap_mux_init_signal("hdmi_ddc_sda",
	112	OMAP_PIN_INPUT_PULLUP);
9a901683 M	113
	114	/*
	115	* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	116	* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	117	* internal pull up resistor.
	118	*/
	119	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
	120	control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
	121	reg = omap4_ctrl_pad_readl(control_i2c_1);
	122	reg \|= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK \|
	123	OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
	124	omap4_ctrl_pad_writel(reg, control_i2c_1);
	125	}
ee9dfd82 M	126	}
ee9dfd82 M	127
e8a30b25	128	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
dc35835c TV	129	{
	130	u32 enable_mask, enable_shift;
	131	u32 pipd_mask, pipd_shift;
	132	u32 reg;
	133
	134	if (dsi_id == 0) {
	135	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	136	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	137	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	138	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	139	} else if (dsi_id == 1) {
	140	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	141	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	142	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	143	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	144	} else {
	145	return -ENODEV;
	146	}
	147
	148	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	149
	150	reg &= ~enable_mask;
	151	reg &= ~pipd_mask;
	152
	153	reg \|= (lanes << enable_shift) & enable_mask;
	154	reg \|= (lanes << pipd_shift) & pipd_mask;
	155
	156	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	157
	158	return 0;
	159	}
	160
d1589f09	161	int __init omap_hdmi_init(enum omap_hdmi_flags flags)
ee9dfd82 M	162	{
ee9dfd82 M	163	if (cpu_is_omap44xx())
9a901683	164	omap4_hdmi_mux_pads(flags);
ee9dfd82 M	165
	166	return 0;
	167	}
	168
e8a30b25	169	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	170	{
dc35835c TV	171	if (cpu_is_omap44xx())
	172	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	173
5bc416cb TV	174	return 0;
	175	}
	176
e8a30b25	177	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	178	{
dc35835c TV	179	if (cpu_is_omap44xx())
dc35835c TV	180	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	181	}
5bc416cb TV	182
62c1dcfc TV	183	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	184	{
	185	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	186	}
	187
966eaed0 TV	188	static struct platform_device create_dss_pdev(const char pdev_name,
	189	int pdev_id, const char oh_name, void pdata, int pdata_len,
	190	struct platform_device *parent)
	191	{
	192	struct platform_device *pdev;
	193	struct omap_device *od;
	194	struct omap_hwmod *ohs[1];
	195	struct omap_hwmod *oh;
	196	int r;
	197
	198	oh = omap_hwmod_lookup(oh_name);
	199	if (!oh) {
	200	pr_err("Could not look up %s\n", oh_name);
	201	r = -ENODEV;
	202	goto err;
	203	}
	204
	205	pdev = platform_device_alloc(pdev_name, pdev_id);
	206	if (!pdev) {
	207	pr_err("Could not create pdev for %s\n", pdev_name);
	208	r = -ENOMEM;
	209	goto err;
	210	}
	211
	212	if (parent != NULL)
	213	pdev->dev.parent = &parent->dev;
	214
	215	if (pdev->id != -1)
	216	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	217	else
	218	dev_set_name(&pdev->dev, "%s", pdev->name);
	219
	220	ohs[0] = oh;
	221	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	222	if (!od) {
	223	pr_err("Could not alloc omap_device for %s\n", pdev_name);
	224	r = -ENOMEM;
	225	goto err;
	226	}
	227
	228	r = platform_device_add_data(pdev, pdata, pdata_len);
	229	if (r) {
	230	pr_err("Could not set pdata for %s\n", pdev_name);
	231	goto err;
	232	}
	233
	234	r = omap_device_register(pdev);
	235	if (r) {
	236	pr_err("Could not register omap_device for %s\n", pdev_name);
	237	goto err;
	238	}
	239
	240	return pdev;
	241
	242	err:
	243	return ERR_PTR(r);
	244	}
	245
53f576a8 TV	246	static struct platform_device create_simple_dss_pdev(const char pdev_name,
	247	int pdev_id, void *pdata, int pdata_len,
	248	struct platform_device *parent)
	249	{
	250	struct platform_device *pdev;
	251	int r;
	252
	253	pdev = platform_device_alloc(pdev_name, pdev_id);
	254	if (!pdev) {
	255	pr_err("Could not create pdev for %s\n", pdev_name);
	256	r = -ENOMEM;
	257	goto err;
	258	}
	259
	260	if (parent != NULL)
	261	pdev->dev.parent = &parent->dev;
	262
	263	if (pdev->id != -1)
	264	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	265	else
	266	dev_set_name(&pdev->dev, "%s", pdev->name);
	267
	268	r = platform_device_add_data(pdev, pdata, pdata_len);
	269	if (r) {
	270	pr_err("Could not set pdata for %s\n", pdev_name);
	271	goto err;
	272	}
	273
c3a21fc7	274	r = platform_device_add(pdev);
53f576a8	275	if (r) {
c3a21fc7	276	pr_err("Could not register platform_device for %s\n", pdev_name);
53f576a8 TV	277	goto err;
	278	}
	279
	280	return pdev;
	281
	282	err:
	283	return ERR_PTR(r);
	284	}
	285
b7ee79ab SS	286	int __init omap_display_init(struct omap_dss_board_info *board_data)
	287	{
	288	int r = 0;
3528c58e	289	struct platform_device *pdev;
179e0453	290	int i, oh_count;
179e0453	291	const struct omap_dss_hwmod_data *curr_dss_hwmod;
966eaed0	292	struct platform_device *dss_pdev;
cf07f531	293
00928eaf TV	294	/* create omapdss device */
	295
	296	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	297	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	298	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	299	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
	300
	301	omap_display_device.dev.platform_data = board_data;
	302
	303	r = platform_device_register(&omap_display_device);
	304	if (r < 0) {
	305	pr_err("Unable to register omapdss device\n");
	306	return r;
	307	}
	308
	309	/* create devices for dss hwmods */
cf07f531	310
179e0453 AT	311	if (cpu_is_omap24xx()) {
	312	curr_dss_hwmod = omap2_dss_hwmod_data;
	313	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	314	} else if (cpu_is_omap34xx()) {
	315	curr_dss_hwmod = omap3_dss_hwmod_data;
	316	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	317	} else {
	318	curr_dss_hwmod = omap4_dss_hwmod_data;
	319	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	320	}
545376e7	321
966eaed0 TV	322	/*
	323	* First create the pdev for dss_core, which is used as a parent device
	324	* by the other dss pdevs. Note: dss_core has to be the first item in
	325	* the hwmod list.
	326	*/
	327	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
	328	curr_dss_hwmod[0].id,
	329	curr_dss_hwmod[0].oh_name,
35deca3d	330	board_data, sizeof(*board_data),
966eaed0	331	NULL);
fd4b34f6	332
966eaed0 TV	333	if (IS_ERR(dss_pdev)) {
	334	pr_err("Could not build omap_device for %s\n",
	335	curr_dss_hwmod[0].oh_name);
	336
	337	return PTR_ERR(dss_pdev);
	338	}
	339
	340	for (i = 1; i < oh_count; i++) {
	341	pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
	342	curr_dss_hwmod[i].id,
	343	curr_dss_hwmod[i].oh_name,
35deca3d	344	board_data, sizeof(*board_data),
966eaed0 TV	345	dss_pdev);
	346
	347	if (IS_ERR(pdev)) {
	348	pr_err("Could not build omap_device for %s\n",
	349	curr_dss_hwmod[i].oh_name);
cf07f531	350
966eaed0 TV	351	return PTR_ERR(pdev);
966eaed0 TV	352	}
cf07f531	353	}
b7ee79ab	354
53f576a8 TV	355	/* Create devices for DPI and SDI */
53f576a8 TV	356
35deca3d TV	357	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
35deca3d TV	358	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	359	if (IS_ERR(pdev)) {
	360	pr_err("Could not build platform_device for omapdss_dpi\n");
	361	return PTR_ERR(pdev);
	362	}
	363
	364	if (cpu_is_omap34xx()) {
35deca3d TV	365	pdev = create_simple_dss_pdev("omapdss_sdi", -1,
35deca3d TV	366	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	367	if (IS_ERR(pdev)) {
	368	pr_err("Could not build platform_device for omapdss_sdi\n");
	369	return PTR_ERR(pdev);
	370	}
	371	}
	372
00928eaf	373	return 0;
b7ee79ab	374	}
13662dc5	375
b923d40d AT	376	static void dispc_disable_outputs(void)
	377	{
	378	u32 v, irq_mask = 0;
	379	bool lcd_en, digit_en, lcd2_en = false;
	380	int i;
	381	struct omap_dss_dispc_dev_attr *da;
	382	struct omap_hwmod *oh;
	383
	384	oh = omap_hwmod_lookup("dss_dispc");
	385	if (!oh) {
	386	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	387	return;
	388	}
	389
	390	if (!oh->dev_attr) {
	391	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	392	return;
	393	}
	394
	395	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	396
	397	/* store value of LCDENABLE and DIGITENABLE bits */
	398	v = omap_hwmod_read(oh, DISPC_CONTROL);
	399	lcd_en = v & LCD_EN_MASK;
	400	digit_en = v & DIGIT_EN_MASK;
	401
	402	/* store value of LCDENABLE for LCD2 */
	403	if (da->manager_count > 2) {
	404	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	405	lcd2_en = v & LCD_EN_MASK;
	406	}
	407
	408	if (!(lcd_en \| digit_en \| lcd2_en))
	409	return; /* no managers currently enabled */
	410
	411	/*
	412	* If any manager was enabled, we need to disable it before
	413	* DSS clocks are disabled or DISPC module is reset
	414	*/
	415	if (lcd_en)
	416	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	417
	418	if (digit_en) {
	419	if (da->has_framedonetv_irq) {
	420	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	421	} else {
	422	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	423	1 << EVSYNC_ODD_IRQ_SHIFT;
	424	}
	425	}
	426
	427	if (lcd2_en)
	428	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
	429
	430	/*
	431	* clear any previous FRAMEDONE, FRAMEDONETV,
	432	* EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
	433	*/
	434	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	435
	436	/* disable LCD and TV managers */
	437	v = omap_hwmod_read(oh, DISPC_CONTROL);
	438	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	439	omap_hwmod_write(v, oh, DISPC_CONTROL);
440
441	/* disable LCD2 manager */
442	if (da->manager_count > 2) {
443	v = omap_hwmod_read(oh, DISPC_CONTROL2);
444	v &= ~LCD_EN_MASK;
445	omap_hwmod_write(v, oh, DISPC_CONTROL2);
446	}
447
448	i = 0;
449	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
450	irq_mask) {
451	i++;
452	if (i > FRAMEDONE_IRQ_TIMEOUT) {
453	pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
454	break;
455	}
456	mdelay(1);
457	}
458	}
459
13662dc5 TV	460	#define MAX_MODULE_SOFTRESET_WAIT 10000
	461	int omap_dss_reset(struct omap_hwmod *oh)
	462	{
	463	struct omap_hwmod_opt_clk *oc;
	464	int c = 0;
	465	int i, r;
	466
	467	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	468	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	469	return -EINVAL;
	470	}
	471
	472	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	473	if (oc->_clk)
	474	clk_enable(oc->_clk);
	475
b923d40d AT	476	dispc_disable_outputs();
	477
	478	/* clear SDI registers */
	479	if (cpu_is_omap3430()) {
	480	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	481	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	482	}
	483
	484	/*
	485	* clear DSS_CONTROL register to switch DSS clock sources to
	486	* PRCM clock, if any
	487	*/
	488	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	489
13662dc5 TV	490	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	491	& SYSS_RESETDONE_MASK),
	492	MAX_MODULE_SOFTRESET_WAIT, c);
	493
	494	if (c == MAX_MODULE_SOFTRESET_WAIT)
	495	pr_warning("dss_core: waiting for reset to finish failed\n");
	496	else
	497	pr_debug("dss_core: softreset done\n");
	498
	499	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	500	if (oc->_clk)
	501	clk_disable(oc->_clk);
	502
	503	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	504
	505	return r;
	506	}