[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>

#include <video/omapdss.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
#include "common.h"

#include "soc.h"
#include "iomap.h"
#include "mux.h"
#include "control.h"
#include "display.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_CONTROL3		0x0848
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONE3_IRQ_SHIFT	30
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
{
	u32 reg;
	u16 control_i2c_1;

	omap_mux_init_signal("hdmi_cec",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_scl",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_sda",
			OMAP_PIN_INPUT_PULLUP);

	/*
	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	 * internal pull up resistor.
	 */
	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
		control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
		reg = omap4_ctrl_pad_readl(control_i2c_1);
		reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
			OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
			omap4_ctrl_pad_writel(reg, control_i2c_1);
	}
}

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	return 0;
}

int __init omap_hdmi_init(enum omap_hdmi_flags flags)
{
	if (cpu_is_omap44xx())
		omap4_hdmi_mux_pads(flags);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static struct platform_device *create_dss_pdev(const char *pdev_name,
		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	struct omap_device *od;
	struct omap_hwmod *ohs[1];
	struct omap_hwmod *oh;
	int r;

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		r = -ENODEV;
		goto err;
	}

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	ohs[0] = oh;
	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	if (IS_ERR(od)) {
		pr_err("Could not alloc omap_device for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = omap_device_register(pdev);
	if (r) {
		pr_err("Could not register omap_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
		int pdev_id, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	int r;

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = platform_device_add(pdev);
	if (r) {
		pr_err("Could not register platform_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static enum omapdss_version __init omap_display_get_version(void)
{
	if (cpu_is_omap24xx())
		return OMAPDSS_VER_OMAP24xx;
	else if (cpu_is_omap3630())
		return OMAPDSS_VER_OMAP3630;
	else if (cpu_is_omap34xx()) {
		if (soc_is_am35xx()) {
			return OMAPDSS_VER_AM35xx;
		} else {
			if (omap_rev() < OMAP3430_REV_ES3_0)
				return OMAPDSS_VER_OMAP34xx_ES1;
			else
				return OMAPDSS_VER_OMAP34xx_ES3;
		}
	} else if (omap_rev() == OMAP4430_REV_ES1_0)
		return OMAPDSS_VER_OMAP4430_ES1;
	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
			omap_rev() == OMAP4430_REV_ES2_1 ||
			omap_rev() == OMAP4430_REV_ES2_2)
		return OMAPDSS_VER_OMAP4430_ES2;
	else if (cpu_is_omap44xx())
		return OMAPDSS_VER_OMAP4;
	else if (soc_is_omap54xx())
		return OMAPDSS_VER_OMAP5;
	else
		return OMAPDSS_VER_UNKNOWN;
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct platform_device *pdev;
	int i, oh_count;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;
	struct platform_device *dss_pdev;
	enum omapdss_version ver;

	/* create omapdss device */

	ver = omap_display_get_version();

	if (ver == OMAPDSS_VER_UNKNOWN) {
		pr_err("DSS not supported on this SoC\n");
		return -ENODEV;
	}

	board_data->version = ver;
	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;

	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create devices for dss hwmods */

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	/*
	 * First create the pdev for dss_core, which is used as a parent device
	 * by the other dss pdevs. Note: dss_core has to be the first item in
	 * the hwmod list.
	 */
	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
			curr_dss_hwmod[0].id,
			curr_dss_hwmod[0].oh_name,
			board_data, sizeof(*board_data),
			NULL);

	if (IS_ERR(dss_pdev)) {
		pr_err("Could not build omap_device for %s\n",
				curr_dss_hwmod[0].oh_name);

		return PTR_ERR(dss_pdev);
	}

	for (i = 1; i < oh_count; i++) {
		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id,
				curr_dss_hwmod[i].oh_name,
				board_data, sizeof(*board_data),
				dss_pdev);

		if (IS_ERR(pdev)) {
			pr_err("Could not build omap_device for %s\n",
					curr_dss_hwmod[i].oh_name);

			return PTR_ERR(pdev);
		}
	}

	/* Create devices for DPI and SDI */

	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
			board_data, sizeof(*board_data), dss_pdev);
	if (IS_ERR(pdev)) {
		pr_err("Could not build platform_device for omapdss_dpi\n");
		return PTR_ERR(pdev);
	}

	if (cpu_is_omap34xx()) {
		pdev = create_simple_dss_pdev("omapdss_sdi", -1,
				board_data, sizeof(*board_data), dss_pdev);
		if (IS_ERR(pdev)) {
			pr_err("Could not build platform_device for omapdss_sdi\n");
			return PTR_ERR(pdev);
		}
	}

	return 0;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	/* store value of LCDENABLE for LCD3 */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		lcd3_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
	if (lcd3_en)
		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	/* disable LCD3 manager */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL3);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

#define MAX_MODULE_SOFTRESET_WAIT	10000
int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_prepare_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable_unprepare(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
b7ee79ab	26
a0b38cc4	27	#include <video/omapdss.h>
2a296c8f	28	#include "omap_hwmod.h"
25c7d49e	29	#include "omap_device.h"
1d5aef49	30	#include "omap-pm.h"
deee6d53	31	#include "common.h"
b7ee79ab	32
e4c060db	33	#include "soc.h"
ee0839c2	34	#include "iomap.h"
ee9dfd82	35	#include "mux.h"
dc35835c	36	#include "control.h"
b923d40d AT	37	#include "display.h"
	38
	39	#define DISPC_CONTROL 0x0040
	40	#define DISPC_CONTROL2 0x0238
465698ee	41	#define DISPC_CONTROL3 0x0848
b923d40d AT	42	#define DISPC_IRQSTATUS 0x0018
	43
	44	#define DSS_SYSCONFIG 0x10
	45	#define DSS_SYSSTATUS 0x14
	46	#define DSS_CONTROL 0x40
	47	#define DSS_SDI_CONTROL 0x44
	48	#define DSS_PLL_CONTROL 0x48
	49
	50	#define LCD_EN_MASK (0x1 << 0)
	51	#define DIGIT_EN_MASK (0x1 << 1)
	52
	53	#define FRAMEDONE_IRQ_SHIFT 0
	54	#define EVSYNC_EVEN_IRQ_SHIFT 2
	55	#define EVSYNC_ODD_IRQ_SHIFT 3
	56	#define FRAMEDONE2_IRQ_SHIFT 22
465698ee	57	#define FRAMEDONE3_IRQ_SHIFT 30
b923d40d AT	58	#define FRAMEDONETV_IRQ_SHIFT 24
	59
	60	/*
	61	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	62	* reset before deciding that something has gone wrong
	63	*/
	64	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	65
b7ee79ab SS	66	static struct platform_device omap_display_device = {
	67	.name = "omapdss",
	68	.id = -1,
	69	.dev = {
	70	.platform_data = NULL,
	71	},
	72	};
	73
179e0453 AT	74	struct omap_dss_hwmod_data {
	75	const char *oh_name;
	76	const char *dev_name;
	77	const int id;
	78	};
	79
bcad6dc3	80	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
179e0453 AT	81	{ "dss_core", "omapdss_dss", -1 },
	82	{ "dss_dispc", "omapdss_dispc", -1 },
	83	{ "dss_rfbi", "omapdss_rfbi", -1 },
	84	{ "dss_venc", "omapdss_venc", -1 },
	85	};
	86
bcad6dc3	87	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
179e0453 AT	88	{ "dss_core", "omapdss_dss", -1 },
	89	{ "dss_dispc", "omapdss_dispc", -1 },
	90	{ "dss_rfbi", "omapdss_rfbi", -1 },
	91	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	92	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	93	};
179e0453 AT	94
bcad6dc3	95	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
179e0453 AT	96	{ "dss_core", "omapdss_dss", -1 },
	97	{ "dss_dispc", "omapdss_dispc", -1 },
	98	{ "dss_rfbi", "omapdss_rfbi", -1 },
7c68dd96 TV	99	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	100	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	101	{ "dss_hdmi", "omapdss_hdmi", -1 },
	102	};
	103
e8a30b25	104	static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
ee9dfd82	105	{
9a901683 M	106	u32 reg;
	107	u16 control_i2c_1;
	108
ee9dfd82 M	109	omap_mux_init_signal("hdmi_cec",
ee9dfd82 M	110	OMAP_PIN_INPUT_PULLUP);
ee9dfd82 M	111	omap_mux_init_signal("hdmi_ddc_scl",
	112	OMAP_PIN_INPUT_PULLUP);
	113	omap_mux_init_signal("hdmi_ddc_sda",
	114	OMAP_PIN_INPUT_PULLUP);
9a901683 M	115
	116	/*
	117	* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	118	* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	119	* internal pull up resistor.
	120	*/
	121	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
	122	control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
	123	reg = omap4_ctrl_pad_readl(control_i2c_1);
	124	reg \|= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK \|
	125	OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
	126	omap4_ctrl_pad_writel(reg, control_i2c_1);
	127	}
ee9dfd82 M	128	}
ee9dfd82 M	129
e8a30b25	130	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
dc35835c TV	131	{
	132	u32 enable_mask, enable_shift;
	133	u32 pipd_mask, pipd_shift;
	134	u32 reg;
	135
	136	if (dsi_id == 0) {
	137	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	138	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	139	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	140	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	141	} else if (dsi_id == 1) {
	142	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	143	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	144	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	145	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	146	} else {
	147	return -ENODEV;
	148	}
	149
	150	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	151
	152	reg &= ~enable_mask;
	153	reg &= ~pipd_mask;
	154
	155	reg \|= (lanes << enable_shift) & enable_mask;
	156	reg \|= (lanes << pipd_shift) & pipd_mask;
	157
	158	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	159
	160	return 0;
	161	}
	162
d1589f09	163	int __init omap_hdmi_init(enum omap_hdmi_flags flags)
ee9dfd82 M	164	{
ee9dfd82 M	165	if (cpu_is_omap44xx())
9a901683	166	omap4_hdmi_mux_pads(flags);
ee9dfd82 M	167
	168	return 0;
	169	}
	170
e8a30b25	171	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	172	{
dc35835c TV	173	if (cpu_is_omap44xx())
	174	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	175
5bc416cb TV	176	return 0;
	177	}
	178
e8a30b25	179	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	180	{
dc35835c TV	181	if (cpu_is_omap44xx())
dc35835c TV	182	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	183	}
5bc416cb TV	184
62c1dcfc TV	185	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	186	{
	187	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	188	}
	189
966eaed0 TV	190	static struct platform_device create_dss_pdev(const char pdev_name,
	191	int pdev_id, const char oh_name, void pdata, int pdata_len,
	192	struct platform_device *parent)
	193	{
	194	struct platform_device *pdev;
	195	struct omap_device *od;
	196	struct omap_hwmod *ohs[1];
	197	struct omap_hwmod *oh;
	198	int r;
	199
	200	oh = omap_hwmod_lookup(oh_name);
	201	if (!oh) {
	202	pr_err("Could not look up %s\n", oh_name);
	203	r = -ENODEV;
	204	goto err;
	205	}
	206
	207	pdev = platform_device_alloc(pdev_name, pdev_id);
	208	if (!pdev) {
	209	pr_err("Could not create pdev for %s\n", pdev_name);
	210	r = -ENOMEM;
	211	goto err;
	212	}
	213
	214	if (parent != NULL)
	215	pdev->dev.parent = &parent->dev;
	216
	217	if (pdev->id != -1)
	218	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	219	else
	220	dev_set_name(&pdev->dev, "%s", pdev->name);
	221
	222	ohs[0] = oh;
	223	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
9ee67723	224	if (IS_ERR(od)) {
966eaed0 TV	225	pr_err("Could not alloc omap_device for %s\n", pdev_name);
	226	r = -ENOMEM;
	227	goto err;
	228	}
	229
	230	r = platform_device_add_data(pdev, pdata, pdata_len);
	231	if (r) {
	232	pr_err("Could not set pdata for %s\n", pdev_name);
	233	goto err;
	234	}
	235
	236	r = omap_device_register(pdev);
	237	if (r) {
	238	pr_err("Could not register omap_device for %s\n", pdev_name);
	239	goto err;
	240	}
	241
	242	return pdev;
	243
	244	err:
	245	return ERR_PTR(r);
	246	}
	247
53f576a8 TV	248	static struct platform_device create_simple_dss_pdev(const char pdev_name,
	249	int pdev_id, void *pdata, int pdata_len,
	250	struct platform_device *parent)
	251	{
	252	struct platform_device *pdev;
	253	int r;
	254
	255	pdev = platform_device_alloc(pdev_name, pdev_id);
	256	if (!pdev) {
	257	pr_err("Could not create pdev for %s\n", pdev_name);
	258	r = -ENOMEM;
	259	goto err;
	260	}
	261
	262	if (parent != NULL)
	263	pdev->dev.parent = &parent->dev;
	264
	265	if (pdev->id != -1)
	266	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	267	else
	268	dev_set_name(&pdev->dev, "%s", pdev->name);
	269
	270	r = platform_device_add_data(pdev, pdata, pdata_len);
	271	if (r) {
	272	pr_err("Could not set pdata for %s\n", pdev_name);
	273	goto err;
	274	}
	275
c3a21fc7	276	r = platform_device_add(pdev);
53f576a8	277	if (r) {
c3a21fc7	278	pr_err("Could not register platform_device for %s\n", pdev_name);
53f576a8 TV	279	goto err;
	280	}
	281
	282	return pdev;
	283
	284	err:
	285	return ERR_PTR(r);
	286	}
	287
acd18af9 TV	288	static enum omapdss_version __init omap_display_get_version(void)
	289	{
	290	if (cpu_is_omap24xx())
	291	return OMAPDSS_VER_OMAP24xx;
	292	else if (cpu_is_omap3630())
	293	return OMAPDSS_VER_OMAP3630;
	294	else if (cpu_is_omap34xx()) {
	295	if (soc_is_am35xx()) {
	296	return OMAPDSS_VER_AM35xx;
	297	} else {
	298	if (omap_rev() < OMAP3430_REV_ES3_0)
	299	return OMAPDSS_VER_OMAP34xx_ES1;
	300	else
	301	return OMAPDSS_VER_OMAP34xx_ES3;
	302	}
	303	} else if (omap_rev() == OMAP4430_REV_ES1_0)
	304	return OMAPDSS_VER_OMAP4430_ES1;
	305	else if (omap_rev() == OMAP4430_REV_ES2_0 \|\|
	306	omap_rev() == OMAP4430_REV_ES2_1 \|\|
	307	omap_rev() == OMAP4430_REV_ES2_2)
	308	return OMAPDSS_VER_OMAP4430_ES2;
	309	else if (cpu_is_omap44xx())
	310	return OMAPDSS_VER_OMAP4;
	311	else if (soc_is_omap54xx())
	312	return OMAPDSS_VER_OMAP5;
	313	else
	314	return OMAPDSS_VER_UNKNOWN;
	315	}
	316
b7ee79ab SS	317	int __init omap_display_init(struct omap_dss_board_info *board_data)
	318	{
	319	int r = 0;
3528c58e	320	struct platform_device *pdev;
179e0453	321	int i, oh_count;
179e0453	322	const struct omap_dss_hwmod_data *curr_dss_hwmod;
966eaed0	323	struct platform_device *dss_pdev;
acd18af9	324	enum omapdss_version ver;
cf07f531	325
00928eaf TV	326	/* create omapdss device */
00928eaf TV	327
acd18af9 TV	328	ver = omap_display_get_version();
	329
	330	if (ver == OMAPDSS_VER_UNKNOWN) {
	331	pr_err("DSS not supported on this SoC\n");
	332	return -ENODEV;
	333	}
	334
	335	board_data->version = ver;
00928eaf TV	336	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	337	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	338	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	339	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
	340
	341	omap_display_device.dev.platform_data = board_data;
	342
	343	r = platform_device_register(&omap_display_device);
	344	if (r < 0) {
	345	pr_err("Unable to register omapdss device\n");
	346	return r;
	347	}
	348
	349	/* create devices for dss hwmods */
cf07f531	350
179e0453 AT	351	if (cpu_is_omap24xx()) {
	352	curr_dss_hwmod = omap2_dss_hwmod_data;
	353	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	354	} else if (cpu_is_omap34xx()) {
	355	curr_dss_hwmod = omap3_dss_hwmod_data;
	356	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	357	} else {
	358	curr_dss_hwmod = omap4_dss_hwmod_data;
	359	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	360	}
545376e7	361
966eaed0 TV	362	/*
	363	* First create the pdev for dss_core, which is used as a parent device
	364	* by the other dss pdevs. Note: dss_core has to be the first item in
	365	* the hwmod list.
	366	*/
	367	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
	368	curr_dss_hwmod[0].id,
	369	curr_dss_hwmod[0].oh_name,
35deca3d	370	board_data, sizeof(*board_data),
966eaed0	371	NULL);
fd4b34f6	372
966eaed0 TV	373	if (IS_ERR(dss_pdev)) {
	374	pr_err("Could not build omap_device for %s\n",
	375	curr_dss_hwmod[0].oh_name);
	376
	377	return PTR_ERR(dss_pdev);
	378	}
	379
	380	for (i = 1; i < oh_count; i++) {
	381	pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
	382	curr_dss_hwmod[i].id,
	383	curr_dss_hwmod[i].oh_name,
35deca3d	384	board_data, sizeof(*board_data),
966eaed0 TV	385	dss_pdev);
	386
	387	if (IS_ERR(pdev)) {
	388	pr_err("Could not build omap_device for %s\n",
	389	curr_dss_hwmod[i].oh_name);
cf07f531	390
966eaed0 TV	391	return PTR_ERR(pdev);
966eaed0 TV	392	}
cf07f531	393	}
b7ee79ab	394
53f576a8 TV	395	/* Create devices for DPI and SDI */
53f576a8 TV	396
35deca3d TV	397	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
35deca3d TV	398	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	399	if (IS_ERR(pdev)) {
	400	pr_err("Could not build platform_device for omapdss_dpi\n");
	401	return PTR_ERR(pdev);
	402	}
	403
	404	if (cpu_is_omap34xx()) {
35deca3d TV	405	pdev = create_simple_dss_pdev("omapdss_sdi", -1,
35deca3d TV	406	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	407	if (IS_ERR(pdev)) {
	408	pr_err("Could not build platform_device for omapdss_sdi\n");
	409	return PTR_ERR(pdev);
	410	}
	411	}
	412
00928eaf	413	return 0;
b7ee79ab	414	}
13662dc5	415
b923d40d AT	416	static void dispc_disable_outputs(void)
	417	{
	418	u32 v, irq_mask = 0;
465698ee	419	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
b923d40d AT	420	int i;
	421	struct omap_dss_dispc_dev_attr *da;
	422	struct omap_hwmod *oh;
	423
	424	oh = omap_hwmod_lookup("dss_dispc");
	425	if (!oh) {
	426	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	427	return;
	428	}
	429
	430	if (!oh->dev_attr) {
	431	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	432	return;
	433	}
	434
	435	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	436
	437	/* store value of LCDENABLE and DIGITENABLE bits */
	438	v = omap_hwmod_read(oh, DISPC_CONTROL);
	439	lcd_en = v & LCD_EN_MASK;
	440	digit_en = v & DIGIT_EN_MASK;
	441
	442	/* store value of LCDENABLE for LCD2 */
	443	if (da->manager_count > 2) {
	444	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	445	lcd2_en = v & LCD_EN_MASK;
	446	}
	447
465698ee CM	448	/* store value of LCDENABLE for LCD3 */
	449	if (da->manager_count > 3) {
	450	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	451	lcd3_en = v & LCD_EN_MASK;
	452	}
	453
	454	if (!(lcd_en \| digit_en \| lcd2_en \| lcd3_en))
b923d40d AT	455	return; /* no managers currently enabled */
	456
	457	/*
	458	* If any manager was enabled, we need to disable it before
	459	* DSS clocks are disabled or DISPC module is reset
	460	*/
	461	if (lcd_en)
	462	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	463
	464	if (digit_en) {
	465	if (da->has_framedonetv_irq) {
	466	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	467	} else {
	468	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	469	1 << EVSYNC_ODD_IRQ_SHIFT;
	470	}
	471	}
	472
	473	if (lcd2_en)
	474	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
465698ee CM	475	if (lcd3_en)
465698ee CM	476	irq_mask \|= 1 << FRAMEDONE3_IRQ_SHIFT;
b923d40d AT	477
	478	/*
	479	* clear any previous FRAMEDONE, FRAMEDONETV,
465698ee	480	* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
b923d40d AT	481	*/
	482	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	483
	484	/* disable LCD and TV managers */
	485	v = omap_hwmod_read(oh, DISPC_CONTROL);
	486	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	487	omap_hwmod_write(v, oh, DISPC_CONTROL);
	488
	489	/* disable LCD2 manager */
	490	if (da->manager_count > 2) {
	491	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	492	v &= ~LCD_EN_MASK;
	493	omap_hwmod_write(v, oh, DISPC_CONTROL2);
	494	}
	495
465698ee CM	496	/* disable LCD3 manager */
	497	if (da->manager_count > 3) {
	498	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	499	v &= ~LCD_EN_MASK;
	500	omap_hwmod_write(v, oh, DISPC_CONTROL3);
	501	}
	502
b923d40d AT	503	i = 0;
	504	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	505	irq_mask) {
	506	i++;
	507	if (i > FRAMEDONE_IRQ_TIMEOUT) {
465698ee	508	pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
b923d40d AT	509	break;
	510	}
	511	mdelay(1);
	512	}
	513	}
	514
13662dc5 TV	515	#define MAX_MODULE_SOFTRESET_WAIT 10000
	516	int omap_dss_reset(struct omap_hwmod *oh)
	517	{
	518	struct omap_hwmod_opt_clk *oc;
	519	int c = 0;
	520	int i, r;
	521
	522	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	523	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	524	return -EINVAL;
	525	}
	526
	527	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	528	if (oc->_clk)
4d7cb45e	529	clk_prepare_enable(oc->_clk);
13662dc5	530
b923d40d AT	531	dispc_disable_outputs();
	532
	533	/* clear SDI registers */
	534	if (cpu_is_omap3430()) {
	535	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	536	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	537	}
	538
	539	/*
	540	* clear DSS_CONTROL register to switch DSS clock sources to
	541	* PRCM clock, if any
	542	*/
	543	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	544
13662dc5 TV	545	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	546	& SYSS_RESETDONE_MASK),
	547	MAX_MODULE_SOFTRESET_WAIT, c);
	548
	549	if (c == MAX_MODULE_SOFTRESET_WAIT)
	550	pr_warning("dss_core: waiting for reset to finish failed\n");
	551	else
	552	pr_debug("dss_core: softreset done\n");
	553
	554	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	555	if (oc->_clk)
4d7cb45e	556	clk_disable_unprepare(oc->_clk);
13662dc5 TV	557
	558	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	559
	560	return r;
	561	}