[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <video/omapdss.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>
#include <plat/common.h>

#include "mux.h"
#include "control.h"
#include "display.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

static void omap4_hdmi_mux_pads()
{
	/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
	omap_mux_init_signal("hdmi_hpd",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_cec",
			OMAP_PIN_INPUT_PULLUP);
	/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
	omap_mux_init_signal("hdmi_ddc_scl",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_sda",
			OMAP_PIN_INPUT_PULLUP);
}

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	return 0;
}

int omap_hdmi_init(void)
{
	if (cpu_is_omap44xx())
		omap4_hdmi_mux_pads();

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct omap_hwmod *oh;
	struct platform_device *pdev;
	int i, oh_count;
	struct omap_display_platform_data pdata;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;

	memset(&pdata, 0, sizeof(pdata));

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	if (board_data->dsi_enable_pads == NULL)
		board_data->dsi_enable_pads = omap_dsi_enable_pads;
	if (board_data->dsi_disable_pads == NULL)
		board_data->dsi_disable_pads = omap_dsi_disable_pads;

	pdata.board_data = board_data;
	pdata.board_data->get_context_loss_count =
		omap_pm_get_dev_context_loss_count;

	for (i = 0; i < oh_count; i++) {
		oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
		if (!oh) {
			pr_err("Could not look up %s\n",
				curr_dss_hwmod[i].oh_name);
			return -ENODEV;
		}

		pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id, oh, &pdata,
				sizeof(struct omap_display_platform_data),
				NULL, 0, 0);

		if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
				curr_dss_hwmod[i].oh_name))
			return -ENODEV;
	}
	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0)
		printk(KERN_ERR "Unable to register OMAP-Display device\n");

	return r;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

#define MAX_MODULE_SOFTRESET_WAIT	10000
int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
	25
a0b38cc4	26	#include <video/omapdss.h>
cf07f531 SG	27	#include <plat/omap_hwmod.h>
cf07f531 SG	28	#include <plat/omap_device.h>
700dee78	29	#include <plat/omap-pm.h>
13662dc5	30	#include <plat/common.h>
b7ee79ab	31
ee9dfd82	32	#include "mux.h"
dc35835c	33	#include "control.h"
b923d40d AT	34	#include "display.h"
	35
	36	#define DISPC_CONTROL 0x0040
	37	#define DISPC_CONTROL2 0x0238
	38	#define DISPC_IRQSTATUS 0x0018
	39
	40	#define DSS_SYSCONFIG 0x10
	41	#define DSS_SYSSTATUS 0x14
	42	#define DSS_CONTROL 0x40
	43	#define DSS_SDI_CONTROL 0x44
	44	#define DSS_PLL_CONTROL 0x48
	45
	46	#define LCD_EN_MASK (0x1 << 0)
	47	#define DIGIT_EN_MASK (0x1 << 1)
	48
	49	#define FRAMEDONE_IRQ_SHIFT 0
	50	#define EVSYNC_EVEN_IRQ_SHIFT 2
	51	#define EVSYNC_ODD_IRQ_SHIFT 3
	52	#define FRAMEDONE2_IRQ_SHIFT 22
	53	#define FRAMEDONETV_IRQ_SHIFT 24
	54
	55	/*
	56	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	57	* reset before deciding that something has gone wrong
	58	*/
	59	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	60
b7ee79ab SS	61	static struct platform_device omap_display_device = {
	62	.name = "omapdss",
	63	.id = -1,
	64	.dev = {
	65	.platform_data = NULL,
	66	},
	67	};
	68
179e0453 AT	69	struct omap_dss_hwmod_data {
	70	const char *oh_name;
	71	const char *dev_name;
	72	const int id;
	73	};
	74
	75	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
	76	{ "dss_core", "omapdss_dss", -1 },
	77	{ "dss_dispc", "omapdss_dispc", -1 },
	78	{ "dss_rfbi", "omapdss_rfbi", -1 },
	79	{ "dss_venc", "omapdss_venc", -1 },
	80	};
	81
	82	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
	83	{ "dss_core", "omapdss_dss", -1 },
	84	{ "dss_dispc", "omapdss_dispc", -1 },
	85	{ "dss_rfbi", "omapdss_rfbi", -1 },
	86	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	87	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	88	};
	89
	90	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
	91	{ "dss_core", "omapdss_dss", -1 },
	92	{ "dss_dispc", "omapdss_dispc", -1 },
	93	{ "dss_rfbi", "omapdss_rfbi", -1 },
	94	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96 TV	95	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	96	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	97	{ "dss_hdmi", "omapdss_hdmi", -1 },
	98	};
	99
ee9dfd82 M	100	static void omap4_hdmi_mux_pads()
	101	{
	102	/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
	103	omap_mux_init_signal("hdmi_hpd",
	104	OMAP_PIN_INPUT_PULLUP);
	105	omap_mux_init_signal("hdmi_cec",
	106	OMAP_PIN_INPUT_PULLUP);
	107	/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
	108	omap_mux_init_signal("hdmi_ddc_scl",
	109	OMAP_PIN_INPUT_PULLUP);
	110	omap_mux_init_signal("hdmi_ddc_sda",
	111	OMAP_PIN_INPUT_PULLUP);
	112	}
	113
dc35835c TV	114	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
	115	{
	116	u32 enable_mask, enable_shift;
	117	u32 pipd_mask, pipd_shift;
	118	u32 reg;
	119
	120	if (dsi_id == 0) {
	121	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	122	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	123	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	124	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	125	} else if (dsi_id == 1) {
	126	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	127	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	128	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	129	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	130	} else {
	131	return -ENODEV;
	132	}
	133
	134	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	135
	136	reg &= ~enable_mask;
	137	reg &= ~pipd_mask;
	138
	139	reg \|= (lanes << enable_shift) & enable_mask;
	140	reg \|= (lanes << pipd_shift) & pipd_mask;
	141
	142	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	143
	144	return 0;
	145	}
	146
ee9dfd82 M	147	int omap_hdmi_init(void)
	148	{
	149	if (cpu_is_omap44xx())
	150	omap4_hdmi_mux_pads();
	151
	152	return 0;
	153	}
	154
5bc416cb TV	155	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb TV	156	{
dc35835c TV	157	if (cpu_is_omap44xx())
	158	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	159
5bc416cb TV	160	return 0;
	161	}
	162
	163	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
	164	{
dc35835c TV	165	if (cpu_is_omap44xx())
dc35835c TV	166	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	167	}
5bc416cb TV	168
b7ee79ab SS	169	int __init omap_display_init(struct omap_dss_board_info *board_data)
	170	{
	171	int r = 0;
cf07f531	172	struct omap_hwmod *oh;
3528c58e	173	struct platform_device *pdev;
179e0453	174	int i, oh_count;
cf07f531	175	struct omap_display_platform_data pdata;
179e0453	176	const struct omap_dss_hwmod_data *curr_dss_hwmod;
cf07f531 SG	177
	178	memset(&pdata, 0, sizeof(pdata));
	179
179e0453 AT	180	if (cpu_is_omap24xx()) {
	181	curr_dss_hwmod = omap2_dss_hwmod_data;
	182	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	183	} else if (cpu_is_omap34xx()) {
	184	curr_dss_hwmod = omap3_dss_hwmod_data;
	185	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	186	} else {
	187	curr_dss_hwmod = omap4_dss_hwmod_data;
	188	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	189	}
545376e7	190
5bc416cb TV	191	if (board_data->dsi_enable_pads == NULL)
	192	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	193	if (board_data->dsi_disable_pads == NULL)
	194	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	195
cf07f531	196	pdata.board_data = board_data;
700dee78 TV	197	pdata.board_data->get_context_loss_count =
700dee78 TV	198	omap_pm_get_dev_context_loss_count;
cf07f531 SG	199
cf07f531 SG	200	for (i = 0; i < oh_count; i++) {
179e0453	201	oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
cf07f531	202	if (!oh) {
179e0453 AT	203	pr_err("Could not look up %s\n",
179e0453 AT	204	curr_dss_hwmod[i].oh_name);
cf07f531 SG	205	return -ENODEV;
cf07f531 SG	206	}
fd4b34f6	207
3528c58e	208	pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
179e0453	209	curr_dss_hwmod[i].id, oh, &pdata,
cf07f531	210	sizeof(struct omap_display_platform_data),
f718e2c0	211	NULL, 0, 0);
cf07f531	212
3528c58e	213	if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
179e0453	214	curr_dss_hwmod[i].oh_name))
cf07f531 SG	215	return -ENODEV;
cf07f531 SG	216	}
b7ee79ab SS	217	omap_display_device.dev.platform_data = board_data;
	218
	219	r = platform_device_register(&omap_display_device);
	220	if (r < 0)
	221	printk(KERN_ERR "Unable to register OMAP-Display device\n");
	222
	223	return r;
	224	}
13662dc5	225
b923d40d AT	226	static void dispc_disable_outputs(void)
	227	{
	228	u32 v, irq_mask = 0;
	229	bool lcd_en, digit_en, lcd2_en = false;
	230	int i;
	231	struct omap_dss_dispc_dev_attr *da;
	232	struct omap_hwmod *oh;
	233
	234	oh = omap_hwmod_lookup("dss_dispc");
	235	if (!oh) {
	236	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	237	return;
	238	}
	239
	240	if (!oh->dev_attr) {
	241	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	242	return;
	243	}
	244
	245	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	246
	247	/* store value of LCDENABLE and DIGITENABLE bits */
	248	v = omap_hwmod_read(oh, DISPC_CONTROL);
	249	lcd_en = v & LCD_EN_MASK;
	250	digit_en = v & DIGIT_EN_MASK;
	251
	252	/* store value of LCDENABLE for LCD2 */
	253	if (da->manager_count > 2) {
	254	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	255	lcd2_en = v & LCD_EN_MASK;
	256	}
	257
	258	if (!(lcd_en \| digit_en \| lcd2_en))
	259	return; /* no managers currently enabled */
	260
	261	/*
	262	* If any manager was enabled, we need to disable it before
	263	* DSS clocks are disabled or DISPC module is reset
	264	*/
	265	if (lcd_en)
	266	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	267
	268	if (digit_en) {
	269	if (da->has_framedonetv_irq) {
	270	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	271	} else {
	272	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	273	1 << EVSYNC_ODD_IRQ_SHIFT;
	274	}
	275	}
	276
	277	if (lcd2_en)
	278	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
	279
	280	/*
	281	* clear any previous FRAMEDONE, FRAMEDONETV,
	282	* EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
	283	*/
	284	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	285
	286	/* disable LCD and TV managers */
	287	v = omap_hwmod_read(oh, DISPC_CONTROL);
	288	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	289	omap_hwmod_write(v, oh, DISPC_CONTROL);
290
291	/* disable LCD2 manager */
292	if (da->manager_count > 2) {
293	v = omap_hwmod_read(oh, DISPC_CONTROL2);
294	v &= ~LCD_EN_MASK;
295	omap_hwmod_write(v, oh, DISPC_CONTROL2);
296	}
297
298	i = 0;
299	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
300	irq_mask) {
301	i++;
302	if (i > FRAMEDONE_IRQ_TIMEOUT) {
303	pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
304	break;
305	}
306	mdelay(1);
307	}
308	}
309
13662dc5 TV	310	#define MAX_MODULE_SOFTRESET_WAIT 10000
	311	int omap_dss_reset(struct omap_hwmod *oh)
	312	{
	313	struct omap_hwmod_opt_clk *oc;
	314	int c = 0;
	315	int i, r;
	316
	317	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	318	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	319	return -EINVAL;
	320	}
	321
	322	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	323	if (oc->_clk)
	324	clk_enable(oc->_clk);
	325
b923d40d AT	326	dispc_disable_outputs();
	327
	328	/* clear SDI registers */
	329	if (cpu_is_omap3430()) {
	330	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	331	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	332	}
	333
	334	/*
	335	* clear DSS_CONTROL register to switch DSS clock sources to
	336	* PRCM clock, if any
	337	*/
	338	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	339
13662dc5 TV	340	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	341	& SYSS_RESETDONE_MASK),
	342	MAX_MODULE_SOFTRESET_WAIT, c);
	343
	344	if (c == MAX_MODULE_SOFTRESET_WAIT)
	345	pr_warning("dss_core: waiting for reset to finish failed\n");
	346	else
	347	pr_debug("dss_core: softreset done\n");
	348
	349	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	350	if (oc->_clk)
	351	clk_disable(oc->_clk);
	352
	353	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	354
	355	return r;
	356	}