Commit | Line | Data |
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a1391d27 RN |
1 | /* |
2 | * OMAP3/4 - specific DPLL control functions | |
3 | * | |
358965d7 RW |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
a1391d27 RN |
6 | * |
7 | * Written by Paul Walmsley | |
358965d7 RW |
8 | * Testing and integration fixes by Jouni Högander |
9 | * | |
10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth | |
11 | * Menon | |
a1391d27 RN |
12 | * |
13 | * Parts of this code are based on code written by | |
14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
a1391d27 RN |
21 | #include <linux/kernel.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/io.h> | |
a1391d27 | 28 | #include <linux/bitops.h> |
6d803ba7 | 29 | #include <linux/clkdev.h> |
a1391d27 | 30 | |
16975a79 | 31 | #include <plat/clock.h> |
a1391d27 | 32 | |
dbc04161 | 33 | #include "soc.h" |
a1391d27 | 34 | #include "clock.h" |
59fb659b | 35 | #include "cm2xxx_3xxx.h" |
a1391d27 RN |
36 | #include "cm-regbits-34xx.h" |
37 | ||
38 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | |
39 | #define DPLL_AUTOIDLE_DISABLE 0x0 | |
40 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | |
41 | ||
42 | #define MAX_DPLL_WAIT_TRIES 1000000 | |
43 | ||
60c3f651 | 44 | /* Private functions */ |
a1391d27 RN |
45 | |
46 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | |
47 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | |
48 | { | |
49 | const struct dpll_data *dd; | |
50 | u32 v; | |
51 | ||
52 | dd = clk->dpll_data; | |
53 | ||
54 | v = __raw_readl(dd->control_reg); | |
55 | v &= ~dd->enable_mask; | |
56 | v |= clken_bits << __ffs(dd->enable_mask); | |
57 | __raw_writel(v, dd->control_reg); | |
58 | } | |
59 | ||
60 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | |
61 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |
62 | { | |
63 | const struct dpll_data *dd; | |
64 | int i = 0; | |
65 | int ret = -EINVAL; | |
5dcc3b97 | 66 | const char *clk_name; |
a1391d27 RN |
67 | |
68 | dd = clk->dpll_data; | |
5dcc3b97 | 69 | clk_name = __clk_get_name(clk); |
a1391d27 RN |
70 | |
71 | state <<= __ffs(dd->idlest_mask); | |
72 | ||
73 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && | |
74 | i < MAX_DPLL_WAIT_TRIES) { | |
75 | i++; | |
76 | udelay(1); | |
77 | } | |
78 | ||
79 | if (i == MAX_DPLL_WAIT_TRIES) { | |
80 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | |
5dcc3b97 | 81 | clk_name, (state) ? "locked" : "bypassed"); |
a1391d27 RN |
82 | } else { |
83 | pr_debug("clock: %s transition to '%s' in %d loops\n", | |
5dcc3b97 | 84 | clk_name, (state) ? "locked" : "bypassed", i); |
a1391d27 RN |
85 | |
86 | ret = 0; | |
87 | } | |
88 | ||
89 | return ret; | |
90 | } | |
91 | ||
92 | /* From 3430 TRM ES2 4.7.6.2 */ | |
93 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | |
94 | { | |
95 | unsigned long fint; | |
96 | u16 f = 0; | |
97 | ||
5dcc3b97 | 98 | fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; |
a1391d27 RN |
99 | |
100 | pr_debug("clock: fint is %lu\n", fint); | |
101 | ||
102 | if (fint >= 750000 && fint <= 1000000) | |
103 | f = 0x3; | |
104 | else if (fint > 1000000 && fint <= 1250000) | |
105 | f = 0x4; | |
106 | else if (fint > 1250000 && fint <= 1500000) | |
107 | f = 0x5; | |
108 | else if (fint > 1500000 && fint <= 1750000) | |
109 | f = 0x6; | |
110 | else if (fint > 1750000 && fint <= 2100000) | |
111 | f = 0x7; | |
112 | else if (fint > 7500000 && fint <= 10000000) | |
113 | f = 0xB; | |
114 | else if (fint > 10000000 && fint <= 12500000) | |
115 | f = 0xC; | |
116 | else if (fint > 12500000 && fint <= 15000000) | |
117 | f = 0xD; | |
118 | else if (fint > 15000000 && fint <= 17500000) | |
119 | f = 0xE; | |
120 | else if (fint > 17500000 && fint <= 21000000) | |
121 | f = 0xF; | |
122 | else | |
123 | pr_debug("clock: unknown freqsel setting for %d\n", n); | |
124 | ||
125 | return f; | |
126 | } | |
127 | ||
a1391d27 RN |
128 | /* |
129 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | |
130 | * @clk: pointer to a DPLL struct clk | |
131 | * | |
132 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | |
133 | * readiness before returning. Will save and restore the DPLL's | |
134 | * autoidle state across the enable, per the CDP code. If the DPLL | |
135 | * locked successfully, return 0; if the DPLL did not lock in the time | |
136 | * allotted, or DPLL3 was passed in, return -EINVAL. | |
137 | */ | |
138 | static int _omap3_noncore_dpll_lock(struct clk *clk) | |
139 | { | |
55ffe163 | 140 | const struct dpll_data *dd; |
a1391d27 | 141 | u8 ai; |
55ffe163 VP |
142 | u8 state = 1; |
143 | int r = 0; | |
a1391d27 | 144 | |
5dcc3b97 | 145 | pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); |
a1391d27 | 146 | |
55ffe163 VP |
147 | dd = clk->dpll_data; |
148 | state <<= __ffs(dd->idlest_mask); | |
149 | ||
150 | /* Check if already locked */ | |
151 | if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state) | |
152 | goto done; | |
153 | ||
a1391d27 RN |
154 | ai = omap3_dpll_autoidle_read(clk); |
155 | ||
d76316fe VB |
156 | if (ai) |
157 | omap3_dpll_deny_idle(clk); | |
a1391d27 RN |
158 | |
159 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | |
160 | ||
161 | r = _omap3_wait_dpll_status(clk, 1); | |
162 | ||
163 | if (ai) | |
164 | omap3_dpll_allow_idle(clk); | |
165 | ||
55ffe163 | 166 | done: |
a1391d27 RN |
167 | return r; |
168 | } | |
169 | ||
170 | /* | |
171 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | |
172 | * @clk: pointer to a DPLL struct clk | |
173 | * | |
174 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | |
175 | * bypass mode, the DPLL's rate is set equal to its parent clock's | |
176 | * rate. Waits for the DPLL to report readiness before returning. | |
177 | * Will save and restore the DPLL's autoidle state across the enable, | |
178 | * per the CDP code. If the DPLL entered bypass mode successfully, | |
179 | * return 0; if the DPLL did not enter bypass in the time allotted, or | |
180 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | |
181 | * return -EINVAL. | |
182 | */ | |
183 | static int _omap3_noncore_dpll_bypass(struct clk *clk) | |
184 | { | |
185 | int r; | |
186 | u8 ai; | |
187 | ||
188 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | |
189 | return -EINVAL; | |
190 | ||
191 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | |
5dcc3b97 | 192 | __clk_get_name(clk)); |
a1391d27 RN |
193 | |
194 | ai = omap3_dpll_autoidle_read(clk); | |
195 | ||
196 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | |
197 | ||
198 | r = _omap3_wait_dpll_status(clk, 0); | |
199 | ||
200 | if (ai) | |
201 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
202 | |
203 | return r; | |
204 | } | |
205 | ||
206 | /* | |
207 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | |
208 | * @clk: pointer to a DPLL struct clk | |
209 | * | |
210 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | |
211 | * restore the DPLL's autoidle state across the stop, per the CDP | |
212 | * code. If DPLL3 was passed in, or the DPLL does not support | |
213 | * low-power stop, return -EINVAL; otherwise, return 0. | |
214 | */ | |
215 | static int _omap3_noncore_dpll_stop(struct clk *clk) | |
216 | { | |
217 | u8 ai; | |
218 | ||
219 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | |
220 | return -EINVAL; | |
221 | ||
5dcc3b97 | 222 | pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); |
a1391d27 RN |
223 | |
224 | ai = omap3_dpll_autoidle_read(clk); | |
225 | ||
226 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | |
227 | ||
228 | if (ai) | |
229 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
230 | |
231 | return 0; | |
232 | } | |
233 | ||
358965d7 | 234 | /** |
a36795c1 | 235 | * _lookup_dco - Lookup DCO used by j-type DPLL |
358965d7 RW |
236 | * @clk: pointer to a DPLL struct clk |
237 | * @dco: digital control oscillator selector | |
358965d7 RW |
238 | * @m: DPLL multiplier to set |
239 | * @n: DPLL divider to set | |
240 | * | |
241 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
242 | * | |
243 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
244 | * out in non-multi-OMAP builds for those chips? | |
245 | */ | |
a36795c1 | 246 | static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) |
358965d7 | 247 | { |
a36795c1 | 248 | unsigned long fint, clkinp; /* watch out for overflow */ |
358965d7 | 249 | |
5dcc3b97 | 250 | clkinp = __clk_get_rate(__clk_get_parent(clk)); |
358965d7 RW |
251 | fint = (clkinp / n) * m; |
252 | ||
253 | if (fint < 1000000000) | |
254 | *dco = 2; | |
255 | else | |
256 | *dco = 4; | |
a36795c1 JH |
257 | } |
258 | ||
259 | /** | |
260 | * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL | |
261 | * @clk: pointer to a DPLL struct clk | |
262 | * @sd_div: target sigma-delta divider | |
263 | * @m: DPLL multiplier to set | |
264 | * @n: DPLL divider to set | |
265 | * | |
266 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
267 | * | |
268 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
269 | * out in non-multi-OMAP builds for those chips? | |
270 | */ | |
271 | static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) | |
272 | { | |
273 | unsigned long clkinp, sd; /* watch out for overflow */ | |
274 | int mod1, mod2; | |
275 | ||
5dcc3b97 | 276 | clkinp = __clk_get_rate(__clk_get_parent(clk)); |
a36795c1 | 277 | |
358965d7 RW |
278 | /* |
279 | * target sigma-delta to near 250MHz | |
280 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | |
281 | */ | |
282 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ | |
283 | mod1 = (clkinp * m) % (250 * n); | |
284 | sd = (clkinp * m) / (250 * n); | |
285 | mod2 = sd % 10; | |
286 | sd /= 10; | |
287 | ||
288 | if (mod1 || mod2) | |
289 | sd++; | |
290 | *sd_div = sd; | |
291 | } | |
292 | ||
60c3f651 PW |
293 | /* |
294 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | |
295 | * @clk: struct clk * of DPLL to set | |
296 | * @m: DPLL multiplier to set | |
297 | * @n: DPLL divider to set | |
298 | * @freqsel: FREQSEL value to set | |
299 | * | |
300 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | |
301 | * lock.. Returns -EINVAL upon error, or 0 upon success. | |
302 | */ | |
303 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |
304 | { | |
305 | struct dpll_data *dd = clk->dpll_data; | |
a36795c1 | 306 | u8 dco, sd_div; |
60c3f651 PW |
307 | u32 v; |
308 | ||
309 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | |
310 | _omap3_noncore_dpll_bypass(clk); | |
311 | ||
5eb75f55 VB |
312 | /* |
313 | * Set jitter correction. No jitter correction for OMAP4 and 3630 | |
314 | * since freqsel field is no longer present | |
315 | */ | |
78da2640 | 316 | if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { |
60c3f651 PW |
317 | v = __raw_readl(dd->control_reg); |
318 | v &= ~dd->freqsel_mask; | |
319 | v |= freqsel << __ffs(dd->freqsel_mask); | |
320 | __raw_writel(v, dd->control_reg); | |
321 | } | |
322 | ||
323 | /* Set DPLL multiplier, divider */ | |
324 | v = __raw_readl(dd->mult_div1_reg); | |
325 | v &= ~(dd->mult_mask | dd->div1_mask); | |
326 | v |= m << __ffs(dd->mult_mask); | |
327 | v |= (n - 1) << __ffs(dd->div1_mask); | |
358965d7 | 328 | |
a36795c1 JH |
329 | /* Configure dco and sd_div for dplls that have these fields */ |
330 | if (dd->dco_mask) { | |
331 | _lookup_dco(clk, &dco, m, n); | |
332 | v &= ~(dd->dco_mask); | |
333 | v |= dco << __ffs(dd->dco_mask); | |
334 | } | |
335 | if (dd->sddiv_mask) { | |
336 | _lookup_sddiv(clk, &sd_div, m, n); | |
337 | v &= ~(dd->sddiv_mask); | |
338 | v |= sd_div << __ffs(dd->sddiv_mask); | |
358965d7 RW |
339 | } |
340 | ||
60c3f651 PW |
341 | __raw_writel(v, dd->mult_div1_reg); |
342 | ||
343 | /* We let the clock framework set the other output dividers later */ | |
344 | ||
345 | /* REVISIT: Set ramp-up delay? */ | |
346 | ||
347 | _omap3_noncore_dpll_lock(clk); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | /* Public functions */ | |
353 | ||
354 | /** | |
355 | * omap3_dpll_recalc - recalculate DPLL rate | |
356 | * @clk: DPLL struct clk | |
357 | * | |
358 | * Recalculate and propagate the DPLL rate. | |
359 | */ | |
360 | unsigned long omap3_dpll_recalc(struct clk *clk) | |
361 | { | |
362 | return omap2_get_dpll_rate(clk); | |
363 | } | |
364 | ||
365 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | |
366 | ||
a1391d27 RN |
367 | /** |
368 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
369 | * @clk: pointer to a DPLL struct clk | |
370 | * | |
371 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
372 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
373 | * the same as the DPLL's parent clock, it will enter bypass; | |
374 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
375 | * indicate readiness before returning, unless the DPLL takes too long | |
376 | * to enter the target state. Intended to be used as the struct clk's | |
377 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
378 | * support low-power stop, or if the DPLL took too long to enter | |
379 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
380 | */ | |
381 | int omap3_noncore_dpll_enable(struct clk *clk) | |
382 | { | |
383 | int r; | |
384 | struct dpll_data *dd; | |
5dcc3b97 | 385 | struct clk *parent; |
a1391d27 RN |
386 | |
387 | dd = clk->dpll_data; | |
388 | if (!dd) | |
389 | return -EINVAL; | |
390 | ||
5dcc3b97 RN |
391 | parent = __clk_get_parent(clk); |
392 | ||
393 | if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { | |
394 | WARN_ON(parent != dd->clk_bypass); | |
a1391d27 RN |
395 | r = _omap3_noncore_dpll_bypass(clk); |
396 | } else { | |
5dcc3b97 | 397 | WARN_ON(parent != dd->clk_ref); |
a1391d27 RN |
398 | r = _omap3_noncore_dpll_lock(clk); |
399 | } | |
400 | /* | |
401 | *FIXME: this is dubious - if clk->rate has changed, what about | |
402 | * propagating? | |
403 | */ | |
404 | if (!r) | |
49642ac8 JH |
405 | clk->rate = (clk->recalc) ? clk->recalc(clk) : |
406 | omap2_get_dpll_rate(clk); | |
a1391d27 RN |
407 | |
408 | return r; | |
409 | } | |
410 | ||
411 | /** | |
412 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop | |
413 | * @clk: pointer to a DPLL struct clk | |
414 | * | |
415 | * Instructs a non-CORE DPLL to enter low-power stop. This function is | |
416 | * intended for use in struct clkops. No return value. | |
417 | */ | |
418 | void omap3_noncore_dpll_disable(struct clk *clk) | |
419 | { | |
420 | _omap3_noncore_dpll_stop(clk); | |
421 | } | |
422 | ||
423 | ||
424 | /* Non-CORE DPLL rate set code */ | |
425 | ||
a1391d27 RN |
426 | /** |
427 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | |
428 | * @clk: struct clk * of DPLL to set | |
429 | * @rate: rounded target rate | |
430 | * | |
431 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | |
432 | * low-power bypass, and the target rate is the bypass source clock | |
433 | * rate, then configure the DPLL for bypass. Otherwise, round the | |
434 | * target rate if it hasn't been done already, then program and lock | |
435 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | |
436 | */ | |
437 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |
438 | { | |
439 | struct clk *new_parent = NULL; | |
5dcc3b97 | 440 | unsigned long hw_rate, bypass_rate; |
16975a79 | 441 | u16 freqsel = 0; |
a1391d27 RN |
442 | struct dpll_data *dd; |
443 | int ret; | |
444 | ||
445 | if (!clk || !rate) | |
446 | return -EINVAL; | |
447 | ||
448 | dd = clk->dpll_data; | |
449 | if (!dd) | |
450 | return -EINVAL; | |
451 | ||
49642ac8 JH |
452 | hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); |
453 | if (rate == hw_rate) | |
a1391d27 RN |
454 | return 0; |
455 | ||
456 | /* | |
457 | * Ensure both the bypass and ref clocks are enabled prior to | |
458 | * doing anything; we need the bypass clock running to reprogram | |
459 | * the DPLL. | |
460 | */ | |
461 | omap2_clk_enable(dd->clk_bypass); | |
462 | omap2_clk_enable(dd->clk_ref); | |
463 | ||
5dcc3b97 RN |
464 | bypass_rate = __clk_get_rate(dd->clk_bypass); |
465 | if (bypass_rate == rate && | |
a1391d27 RN |
466 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { |
467 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | |
468 | ||
469 | ret = _omap3_noncore_dpll_bypass(clk); | |
470 | if (!ret) | |
471 | new_parent = dd->clk_bypass; | |
472 | } else { | |
473 | if (dd->last_rounded_rate != rate) | |
273a1ce9 | 474 | rate = clk->round_rate(clk, rate); |
a1391d27 RN |
475 | |
476 | if (dd->last_rounded_rate == 0) | |
477 | return -EINVAL; | |
478 | ||
5eb75f55 | 479 | /* No freqsel on OMAP4 and OMAP3630 */ |
78da2640 | 480 | if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { |
16975a79 RN |
481 | freqsel = _omap3_dpll_compute_freqsel(clk, |
482 | dd->last_rounded_n); | |
483 | if (!freqsel) | |
484 | WARN_ON(1); | |
485 | } | |
a1391d27 RN |
486 | |
487 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | |
5dcc3b97 | 488 | __clk_get_name(clk), rate); |
a1391d27 RN |
489 | |
490 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | |
491 | dd->last_rounded_n, freqsel); | |
492 | if (!ret) | |
493 | new_parent = dd->clk_ref; | |
494 | } | |
495 | if (!ret) { | |
496 | /* | |
732bee7a | 497 | * Switch the parent clock in the hierarchy, and make sure |
a1391d27 RN |
498 | * that the new parent's usecount is correct. Note: we |
499 | * enable the new parent before disabling the old to avoid | |
500 | * any unnecessary hardware disable->enable transitions. | |
501 | */ | |
502 | if (clk->usecount) { | |
503 | omap2_clk_enable(new_parent); | |
504 | omap2_clk_disable(clk->parent); | |
505 | } | |
506 | clk_reparent(clk, new_parent); | |
507 | clk->rate = rate; | |
508 | } | |
509 | omap2_clk_disable(dd->clk_ref); | |
510 | omap2_clk_disable(dd->clk_bypass); | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
515 | /* DPLL autoidle read/set code */ | |
516 | ||
517 | /** | |
518 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | |
519 | * @clk: struct clk * of the DPLL to read | |
520 | * | |
521 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | |
522 | * -EINVAL if passed a null pointer or if the struct clk does not | |
523 | * appear to refer to a DPLL. | |
524 | */ | |
525 | u32 omap3_dpll_autoidle_read(struct clk *clk) | |
526 | { | |
527 | const struct dpll_data *dd; | |
528 | u32 v; | |
529 | ||
530 | if (!clk || !clk->dpll_data) | |
531 | return -EINVAL; | |
532 | ||
533 | dd = clk->dpll_data; | |
534 | ||
d76316fe VB |
535 | if (!dd->autoidle_reg) |
536 | return -EINVAL; | |
537 | ||
a1391d27 RN |
538 | v = __raw_readl(dd->autoidle_reg); |
539 | v &= dd->autoidle_mask; | |
540 | v >>= __ffs(dd->autoidle_mask); | |
541 | ||
542 | return v; | |
543 | } | |
544 | ||
545 | /** | |
546 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | |
547 | * @clk: struct clk * of the DPLL to operate on | |
548 | * | |
549 | * Enable DPLL automatic idle control. This automatic idle mode | |
550 | * switching takes effect only when the DPLL is locked, at least on | |
551 | * OMAP3430. The DPLL will enter low-power stop when its downstream | |
552 | * clocks are gated. No return value. | |
553 | */ | |
554 | void omap3_dpll_allow_idle(struct clk *clk) | |
555 | { | |
556 | const struct dpll_data *dd; | |
557 | u32 v; | |
558 | ||
559 | if (!clk || !clk->dpll_data) | |
560 | return; | |
561 | ||
562 | dd = clk->dpll_data; | |
563 | ||
d76316fe VB |
564 | if (!dd->autoidle_reg) { |
565 | pr_debug("clock: DPLL %s: autoidle not supported\n", | |
5dcc3b97 | 566 | __clk_get_name(clk)); |
d76316fe VB |
567 | return; |
568 | } | |
569 | ||
a1391d27 RN |
570 | /* |
571 | * REVISIT: CORE DPLL can optionally enter low-power bypass | |
572 | * by writing 0x5 instead of 0x1. Add some mechanism to | |
573 | * optionally enter this mode. | |
574 | */ | |
575 | v = __raw_readl(dd->autoidle_reg); | |
576 | v &= ~dd->autoidle_mask; | |
577 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | |
578 | __raw_writel(v, dd->autoidle_reg); | |
d76316fe | 579 | |
a1391d27 RN |
580 | } |
581 | ||
582 | /** | |
583 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | |
584 | * @clk: struct clk * of the DPLL to operate on | |
585 | * | |
586 | * Disable DPLL automatic idle control. No return value. | |
587 | */ | |
588 | void omap3_dpll_deny_idle(struct clk *clk) | |
589 | { | |
590 | const struct dpll_data *dd; | |
591 | u32 v; | |
592 | ||
593 | if (!clk || !clk->dpll_data) | |
594 | return; | |
595 | ||
596 | dd = clk->dpll_data; | |
597 | ||
d76316fe VB |
598 | if (!dd->autoidle_reg) { |
599 | pr_debug("clock: DPLL %s: autoidle not supported\n", | |
5dcc3b97 | 600 | __clk_get_name(clk)); |
d76316fe VB |
601 | return; |
602 | } | |
603 | ||
a1391d27 RN |
604 | v = __raw_readl(dd->autoidle_reg); |
605 | v &= ~dd->autoidle_mask; | |
606 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | |
607 | __raw_writel(v, dd->autoidle_reg); | |
608 | ||
609 | } | |
610 | ||
611 | /* Clock control for DPLL outputs */ | |
612 | ||
613 | /** | |
614 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | |
615 | * @clk: DPLL output struct clk | |
616 | * | |
617 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | |
618 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | |
619 | */ | |
620 | unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |
621 | { | |
622 | const struct dpll_data *dd; | |
623 | unsigned long rate; | |
624 | u32 v; | |
625 | struct clk *pclk; | |
5dcc3b97 | 626 | unsigned long parent_rate; |
a1391d27 RN |
627 | |
628 | /* Walk up the parents of clk, looking for a DPLL */ | |
5dcc3b97 | 629 | pclk = __clk_get_parent(clk); |
a1391d27 | 630 | while (pclk && !pclk->dpll_data) |
5dcc3b97 | 631 | pclk = __clk_get_parent(pclk); |
a1391d27 | 632 | |
a032d33b PW |
633 | /* clk does not have a DPLL as a parent? error in the clock data */ |
634 | if (!pclk) { | |
635 | WARN_ON(1); | |
636 | return 0; | |
637 | } | |
a1391d27 RN |
638 | |
639 | dd = pclk->dpll_data; | |
640 | ||
641 | WARN_ON(!dd->enable_mask); | |
642 | ||
5dcc3b97 | 643 | parent_rate = __clk_get_rate(__clk_get_parent(clk)); |
a1391d27 RN |
644 | v = __raw_readl(dd->control_reg) & dd->enable_mask; |
645 | v >>= __ffs(dd->enable_mask); | |
358965d7 | 646 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
5dcc3b97 | 647 | rate = parent_rate; |
a1391d27 | 648 | else |
5dcc3b97 | 649 | rate = parent_rate * 2; |
a1391d27 RN |
650 | return rate; |
651 | } | |
353cec46 VH |
652 | |
653 | /* OMAP3/4 non-CORE DPLL clkops */ | |
654 | ||
655 | const struct clkops clkops_omap3_noncore_dpll_ops = { | |
656 | .enable = omap3_noncore_dpll_enable, | |
657 | .disable = omap3_noncore_dpll_disable, | |
658 | .allow_idle = omap3_dpll_allow_idle, | |
659 | .deny_idle = omap3_dpll_deny_idle, | |
660 | }; | |
661 | ||
662 | const struct clkops clkops_omap3_core_dpll_ops = { | |
663 | .allow_idle = omap3_dpll_allow_idle, | |
664 | .deny_idle = omap3_dpll_deny_idle, | |
665 | }; |