Commit | Line | Data |
---|---|---|
a1391d27 RN |
1 | /* |
2 | * OMAP3/4 - specific DPLL control functions | |
3 | * | |
358965d7 RW |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
a1391d27 RN |
6 | * |
7 | * Written by Paul Walmsley | |
358965d7 RW |
8 | * Testing and integration fixes by Jouni Högander |
9 | * | |
10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth | |
11 | * Menon | |
a1391d27 RN |
12 | * |
13 | * Parts of this code are based on code written by | |
14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
a1391d27 RN |
21 | #include <linux/kernel.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/io.h> | |
a1391d27 | 28 | #include <linux/bitops.h> |
6d803ba7 | 29 | #include <linux/clkdev.h> |
a1391d27 | 30 | |
32cc0021 | 31 | #include "clockdomain.h" |
a1391d27 | 32 | #include "clock.h" |
a1391d27 RN |
33 | |
34 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | |
35 | #define DPLL_AUTOIDLE_DISABLE 0x0 | |
36 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | |
37 | ||
38 | #define MAX_DPLL_WAIT_TRIES 1000000 | |
39 | ||
60c3f651 | 40 | /* Private functions */ |
a1391d27 RN |
41 | |
42 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | |
32cc0021 | 43 | static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) |
a1391d27 RN |
44 | { |
45 | const struct dpll_data *dd; | |
46 | u32 v; | |
47 | ||
48 | dd = clk->dpll_data; | |
49 | ||
519ab8b2 | 50 | v = omap2_clk_readl(clk, dd->control_reg); |
a1391d27 RN |
51 | v &= ~dd->enable_mask; |
52 | v |= clken_bits << __ffs(dd->enable_mask); | |
519ab8b2 | 53 | omap2_clk_writel(v, clk, dd->control_reg); |
a1391d27 RN |
54 | } |
55 | ||
56 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | |
32cc0021 | 57 | static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) |
a1391d27 RN |
58 | { |
59 | const struct dpll_data *dd; | |
60 | int i = 0; | |
61 | int ret = -EINVAL; | |
5dcc3b97 | 62 | const char *clk_name; |
a1391d27 RN |
63 | |
64 | dd = clk->dpll_data; | |
32cc0021 | 65 | clk_name = __clk_get_name(clk->hw.clk); |
a1391d27 RN |
66 | |
67 | state <<= __ffs(dd->idlest_mask); | |
68 | ||
519ab8b2 TK |
69 | while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) |
70 | != state) && i < MAX_DPLL_WAIT_TRIES) { | |
a1391d27 RN |
71 | i++; |
72 | udelay(1); | |
73 | } | |
74 | ||
75 | if (i == MAX_DPLL_WAIT_TRIES) { | |
76 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | |
5dcc3b97 | 77 | clk_name, (state) ? "locked" : "bypassed"); |
a1391d27 RN |
78 | } else { |
79 | pr_debug("clock: %s transition to '%s' in %d loops\n", | |
5dcc3b97 | 80 | clk_name, (state) ? "locked" : "bypassed", i); |
a1391d27 RN |
81 | |
82 | ret = 0; | |
83 | } | |
84 | ||
85 | return ret; | |
86 | } | |
87 | ||
88 | /* From 3430 TRM ES2 4.7.6.2 */ | |
32cc0021 | 89 | static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) |
a1391d27 RN |
90 | { |
91 | unsigned long fint; | |
92 | u16 f = 0; | |
93 | ||
5dcc3b97 | 94 | fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; |
a1391d27 RN |
95 | |
96 | pr_debug("clock: fint is %lu\n", fint); | |
97 | ||
98 | if (fint >= 750000 && fint <= 1000000) | |
99 | f = 0x3; | |
100 | else if (fint > 1000000 && fint <= 1250000) | |
101 | f = 0x4; | |
102 | else if (fint > 1250000 && fint <= 1500000) | |
103 | f = 0x5; | |
104 | else if (fint > 1500000 && fint <= 1750000) | |
105 | f = 0x6; | |
106 | else if (fint > 1750000 && fint <= 2100000) | |
107 | f = 0x7; | |
108 | else if (fint > 7500000 && fint <= 10000000) | |
109 | f = 0xB; | |
110 | else if (fint > 10000000 && fint <= 12500000) | |
111 | f = 0xC; | |
112 | else if (fint > 12500000 && fint <= 15000000) | |
113 | f = 0xD; | |
114 | else if (fint > 15000000 && fint <= 17500000) | |
115 | f = 0xE; | |
116 | else if (fint > 17500000 && fint <= 21000000) | |
117 | f = 0xF; | |
118 | else | |
119 | pr_debug("clock: unknown freqsel setting for %d\n", n); | |
120 | ||
121 | return f; | |
122 | } | |
123 | ||
a1391d27 RN |
124 | /* |
125 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | |
126 | * @clk: pointer to a DPLL struct clk | |
127 | * | |
128 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | |
129 | * readiness before returning. Will save and restore the DPLL's | |
130 | * autoidle state across the enable, per the CDP code. If the DPLL | |
131 | * locked successfully, return 0; if the DPLL did not lock in the time | |
132 | * allotted, or DPLL3 was passed in, return -EINVAL. | |
133 | */ | |
32cc0021 | 134 | static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) |
a1391d27 | 135 | { |
55ffe163 | 136 | const struct dpll_data *dd; |
a1391d27 | 137 | u8 ai; |
55ffe163 VP |
138 | u8 state = 1; |
139 | int r = 0; | |
a1391d27 | 140 | |
32cc0021 | 141 | pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); |
a1391d27 | 142 | |
55ffe163 VP |
143 | dd = clk->dpll_data; |
144 | state <<= __ffs(dd->idlest_mask); | |
145 | ||
146 | /* Check if already locked */ | |
519ab8b2 | 147 | if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state) |
55ffe163 VP |
148 | goto done; |
149 | ||
a1391d27 RN |
150 | ai = omap3_dpll_autoidle_read(clk); |
151 | ||
d76316fe VB |
152 | if (ai) |
153 | omap3_dpll_deny_idle(clk); | |
a1391d27 RN |
154 | |
155 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | |
156 | ||
157 | r = _omap3_wait_dpll_status(clk, 1); | |
158 | ||
159 | if (ai) | |
160 | omap3_dpll_allow_idle(clk); | |
161 | ||
55ffe163 | 162 | done: |
a1391d27 RN |
163 | return r; |
164 | } | |
165 | ||
166 | /* | |
167 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | |
168 | * @clk: pointer to a DPLL struct clk | |
169 | * | |
170 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | |
171 | * bypass mode, the DPLL's rate is set equal to its parent clock's | |
172 | * rate. Waits for the DPLL to report readiness before returning. | |
173 | * Will save and restore the DPLL's autoidle state across the enable, | |
174 | * per the CDP code. If the DPLL entered bypass mode successfully, | |
175 | * return 0; if the DPLL did not enter bypass in the time allotted, or | |
176 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | |
177 | * return -EINVAL. | |
178 | */ | |
32cc0021 | 179 | static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) |
a1391d27 RN |
180 | { |
181 | int r; | |
182 | u8 ai; | |
183 | ||
184 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | |
185 | return -EINVAL; | |
186 | ||
187 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | |
32cc0021 | 188 | __clk_get_name(clk->hw.clk)); |
a1391d27 RN |
189 | |
190 | ai = omap3_dpll_autoidle_read(clk); | |
191 | ||
192 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | |
193 | ||
194 | r = _omap3_wait_dpll_status(clk, 0); | |
195 | ||
196 | if (ai) | |
197 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
198 | |
199 | return r; | |
200 | } | |
201 | ||
202 | /* | |
203 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | |
204 | * @clk: pointer to a DPLL struct clk | |
205 | * | |
206 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | |
207 | * restore the DPLL's autoidle state across the stop, per the CDP | |
208 | * code. If DPLL3 was passed in, or the DPLL does not support | |
209 | * low-power stop, return -EINVAL; otherwise, return 0. | |
210 | */ | |
32cc0021 | 211 | static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) |
a1391d27 RN |
212 | { |
213 | u8 ai; | |
214 | ||
215 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | |
216 | return -EINVAL; | |
217 | ||
32cc0021 | 218 | pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); |
a1391d27 RN |
219 | |
220 | ai = omap3_dpll_autoidle_read(clk); | |
221 | ||
222 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | |
223 | ||
224 | if (ai) | |
225 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
226 | |
227 | return 0; | |
228 | } | |
229 | ||
358965d7 | 230 | /** |
a36795c1 | 231 | * _lookup_dco - Lookup DCO used by j-type DPLL |
358965d7 RW |
232 | * @clk: pointer to a DPLL struct clk |
233 | * @dco: digital control oscillator selector | |
358965d7 RW |
234 | * @m: DPLL multiplier to set |
235 | * @n: DPLL divider to set | |
236 | * | |
237 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
238 | * | |
239 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
240 | * out in non-multi-OMAP builds for those chips? | |
241 | */ | |
32cc0021 | 242 | static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) |
358965d7 | 243 | { |
a36795c1 | 244 | unsigned long fint, clkinp; /* watch out for overflow */ |
358965d7 | 245 | |
32cc0021 | 246 | clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); |
358965d7 RW |
247 | fint = (clkinp / n) * m; |
248 | ||
249 | if (fint < 1000000000) | |
250 | *dco = 2; | |
251 | else | |
252 | *dco = 4; | |
a36795c1 JH |
253 | } |
254 | ||
255 | /** | |
256 | * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL | |
257 | * @clk: pointer to a DPLL struct clk | |
258 | * @sd_div: target sigma-delta divider | |
259 | * @m: DPLL multiplier to set | |
260 | * @n: DPLL divider to set | |
261 | * | |
262 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
263 | * | |
264 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
265 | * out in non-multi-OMAP builds for those chips? | |
266 | */ | |
32cc0021 | 267 | static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) |
a36795c1 JH |
268 | { |
269 | unsigned long clkinp, sd; /* watch out for overflow */ | |
270 | int mod1, mod2; | |
271 | ||
32cc0021 | 272 | clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); |
a36795c1 | 273 | |
358965d7 RW |
274 | /* |
275 | * target sigma-delta to near 250MHz | |
276 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | |
277 | */ | |
278 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ | |
279 | mod1 = (clkinp * m) % (250 * n); | |
280 | sd = (clkinp * m) / (250 * n); | |
281 | mod2 = sd % 10; | |
282 | sd /= 10; | |
283 | ||
284 | if (mod1 || mod2) | |
285 | sd++; | |
286 | *sd_div = sd; | |
287 | } | |
288 | ||
60c3f651 PW |
289 | /* |
290 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | |
3ff51ed8 JH |
291 | * @clk: struct clk * of DPLL to set |
292 | * @freqsel: FREQSEL value to set | |
60c3f651 | 293 | * |
3ff51ed8 JH |
294 | * Program the DPLL with the last M, N values calculated, and wait for |
295 | * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success. | |
60c3f651 | 296 | */ |
3ff51ed8 | 297 | static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) |
60c3f651 PW |
298 | { |
299 | struct dpll_data *dd = clk->dpll_data; | |
a36795c1 | 300 | u8 dco, sd_div; |
60c3f651 PW |
301 | u32 v; |
302 | ||
303 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | |
304 | _omap3_noncore_dpll_bypass(clk); | |
305 | ||
5eb75f55 | 306 | /* |
ecf51648 RN |
307 | * Set jitter correction. Jitter correction applicable for OMAP343X |
308 | * only since freqsel field is no longer present on other devices. | |
5eb75f55 | 309 | */ |
2337c5b5 | 310 | if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { |
519ab8b2 | 311 | v = omap2_clk_readl(clk, dd->control_reg); |
60c3f651 PW |
312 | v &= ~dd->freqsel_mask; |
313 | v |= freqsel << __ffs(dd->freqsel_mask); | |
519ab8b2 | 314 | omap2_clk_writel(v, clk, dd->control_reg); |
60c3f651 PW |
315 | } |
316 | ||
317 | /* Set DPLL multiplier, divider */ | |
519ab8b2 | 318 | v = omap2_clk_readl(clk, dd->mult_div1_reg); |
ce369a54 AT |
319 | |
320 | /* Handle Duty Cycle Correction */ | |
321 | if (dd->dcc_mask) { | |
322 | if (dd->last_rounded_rate >= dd->dcc_rate) | |
323 | v |= dd->dcc_mask; /* Enable DCC */ | |
324 | else | |
325 | v &= ~dd->dcc_mask; /* Disable DCC */ | |
326 | } | |
327 | ||
60c3f651 | 328 | v &= ~(dd->mult_mask | dd->div1_mask); |
3ff51ed8 JH |
329 | v |= dd->last_rounded_m << __ffs(dd->mult_mask); |
330 | v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); | |
358965d7 | 331 | |
a36795c1 JH |
332 | /* Configure dco and sd_div for dplls that have these fields */ |
333 | if (dd->dco_mask) { | |
3ff51ed8 | 334 | _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); |
a36795c1 JH |
335 | v &= ~(dd->dco_mask); |
336 | v |= dco << __ffs(dd->dco_mask); | |
337 | } | |
338 | if (dd->sddiv_mask) { | |
3ff51ed8 JH |
339 | _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, |
340 | dd->last_rounded_n); | |
a36795c1 JH |
341 | v &= ~(dd->sddiv_mask); |
342 | v |= sd_div << __ffs(dd->sddiv_mask); | |
358965d7 RW |
343 | } |
344 | ||
519ab8b2 | 345 | omap2_clk_writel(v, clk, dd->mult_div1_reg); |
60c3f651 | 346 | |
3ff51ed8 JH |
347 | /* Set 4X multiplier and low-power mode */ |
348 | if (dd->m4xen_mask || dd->lpmode_mask) { | |
519ab8b2 | 349 | v = omap2_clk_readl(clk, dd->control_reg); |
3ff51ed8 JH |
350 | |
351 | if (dd->m4xen_mask) { | |
352 | if (dd->last_rounded_m4xen) | |
353 | v |= dd->m4xen_mask; | |
354 | else | |
355 | v &= ~dd->m4xen_mask; | |
356 | } | |
357 | ||
358 | if (dd->lpmode_mask) { | |
359 | if (dd->last_rounded_lpmode) | |
360 | v |= dd->lpmode_mask; | |
361 | else | |
362 | v &= ~dd->lpmode_mask; | |
363 | } | |
364 | ||
519ab8b2 | 365 | omap2_clk_writel(v, clk, dd->control_reg); |
3ff51ed8 JH |
366 | } |
367 | ||
60c3f651 PW |
368 | /* We let the clock framework set the other output dividers later */ |
369 | ||
370 | /* REVISIT: Set ramp-up delay? */ | |
371 | ||
372 | _omap3_noncore_dpll_lock(clk); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | /* Public functions */ | |
378 | ||
379 | /** | |
380 | * omap3_dpll_recalc - recalculate DPLL rate | |
381 | * @clk: DPLL struct clk | |
382 | * | |
383 | * Recalculate and propagate the DPLL rate. | |
384 | */ | |
32cc0021 MT |
385 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) |
386 | { | |
387 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
455db9c9 | 388 | |
60c3f651 PW |
389 | return omap2_get_dpll_rate(clk); |
390 | } | |
391 | ||
392 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | |
393 | ||
a1391d27 RN |
394 | /** |
395 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
396 | * @clk: pointer to a DPLL struct clk | |
397 | * | |
398 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
399 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
400 | * the same as the DPLL's parent clock, it will enter bypass; | |
401 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
402 | * indicate readiness before returning, unless the DPLL takes too long | |
403 | * to enter the target state. Intended to be used as the struct clk's | |
404 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
405 | * support low-power stop, or if the DPLL took too long to enter | |
406 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
407 | */ | |
32cc0021 MT |
408 | int omap3_noncore_dpll_enable(struct clk_hw *hw) |
409 | { | |
410 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1391d27 RN |
411 | int r; |
412 | struct dpll_data *dd; | |
5dcc3b97 | 413 | struct clk *parent; |
a1391d27 RN |
414 | |
415 | dd = clk->dpll_data; | |
416 | if (!dd) | |
417 | return -EINVAL; | |
418 | ||
32cc0021 MT |
419 | if (clk->clkdm) { |
420 | r = clkdm_clk_enable(clk->clkdm, hw->clk); | |
421 | if (r) { | |
422 | WARN(1, | |
423 | "%s: could not enable %s's clockdomain %s: %d\n", | |
424 | __func__, __clk_get_name(hw->clk), | |
425 | clk->clkdm->name, r); | |
426 | return r; | |
427 | } | |
428 | } | |
429 | ||
430 | parent = __clk_get_parent(hw->clk); | |
431 | ||
432 | if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { | |
5dcc3b97 | 433 | WARN_ON(parent != dd->clk_bypass); |
a1391d27 RN |
434 | r = _omap3_noncore_dpll_bypass(clk); |
435 | } else { | |
5dcc3b97 | 436 | WARN_ON(parent != dd->clk_ref); |
a1391d27 RN |
437 | r = _omap3_noncore_dpll_lock(clk); |
438 | } | |
32cc0021 | 439 | |
a1391d27 RN |
440 | return r; |
441 | } | |
442 | ||
443 | /** | |
444 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop | |
445 | * @clk: pointer to a DPLL struct clk | |
446 | * | |
447 | * Instructs a non-CORE DPLL to enter low-power stop. This function is | |
448 | * intended for use in struct clkops. No return value. | |
449 | */ | |
32cc0021 MT |
450 | void omap3_noncore_dpll_disable(struct clk_hw *hw) |
451 | { | |
452 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
453 | ||
454 | _omap3_noncore_dpll_stop(clk); | |
455 | if (clk->clkdm) | |
456 | clkdm_clk_disable(clk->clkdm, hw->clk); | |
a1391d27 RN |
457 | } |
458 | ||
459 | ||
460 | /* Non-CORE DPLL rate set code */ | |
461 | ||
a1391d27 RN |
462 | /** |
463 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | |
464 | * @clk: struct clk * of DPLL to set | |
465 | * @rate: rounded target rate | |
466 | * | |
467 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | |
468 | * low-power bypass, and the target rate is the bypass source clock | |
469 | * rate, then configure the DPLL for bypass. Otherwise, round the | |
470 | * target rate if it hasn't been done already, then program and lock | |
471 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | |
472 | */ | |
32cc0021 MT |
473 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, |
474 | unsigned long parent_rate) | |
475 | { | |
476 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
477 | struct clk *new_parent = NULL; | |
0a263444 | 478 | unsigned long rrate; |
32cc0021 MT |
479 | u16 freqsel = 0; |
480 | struct dpll_data *dd; | |
481 | int ret; | |
482 | ||
483 | if (!hw || !rate) | |
484 | return -EINVAL; | |
485 | ||
486 | dd = clk->dpll_data; | |
487 | if (!dd) | |
488 | return -EINVAL; | |
489 | ||
32cc0021 MT |
490 | if (__clk_get_rate(dd->clk_bypass) == rate && |
491 | (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | |
492 | pr_debug("%s: %s: set rate: entering bypass.\n", | |
493 | __func__, __clk_get_name(hw->clk)); | |
494 | ||
469d633d RN |
495 | __clk_prepare(dd->clk_bypass); |
496 | clk_enable(dd->clk_bypass); | |
32cc0021 MT |
497 | ret = _omap3_noncore_dpll_bypass(clk); |
498 | if (!ret) | |
499 | new_parent = dd->clk_bypass; | |
469d633d RN |
500 | clk_disable(dd->clk_bypass); |
501 | __clk_unprepare(dd->clk_bypass); | |
32cc0021 | 502 | } else { |
469d633d RN |
503 | __clk_prepare(dd->clk_ref); |
504 | clk_enable(dd->clk_ref); | |
505 | ||
0a263444 PW |
506 | /* XXX this check is probably pointless in the CCF context */ |
507 | if (dd->last_rounded_rate != rate) { | |
508 | rrate = __clk_round_rate(hw->clk, rate); | |
509 | if (rrate != rate) { | |
510 | pr_warn("%s: %s: final rate %lu does not match desired rate %lu\n", | |
511 | __func__, __clk_get_name(hw->clk), | |
512 | rrate, rate); | |
513 | rate = rrate; | |
514 | } | |
515 | } | |
32cc0021 MT |
516 | |
517 | if (dd->last_rounded_rate == 0) | |
518 | return -EINVAL; | |
519 | ||
ecf51648 | 520 | /* Freqsel is available only on OMAP343X devices */ |
2337c5b5 | 521 | if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { |
32cc0021 MT |
522 | freqsel = _omap3_dpll_compute_freqsel(clk, |
523 | dd->last_rounded_n); | |
f64d204b | 524 | WARN_ON(!freqsel); |
32cc0021 MT |
525 | } |
526 | ||
527 | pr_debug("%s: %s: set rate: locking rate to %lu.\n", | |
528 | __func__, __clk_get_name(hw->clk), rate); | |
529 | ||
3ff51ed8 | 530 | ret = omap3_noncore_dpll_program(clk, freqsel); |
32cc0021 MT |
531 | if (!ret) |
532 | new_parent = dd->clk_ref; | |
469d633d RN |
533 | clk_disable(dd->clk_ref); |
534 | __clk_unprepare(dd->clk_ref); | |
32cc0021 MT |
535 | } |
536 | /* | |
537 | * FIXME - this is all wrong. common code handles reparenting and | |
538 | * migrating prepare/enable counts. dplls should be a multiplexer | |
539 | * clock and this should be a set_parent operation so that all of that | |
540 | * stuff is inherited for free | |
541 | */ | |
542 | ||
110e884d | 543 | if (!ret && clk_get_parent(hw->clk) != new_parent) |
32cc0021 MT |
544 | __clk_reparent(hw->clk, new_parent); |
545 | ||
32cc0021 MT |
546 | return 0; |
547 | } | |
a1391d27 RN |
548 | |
549 | /* DPLL autoidle read/set code */ | |
550 | ||
551 | /** | |
552 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | |
553 | * @clk: struct clk * of the DPLL to read | |
554 | * | |
555 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | |
556 | * -EINVAL if passed a null pointer or if the struct clk does not | |
557 | * appear to refer to a DPLL. | |
558 | */ | |
32cc0021 | 559 | u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) |
a1391d27 RN |
560 | { |
561 | const struct dpll_data *dd; | |
562 | u32 v; | |
563 | ||
564 | if (!clk || !clk->dpll_data) | |
565 | return -EINVAL; | |
566 | ||
567 | dd = clk->dpll_data; | |
568 | ||
d76316fe VB |
569 | if (!dd->autoidle_reg) |
570 | return -EINVAL; | |
571 | ||
519ab8b2 | 572 | v = omap2_clk_readl(clk, dd->autoidle_reg); |
a1391d27 RN |
573 | v &= dd->autoidle_mask; |
574 | v >>= __ffs(dd->autoidle_mask); | |
575 | ||
576 | return v; | |
577 | } | |
578 | ||
579 | /** | |
580 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | |
581 | * @clk: struct clk * of the DPLL to operate on | |
582 | * | |
583 | * Enable DPLL automatic idle control. This automatic idle mode | |
584 | * switching takes effect only when the DPLL is locked, at least on | |
585 | * OMAP3430. The DPLL will enter low-power stop when its downstream | |
586 | * clocks are gated. No return value. | |
587 | */ | |
32cc0021 | 588 | void omap3_dpll_allow_idle(struct clk_hw_omap *clk) |
a1391d27 RN |
589 | { |
590 | const struct dpll_data *dd; | |
591 | u32 v; | |
592 | ||
593 | if (!clk || !clk->dpll_data) | |
594 | return; | |
595 | ||
596 | dd = clk->dpll_data; | |
597 | ||
455db9c9 | 598 | if (!dd->autoidle_reg) |
d76316fe | 599 | return; |
d76316fe | 600 | |
a1391d27 RN |
601 | /* |
602 | * REVISIT: CORE DPLL can optionally enter low-power bypass | |
603 | * by writing 0x5 instead of 0x1. Add some mechanism to | |
604 | * optionally enter this mode. | |
605 | */ | |
519ab8b2 | 606 | v = omap2_clk_readl(clk, dd->autoidle_reg); |
a1391d27 RN |
607 | v &= ~dd->autoidle_mask; |
608 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | |
519ab8b2 | 609 | omap2_clk_writel(v, clk, dd->autoidle_reg); |
d76316fe | 610 | |
a1391d27 RN |
611 | } |
612 | ||
613 | /** | |
614 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | |
615 | * @clk: struct clk * of the DPLL to operate on | |
616 | * | |
617 | * Disable DPLL automatic idle control. No return value. | |
618 | */ | |
32cc0021 | 619 | void omap3_dpll_deny_idle(struct clk_hw_omap *clk) |
a1391d27 RN |
620 | { |
621 | const struct dpll_data *dd; | |
622 | u32 v; | |
623 | ||
624 | if (!clk || !clk->dpll_data) | |
625 | return; | |
626 | ||
627 | dd = clk->dpll_data; | |
628 | ||
455db9c9 | 629 | if (!dd->autoidle_reg) |
d76316fe | 630 | return; |
d76316fe | 631 | |
519ab8b2 | 632 | v = omap2_clk_readl(clk, dd->autoidle_reg); |
a1391d27 RN |
633 | v &= ~dd->autoidle_mask; |
634 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | |
519ab8b2 | 635 | omap2_clk_writel(v, clk, dd->autoidle_reg); |
a1391d27 RN |
636 | |
637 | } | |
638 | ||
639 | /* Clock control for DPLL outputs */ | |
640 | ||
994c41ee TV |
641 | /* Find the parent DPLL for the given clkoutx2 clock */ |
642 | static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) | |
643 | { | |
644 | struct clk_hw_omap *pclk = NULL; | |
645 | struct clk *parent; | |
646 | ||
647 | /* Walk up the parents of clk, looking for a DPLL */ | |
648 | do { | |
649 | do { | |
650 | parent = __clk_get_parent(hw->clk); | |
651 | hw = __clk_get_hw(parent); | |
652 | } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); | |
653 | if (!hw) | |
654 | break; | |
655 | pclk = to_clk_hw_omap(hw); | |
656 | } while (pclk && !pclk->dpll_data); | |
657 | ||
658 | /* clk does not have a DPLL as a parent? error in the clock data */ | |
659 | if (!pclk) { | |
660 | WARN_ON(1); | |
661 | return NULL; | |
662 | } | |
663 | ||
664 | return pclk; | |
665 | } | |
666 | ||
a1391d27 RN |
667 | /** |
668 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | |
669 | * @clk: DPLL output struct clk | |
670 | * | |
671 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | |
672 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | |
673 | */ | |
32cc0021 MT |
674 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, |
675 | unsigned long parent_rate) | |
676 | { | |
677 | const struct dpll_data *dd; | |
678 | unsigned long rate; | |
679 | u32 v; | |
680 | struct clk_hw_omap *pclk = NULL; | |
32cc0021 | 681 | |
519ab8b2 TK |
682 | if (!parent_rate) |
683 | return 0; | |
684 | ||
994c41ee | 685 | pclk = omap3_find_clkoutx2_dpll(hw); |
a1391d27 | 686 | |
994c41ee | 687 | if (!pclk) |
a032d33b | 688 | return 0; |
a1391d27 RN |
689 | |
690 | dd = pclk->dpll_data; | |
691 | ||
692 | WARN_ON(!dd->enable_mask); | |
693 | ||
519ab8b2 | 694 | v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; |
a1391d27 | 695 | v >>= __ffs(dd->enable_mask); |
358965d7 | 696 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
5dcc3b97 | 697 | rate = parent_rate; |
a1391d27 | 698 | else |
5dcc3b97 | 699 | rate = parent_rate * 2; |
a1391d27 RN |
700 | return rate; |
701 | } | |
353cec46 | 702 | |
994c41ee TV |
703 | int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate, |
704 | unsigned long parent_rate) | |
705 | { | |
706 | return 0; | |
707 | } | |
708 | ||
709 | long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate, | |
710 | unsigned long *prate) | |
711 | { | |
712 | const struct dpll_data *dd; | |
713 | u32 v; | |
714 | struct clk_hw_omap *pclk = NULL; | |
715 | ||
716 | if (!*prate) | |
717 | return 0; | |
718 | ||
719 | pclk = omap3_find_clkoutx2_dpll(hw); | |
720 | ||
721 | if (!pclk) | |
722 | return 0; | |
723 | ||
724 | dd = pclk->dpll_data; | |
725 | ||
726 | /* TYPE J does not have a clkoutx2 */ | |
727 | if (dd->flags & DPLL_J_TYPE) { | |
728 | *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate); | |
729 | return *prate; | |
730 | } | |
731 | ||
732 | WARN_ON(!dd->enable_mask); | |
733 | ||
734 | v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; | |
735 | v >>= __ffs(dd->enable_mask); | |
736 | ||
737 | /* If in bypass, the rate is fixed to the bypass rate*/ | |
738 | if (v != OMAP3XXX_EN_DPLL_LOCKED) | |
739 | return *prate; | |
740 | ||
741 | if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { | |
742 | unsigned long best_parent; | |
743 | ||
744 | best_parent = (rate / 2); | |
745 | *prate = __clk_round_rate(__clk_get_parent(hw->clk), | |
746 | best_parent); | |
747 | } | |
748 | ||
749 | return *prate * 2; | |
750 | } | |
751 | ||
353cec46 | 752 | /* OMAP3/4 non-CORE DPLL clkops */ |
32cc0021 MT |
753 | const struct clk_hw_omap_ops clkhwops_omap3_dpll = { |
754 | .allow_idle = omap3_dpll_allow_idle, | |
755 | .deny_idle = omap3_dpll_deny_idle, | |
756 | }; |