[deliverable/linux.git] / arch / arm / mach-omap2 / dpll3xxx.c

/*
 * OMAP3/4 - specific DPLL control functions
 *
 * Copyright (C) 2009-2010 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Written by Paul Walmsley
 * Testing and integration fixes by Jouni Högander
 *
 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
 * Menon
 *
 * Parts of this code are based on code written by
 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clkdev.h>

#include "soc.h"
#include "clockdomain.h"
#include "clock.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
#define DPLL_AUTOIDLE_DISABLE			0x0
#define DPLL_AUTOIDLE_LOW_POWER_STOP		0x1

#define MAX_DPLL_WAIT_TRIES		1000000

/* Private functions */

/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
{
	const struct dpll_data *dd;
	u32 v;

	dd = clk->dpll_data;

	v = __raw_readl(dd->control_reg);
	v &= ~dd->enable_mask;
	v |= clken_bits << __ffs(dd->enable_mask);
	__raw_writel(v, dd->control_reg);
}

/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
{
	const struct dpll_data *dd;
	int i = 0;
	int ret = -EINVAL;
	const char *clk_name;

	dd = clk->dpll_data;
	clk_name = __clk_get_name(clk->hw.clk);

	state <<= __ffs(dd->idlest_mask);

	while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
	       i < MAX_DPLL_WAIT_TRIES) {
		i++;
		udelay(1);
	}

	if (i == MAX_DPLL_WAIT_TRIES) {
		printk(KERN_ERR "clock: %s failed transition to '%s'\n",
		       clk_name, (state) ? "locked" : "bypassed");
	} else {
		pr_debug("clock: %s transition to '%s' in %d loops\n",
			 clk_name, (state) ? "locked" : "bypassed", i);

		ret = 0;
	}

	return ret;
}

/* From 3430 TRM ES2 4.7.6.2 */
static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
{
	unsigned long fint;
	u16 f = 0;

	fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;

	pr_debug("clock: fint is %lu\n", fint);

	if (fint >= 750000 && fint <= 1000000)
		f = 0x3;
	else if (fint > 1000000 && fint <= 1250000)
		f = 0x4;
	else if (fint > 1250000 && fint <= 1500000)
		f = 0x5;
	else if (fint > 1500000 && fint <= 1750000)
		f = 0x6;
	else if (fint > 1750000 && fint <= 2100000)
		f = 0x7;
	else if (fint > 7500000 && fint <= 10000000)
		f = 0xB;
	else if (fint > 10000000 && fint <= 12500000)
		f = 0xC;
	else if (fint > 12500000 && fint <= 15000000)
		f = 0xD;
	else if (fint > 15000000 && fint <= 17500000)
		f = 0xE;
	else if (fint > 17500000 && fint <= 21000000)
		f = 0xF;
	else
		pr_debug("clock: unknown freqsel setting for %d\n", n);

	return f;
}

/*
 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
 * @clk: pointer to a DPLL struct clk
 *
 * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
 * readiness before returning.  Will save and restore the DPLL's
 * autoidle state across the enable, per the CDP code.  If the DPLL
 * locked successfully, return 0; if the DPLL did not lock in the time
 * allotted, or DPLL3 was passed in, return -EINVAL.
 */
static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
{
	const struct dpll_data *dd;
	u8 ai;
	u8 state = 1;
	int r = 0;

	pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));

	dd = clk->dpll_data;
	state <<= __ffs(dd->idlest_mask);

	/* Check if already locked */
	if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
		goto done;

	ai = omap3_dpll_autoidle_read(clk);

	if (ai)
		omap3_dpll_deny_idle(clk);

	_omap3_dpll_write_clken(clk, DPLL_LOCKED);

	r = _omap3_wait_dpll_status(clk, 1);

	if (ai)
		omap3_dpll_allow_idle(clk);

done:
	return r;
}

/*
 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
 * @clk: pointer to a DPLL struct clk
 *
 * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
 * bypass mode, the DPLL's rate is set equal to its parent clock's
 * rate.  Waits for the DPLL to report readiness before returning.
 * Will save and restore the DPLL's autoidle state across the enable,
 * per the CDP code.  If the DPLL entered bypass mode successfully,
 * return 0; if the DPLL did not enter bypass in the time allotted, or
 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
 * return -EINVAL.
 */
static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
{
	int r;
	u8 ai;

	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
		return -EINVAL;

	pr_debug("clock: configuring DPLL %s for low-power bypass\n",
		 __clk_get_name(clk->hw.clk));

	ai = omap3_dpll_autoidle_read(clk);

	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);

	r = _omap3_wait_dpll_status(clk, 0);

	if (ai)
		omap3_dpll_allow_idle(clk);

	return r;
}

/*
 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
 * @clk: pointer to a DPLL struct clk
 *
 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
 * restore the DPLL's autoidle state across the stop, per the CDP
 * code.  If DPLL3 was passed in, or the DPLL does not support
 * low-power stop, return -EINVAL; otherwise, return 0.
 */
static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
{
	u8 ai;

	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
		return -EINVAL;

	pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));

	ai = omap3_dpll_autoidle_read(clk);

	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);

	if (ai)
		omap3_dpll_allow_idle(clk);

	return 0;
}

/**
 * _lookup_dco - Lookup DCO used by j-type DPLL
 * @clk: pointer to a DPLL struct clk
 * @dco: digital control oscillator selector
 * @m: DPLL multiplier to set
 * @n: DPLL divider to set
 *
 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
 *
 * XXX This code is not needed for 3430/AM35xx; can it be optimized
 * out in non-multi-OMAP builds for those chips?
 */
static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
{
	unsigned long fint, clkinp; /* watch out for overflow */

	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
	fint = (clkinp / n) * m;

	if (fint < 1000000000)
		*dco = 2;
	else
		*dco = 4;
}

/**
 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
 * @clk: pointer to a DPLL struct clk
 * @sd_div: target sigma-delta divider
 * @m: DPLL multiplier to set
 * @n: DPLL divider to set
 *
 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
 *
 * XXX This code is not needed for 3430/AM35xx; can it be optimized
 * out in non-multi-OMAP builds for those chips?
 */
static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
{
	unsigned long clkinp, sd; /* watch out for overflow */
	int mod1, mod2;

	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));

	/*
	 * target sigma-delta to near 250MHz
	 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
	 */
	clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
	mod1 = (clkinp * m) % (250 * n);
	sd = (clkinp * m) / (250 * n);
	mod2 = sd % 10;
	sd /= 10;

	if (mod1 || mod2)
		sd++;
	*sd_div = sd;
}

/*
 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 * @clk: struct clk * of DPLL to set
 * @m: DPLL multiplier to set
 * @n: DPLL divider to set
 * @freqsel: FREQSEL value to set
 *
 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 * lock..  Returns -EINVAL upon error, or 0 upon success.
 */
static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
				      u16 freqsel)
{
	struct dpll_data *dd = clk->dpll_data;
	u8 dco, sd_div;
	u32 v;

	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
	_omap3_noncore_dpll_bypass(clk);

	/*
	 * Set jitter correction. No jitter correction for OMAP4 and 3630
	 * since freqsel field is no longer present
	 */
	if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
		v = __raw_readl(dd->control_reg);
		v &= ~dd->freqsel_mask;
		v |= freqsel << __ffs(dd->freqsel_mask);
		__raw_writel(v, dd->control_reg);
	}

	/* Set DPLL multiplier, divider */
	v = __raw_readl(dd->mult_div1_reg);
	v &= ~(dd->mult_mask | dd->div1_mask);
	v |= m << __ffs(dd->mult_mask);
	v |= (n - 1) << __ffs(dd->div1_mask);

	/* Configure dco and sd_div for dplls that have these fields */
	if (dd->dco_mask) {
		_lookup_dco(clk, &dco, m, n);
		v &= ~(dd->dco_mask);
		v |= dco << __ffs(dd->dco_mask);
	}
	if (dd->sddiv_mask) {
		_lookup_sddiv(clk, &sd_div, m, n);
		v &= ~(dd->sddiv_mask);
		v |= sd_div << __ffs(dd->sddiv_mask);
	}

	__raw_writel(v, dd->mult_div1_reg);

	/* We let the clock framework set the other output dividers later */

	/* REVISIT: Set ramp-up delay? */

	_omap3_noncore_dpll_lock(clk);

	return 0;
}

/* Public functions */

/**
 * omap3_dpll_recalc - recalculate DPLL rate
 * @clk: DPLL struct clk
 *
 * Recalculate and propagate the DPLL rate.
 */
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

	return omap2_get_dpll_rate(clk);
}

/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */

/**
 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 * @clk: pointer to a DPLL struct clk
 *
 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 * The choice of modes depends on the DPLL's programmed rate: if it is
 * the same as the DPLL's parent clock, it will enter bypass;
 * otherwise, it will enter lock.  This code will wait for the DPLL to
 * indicate readiness before returning, unless the DPLL takes too long
 * to enter the target state.  Intended to be used as the struct clk's
 * enable function.  If DPLL3 was passed in, or the DPLL does not
 * support low-power stop, or if the DPLL took too long to enter
 * bypass or lock, return -EINVAL; otherwise, return 0.
 */
int omap3_noncore_dpll_enable(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	int r;
	struct dpll_data *dd;
	struct clk *parent;

	dd = clk->dpll_data;
	if (!dd)
		return -EINVAL;

	if (clk->clkdm) {
		r = clkdm_clk_enable(clk->clkdm, hw->clk);
		if (r) {
			WARN(1,
			     "%s: could not enable %s's clockdomain %s: %d\n",
			     __func__, __clk_get_name(hw->clk),
			     clk->clkdm->name, r);
			return r;
		}
	}

	parent = __clk_get_parent(hw->clk);

	if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
		WARN_ON(parent != dd->clk_bypass);
		r = _omap3_noncore_dpll_bypass(clk);
	} else {
		WARN_ON(parent != dd->clk_ref);
		r = _omap3_noncore_dpll_lock(clk);
	}

	return r;
}

/**
 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
 * @clk: pointer to a DPLL struct clk
 *
 * Instructs a non-CORE DPLL to enter low-power stop.  This function is
 * intended for use in struct clkops.  No return value.
 */
void omap3_noncore_dpll_disable(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

	_omap3_noncore_dpll_stop(clk);
	if (clk->clkdm)
		clkdm_clk_disable(clk->clkdm, hw->clk);
}


/* Non-CORE DPLL rate set code */

/**
 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
 * @clk: struct clk * of DPLL to set
 * @rate: rounded target rate
 *
 * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
 * low-power bypass, and the target rate is the bypass source clock
 * rate, then configure the DPLL for bypass.  Otherwise, round the
 * target rate if it hasn't been done already, then program and lock
 * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
 */
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
					unsigned long parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct clk *new_parent = NULL;
	u16 freqsel = 0;
	struct dpll_data *dd;
	int ret;

	if (!hw || !rate)
		return -EINVAL;

	dd = clk->dpll_data;
	if (!dd)
		return -EINVAL;

	__clk_prepare(dd->clk_bypass);
	clk_enable(dd->clk_bypass);
	__clk_prepare(dd->clk_ref);
	clk_enable(dd->clk_ref);

	if (__clk_get_rate(dd->clk_bypass) == rate &&
	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
		pr_debug("%s: %s: set rate: entering bypass.\n",
			 __func__, __clk_get_name(hw->clk));

		ret = _omap3_noncore_dpll_bypass(clk);
		if (!ret)
			new_parent = dd->clk_bypass;
	} else {
		if (dd->last_rounded_rate != rate)
			rate = __clk_round_rate(hw->clk, rate);

		if (dd->last_rounded_rate == 0)
			return -EINVAL;

		/* No freqsel on OMAP4 and OMAP3630 */
		if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
			freqsel = _omap3_dpll_compute_freqsel(clk,
						dd->last_rounded_n);
			if (!freqsel)
				WARN_ON(1);
		}

		pr_debug("%s: %s: set rate: locking rate to %lu.\n",
			 __func__, __clk_get_name(hw->clk), rate);

		ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
						dd->last_rounded_n, freqsel);
		if (!ret)
			new_parent = dd->clk_ref;
	}
	/*
	* FIXME - this is all wrong.  common code handles reparenting and
	* migrating prepare/enable counts.  dplls should be a multiplexer
	* clock and this should be a set_parent operation so that all of that
	* stuff is inherited for free
	*/

	if (!ret)
		__clk_reparent(hw->clk, new_parent);

	clk_disable(dd->clk_ref);
	__clk_unprepare(dd->clk_ref);
	clk_disable(dd->clk_bypass);
	__clk_unprepare(dd->clk_bypass);

	return 0;
}

/* DPLL autoidle read/set code */

/**
 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
 * @clk: struct clk * of the DPLL to read
 *
 * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
 * -EINVAL if passed a null pointer or if the struct clk does not
 * appear to refer to a DPLL.
 */
u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
{
	const struct dpll_data *dd;
	u32 v;

	if (!clk || !clk->dpll_data)
		return -EINVAL;

	dd = clk->dpll_data;

	if (!dd->autoidle_reg)
		return -EINVAL;

	v = __raw_readl(dd->autoidle_reg);
	v &= dd->autoidle_mask;
	v >>= __ffs(dd->autoidle_mask);

	return v;
}

/**
 * omap3_dpll_allow_idle - enable DPLL autoidle bits
 * @clk: struct clk * of the DPLL to operate on
 *
 * Enable DPLL automatic idle control.  This automatic idle mode
 * switching takes effect only when the DPLL is locked, at least on
 * OMAP3430.  The DPLL will enter low-power stop when its downstream
 * clocks are gated.  No return value.
 */
void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
{
	const struct dpll_data *dd;
	u32 v;

	if (!clk || !clk->dpll_data)
		return;

	dd = clk->dpll_data;

	if (!dd->autoidle_reg)
		return;

	/*
	 * REVISIT: CORE DPLL can optionally enter low-power bypass
	 * by writing 0x5 instead of 0x1.  Add some mechanism to
	 * optionally enter this mode.
	 */
	v = __raw_readl(dd->autoidle_reg);
	v &= ~dd->autoidle_mask;
	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
	__raw_writel(v, dd->autoidle_reg);

}

/**
 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
 * @clk: struct clk * of the DPLL to operate on
 *
 * Disable DPLL automatic idle control.  No return value.
 */
void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
{
	const struct dpll_data *dd;
	u32 v;

	if (!clk || !clk->dpll_data)
		return;

	dd = clk->dpll_data;

	if (!dd->autoidle_reg)
		return;

	v = __raw_readl(dd->autoidle_reg);
	v &= ~dd->autoidle_mask;
	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
	__raw_writel(v, dd->autoidle_reg);

}

/* Clock control for DPLL outputs */

/**
 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
 * @clk: DPLL output struct clk
 *
 * Using parent clock DPLL data, look up DPLL state.  If locked, set our
 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
 */
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
				    unsigned long parent_rate)
{
	const struct dpll_data *dd;
	unsigned long rate;
	u32 v;
	struct clk_hw_omap *pclk = NULL;
	struct clk *parent;

	/* Walk up the parents of clk, looking for a DPLL */
	do {
		do {
			parent = __clk_get_parent(hw->clk);
			hw = __clk_get_hw(parent);
		} while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
		if (!hw)
			break;
		pclk = to_clk_hw_omap(hw);
	} while (pclk && !pclk->dpll_data);

	/* clk does not have a DPLL as a parent?  error in the clock data */
	if (!pclk) {
		WARN_ON(1);
		return 0;
	}

	dd = pclk->dpll_data;

	WARN_ON(!dd->enable_mask);

	v = __raw_readl(dd->control_reg) & dd->enable_mask;
	v >>= __ffs(dd->enable_mask);
	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
		rate = parent_rate;
	else
		rate = parent_rate * 2;
	return rate;
}

/* OMAP3/4 non-CORE DPLL clkops */
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
	.allow_idle	= omap3_dpll_allow_idle,
	.deny_idle	= omap3_dpll_deny_idle,
};
Commit	Line	Data
a1391d27 RN	1	/*
	2	* OMAP3/4 - specific DPLL control functions
	3	*
358965d7 RW	4	* Copyright (C) 2009-2010 Texas Instruments, Inc.
358965d7 RW	5	* Copyright (C) 2009-2010 Nokia Corporation
a1391d27 RN	6	*
a1391d27 RN	7	* Written by Paul Walmsley
358965d7 RW	8	* Testing and integration fixes by Jouni Högander
	9	*
	10	* 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
	11	* Menon
a1391d27 RN	12	*
	13	* Parts of this code are based on code written by
	14	* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
a1391d27 RN	21	#include <linux/kernel.h>
	22	#include <linux/device.h>
	23	#include <linux/list.h>
	24	#include <linux/errno.h>
	25	#include <linux/delay.h>
	26	#include <linux/clk.h>
	27	#include <linux/io.h>
a1391d27	28	#include <linux/bitops.h>
6d803ba7	29	#include <linux/clkdev.h>
a1391d27	30
dbc04161	31	#include "soc.h"
32cc0021	32	#include "clockdomain.h"
a1391d27	33	#include "clock.h"
59fb659b	34	#include "cm2xxx_3xxx.h"
a1391d27 RN	35	#include "cm-regbits-34xx.h"
	36
	37	/* CM_AUTOIDLE_PLL.AUTO_ bit values */
	38	#define DPLL_AUTOIDLE_DISABLE 0x0
	39	#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
	40
	41	#define MAX_DPLL_WAIT_TRIES 1000000
	42
60c3f651	43	/* Private functions */
a1391d27 RN	44
a1391d27 RN	45	/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
32cc0021	46	static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
a1391d27 RN	47	{
	48	const struct dpll_data *dd;
	49	u32 v;
	50
	51	dd = clk->dpll_data;
	52
	53	v = __raw_readl(dd->control_reg);
	54	v &= ~dd->enable_mask;
	55	v \|= clken_bits << __ffs(dd->enable_mask);
	56	__raw_writel(v, dd->control_reg);
	57	}
	58
	59	/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
32cc0021	60	static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
a1391d27 RN	61	{
	62	const struct dpll_data *dd;
	63	int i = 0;
	64	int ret = -EINVAL;
5dcc3b97	65	const char *clk_name;
a1391d27 RN	66
a1391d27 RN	67	dd = clk->dpll_data;
32cc0021	68	clk_name = __clk_get_name(clk->hw.clk);
a1391d27 RN	69
	70	state <<= __ffs(dd->idlest_mask);
	71
	72	while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
	73	i < MAX_DPLL_WAIT_TRIES) {
	74	i++;
	75	udelay(1);
	76	}
	77
	78	if (i == MAX_DPLL_WAIT_TRIES) {
	79	printk(KERN_ERR "clock: %s failed transition to '%s'\n",
5dcc3b97	80	clk_name, (state) ? "locked" : "bypassed");
a1391d27 RN	81	} else {
a1391d27 RN	82	pr_debug("clock: %s transition to '%s' in %d loops\n",
5dcc3b97	83	clk_name, (state) ? "locked" : "bypassed", i);
a1391d27 RN	84
	85	ret = 0;
	86	}
	87
	88	return ret;
	89	}
	90
	91	/* From 3430 TRM ES2 4.7.6.2 */
32cc0021	92	static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
a1391d27 RN	93	{
	94	unsigned long fint;
	95	u16 f = 0;
	96
5dcc3b97	97	fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
a1391d27 RN	98
	99	pr_debug("clock: fint is %lu\n", fint);
	100
	101	if (fint >= 750000 && fint <= 1000000)
	102	f = 0x3;
	103	else if (fint > 1000000 && fint <= 1250000)
	104	f = 0x4;
	105	else if (fint > 1250000 && fint <= 1500000)
	106	f = 0x5;
	107	else if (fint > 1500000 && fint <= 1750000)
	108	f = 0x6;
	109	else if (fint > 1750000 && fint <= 2100000)
	110	f = 0x7;
	111	else if (fint > 7500000 && fint <= 10000000)
	112	f = 0xB;
	113	else if (fint > 10000000 && fint <= 12500000)
	114	f = 0xC;
	115	else if (fint > 12500000 && fint <= 15000000)
	116	f = 0xD;
	117	else if (fint > 15000000 && fint <= 17500000)
	118	f = 0xE;
	119	else if (fint > 17500000 && fint <= 21000000)
	120	f = 0xF;
	121	else
	122	pr_debug("clock: unknown freqsel setting for %d\n", n);
	123
	124	return f;
	125	}
	126
a1391d27 RN	127	/*
	128	* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
	129	* @clk: pointer to a DPLL struct clk
	130	*
	131	* Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
	132	* readiness before returning. Will save and restore the DPLL's
	133	* autoidle state across the enable, per the CDP code. If the DPLL
	134	* locked successfully, return 0; if the DPLL did not lock in the time
	135	* allotted, or DPLL3 was passed in, return -EINVAL.
	136	*/
32cc0021	137	static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
a1391d27	138	{
55ffe163	139	const struct dpll_data *dd;
a1391d27	140	u8 ai;
55ffe163 VP	141	u8 state = 1;
55ffe163 VP	142	int r = 0;
a1391d27	143
32cc0021	144	pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
a1391d27	145
55ffe163 VP	146	dd = clk->dpll_data;
	147	state <<= __ffs(dd->idlest_mask);
	148
	149	/* Check if already locked */
	150	if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
	151	goto done;
	152
a1391d27 RN	153	ai = omap3_dpll_autoidle_read(clk);
a1391d27 RN	154
d76316fe VB	155	if (ai)
d76316fe VB	156	omap3_dpll_deny_idle(clk);
a1391d27 RN	157
	158	_omap3_dpll_write_clken(clk, DPLL_LOCKED);
	159
	160	r = _omap3_wait_dpll_status(clk, 1);
	161
	162	if (ai)
	163	omap3_dpll_allow_idle(clk);
	164
55ffe163	165	done:
a1391d27 RN	166	return r;
	167	}
	168
	169	/*
	170	* _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
	171	* @clk: pointer to a DPLL struct clk
	172	*
	173	* Instructs a non-CORE DPLL to enter low-power bypass mode. In
	174	* bypass mode, the DPLL's rate is set equal to its parent clock's
	175	* rate. Waits for the DPLL to report readiness before returning.
	176	* Will save and restore the DPLL's autoidle state across the enable,
	177	* per the CDP code. If the DPLL entered bypass mode successfully,
	178	* return 0; if the DPLL did not enter bypass in the time allotted, or
	179	* DPLL3 was passed in, or the DPLL does not support low-power bypass,
	180	* return -EINVAL.
	181	*/
32cc0021	182	static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
a1391d27 RN	183	{
	184	int r;
	185	u8 ai;
	186
	187	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
	188	return -EINVAL;
	189
	190	pr_debug("clock: configuring DPLL %s for low-power bypass\n",
32cc0021	191	__clk_get_name(clk->hw.clk));
a1391d27 RN	192
	193	ai = omap3_dpll_autoidle_read(clk);
	194
	195	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
	196
	197	r = _omap3_wait_dpll_status(clk, 0);
	198
	199	if (ai)
	200	omap3_dpll_allow_idle(clk);
a1391d27 RN	201
	202	return r;
	203	}
	204
	205	/*
	206	* _omap3_noncore_dpll_stop - instruct a DPLL to stop
	207	* @clk: pointer to a DPLL struct clk
	208	*
	209	* Instructs a non-CORE DPLL to enter low-power stop. Will save and
	210	* restore the DPLL's autoidle state across the stop, per the CDP
	211	* code. If DPLL3 was passed in, or the DPLL does not support
	212	* low-power stop, return -EINVAL; otherwise, return 0.
	213	*/
32cc0021	214	static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
a1391d27 RN	215	{
	216	u8 ai;
	217
	218	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
	219	return -EINVAL;
	220
32cc0021	221	pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
a1391d27 RN	222
	223	ai = omap3_dpll_autoidle_read(clk);
	224
	225	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
	226
	227	if (ai)
	228	omap3_dpll_allow_idle(clk);
a1391d27 RN	229
	230	return 0;
	231	}
	232
358965d7	233	/**
a36795c1	234	* _lookup_dco - Lookup DCO used by j-type DPLL
358965d7 RW	235	* @clk: pointer to a DPLL struct clk
358965d7 RW	236	* @dco: digital control oscillator selector
358965d7 RW	237	* @m: DPLL multiplier to set
	238	* @n: DPLL divider to set
	239	*
	240	* See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
	241	*
	242	* XXX This code is not needed for 3430/AM35xx; can it be optimized
	243	* out in non-multi-OMAP builds for those chips?
	244	*/
32cc0021	245	static void _lookup_dco(struct clk_hw_omap clk, u8 dco, u16 m, u8 n)
358965d7	246	{
a36795c1	247	unsigned long fint, clkinp; /* watch out for overflow */
358965d7	248
32cc0021	249	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
358965d7 RW	250	fint = (clkinp / n) * m;
	251
	252	if (fint < 1000000000)
	253	*dco = 2;
	254	else
	255	*dco = 4;
a36795c1 JH	256	}
	257
	258	/**
	259	* _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
	260	* @clk: pointer to a DPLL struct clk
	261	* @sd_div: target sigma-delta divider
	262	* @m: DPLL multiplier to set
	263	* @n: DPLL divider to set
	264	*
	265	* See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
	266	*
	267	* XXX This code is not needed for 3430/AM35xx; can it be optimized
	268	* out in non-multi-OMAP builds for those chips?
	269	*/
32cc0021	270	static void _lookup_sddiv(struct clk_hw_omap clk, u8 sd_div, u16 m, u8 n)
a36795c1 JH	271	{
	272	unsigned long clkinp, sd; /* watch out for overflow */
	273	int mod1, mod2;
	274
32cc0021	275	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
a36795c1	276
358965d7 RW	277	/*
	278	* target sigma-delta to near 250MHz
	279	* sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
	280	*/
	281	clkinp /= 100000; /* shift from MHz to 10Hz for 38.4 and 19.2 /
	282	mod1 = (clkinp * m) % (250 * n);
	283	sd = (clkinp * m) / (250 * n);
	284	mod2 = sd % 10;
	285	sd /= 10;
	286
	287	if (mod1 \|\| mod2)
	288	sd++;
	289	*sd_div = sd;
	290	}
	291
60c3f651 PW	292	/*
	293	* _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
	294	* @clk: struct clk * of DPLL to set
	295	* @m: DPLL multiplier to set
	296	* @n: DPLL divider to set
	297	* @freqsel: FREQSEL value to set
	298	*
	299	* Program the DPLL with the supplied M, N values, and wait for the DPLL to
	300	* lock.. Returns -EINVAL upon error, or 0 upon success.
	301	*/
32cc0021 MT	302	static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
32cc0021 MT	303	u16 freqsel)
60c3f651 PW	304	{
60c3f651 PW	305	struct dpll_data *dd = clk->dpll_data;
a36795c1	306	u8 dco, sd_div;
60c3f651 PW	307	u32 v;
	308
	309	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
	310	_omap3_noncore_dpll_bypass(clk);
	311
5eb75f55 VB	312	/*
	313	* Set jitter correction. No jitter correction for OMAP4 and 3630
	314	* since freqsel field is no longer present
	315	*/
78da2640	316	if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
60c3f651 PW	317	v = __raw_readl(dd->control_reg);
	318	v &= ~dd->freqsel_mask;
	319	v \|= freqsel << __ffs(dd->freqsel_mask);
	320	__raw_writel(v, dd->control_reg);
	321	}
	322
	323	/* Set DPLL multiplier, divider */
	324	v = __raw_readl(dd->mult_div1_reg);
	325	v &= ~(dd->mult_mask \| dd->div1_mask);
	326	v \|= m << __ffs(dd->mult_mask);
	327	v \|= (n - 1) << __ffs(dd->div1_mask);
358965d7	328
a36795c1 JH	329	/* Configure dco and sd_div for dplls that have these fields */
	330	if (dd->dco_mask) {
	331	_lookup_dco(clk, &dco, m, n);
	332	v &= ~(dd->dco_mask);
	333	v \|= dco << __ffs(dd->dco_mask);
	334	}
	335	if (dd->sddiv_mask) {
	336	_lookup_sddiv(clk, &sd_div, m, n);
	337	v &= ~(dd->sddiv_mask);
	338	v \|= sd_div << __ffs(dd->sddiv_mask);
358965d7 RW	339	}
358965d7 RW	340
60c3f651 PW	341	__raw_writel(v, dd->mult_div1_reg);
	342
	343	/* We let the clock framework set the other output dividers later */
	344
	345	/* REVISIT: Set ramp-up delay? */
	346
	347	_omap3_noncore_dpll_lock(clk);
	348
	349	return 0;
	350	}
	351
	352	/* Public functions */
	353
	354	/**
	355	* omap3_dpll_recalc - recalculate DPLL rate
	356	* @clk: DPLL struct clk
	357	*
	358	* Recalculate and propagate the DPLL rate.
	359	*/
32cc0021 MT	360	unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
	361	{
	362	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
455db9c9	363
60c3f651 PW	364	return omap2_get_dpll_rate(clk);
	365	}
	366
	367	/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
	368
a1391d27 RN	369	/**
	370	* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
	371	* @clk: pointer to a DPLL struct clk
	372	*
	373	* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
	374	* The choice of modes depends on the DPLL's programmed rate: if it is
	375	* the same as the DPLL's parent clock, it will enter bypass;
	376	* otherwise, it will enter lock. This code will wait for the DPLL to
	377	* indicate readiness before returning, unless the DPLL takes too long
	378	* to enter the target state. Intended to be used as the struct clk's
	379	* enable function. If DPLL3 was passed in, or the DPLL does not
	380	* support low-power stop, or if the DPLL took too long to enter
	381	* bypass or lock, return -EINVAL; otherwise, return 0.
	382	*/
32cc0021 MT	383	int omap3_noncore_dpll_enable(struct clk_hw *hw)
	384	{
	385	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
a1391d27 RN	386	int r;
a1391d27 RN	387	struct dpll_data *dd;
5dcc3b97	388	struct clk *parent;
a1391d27 RN	389
	390	dd = clk->dpll_data;
	391	if (!dd)
	392	return -EINVAL;
	393
32cc0021 MT	394	if (clk->clkdm) {
	395	r = clkdm_clk_enable(clk->clkdm, hw->clk);
	396	if (r) {
	397	WARN(1,
	398	"%s: could not enable %s's clockdomain %s: %d\n",
	399	__func__, __clk_get_name(hw->clk),
	400	clk->clkdm->name, r);
	401	return r;
	402	}
	403	}
	404
	405	parent = __clk_get_parent(hw->clk);
	406
	407	if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
5dcc3b97	408	WARN_ON(parent != dd->clk_bypass);
a1391d27 RN	409	r = _omap3_noncore_dpll_bypass(clk);
a1391d27 RN	410	} else {
5dcc3b97	411	WARN_ON(parent != dd->clk_ref);
a1391d27 RN	412	r = _omap3_noncore_dpll_lock(clk);
a1391d27 RN	413	}
32cc0021	414
a1391d27 RN	415	return r;
	416	}
	417
	418	/**
	419	* omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
	420	* @clk: pointer to a DPLL struct clk
	421	*
	422	* Instructs a non-CORE DPLL to enter low-power stop. This function is
	423	* intended for use in struct clkops. No return value.
	424	*/
32cc0021 MT	425	void omap3_noncore_dpll_disable(struct clk_hw *hw)
	426	{
	427	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	428
	429	_omap3_noncore_dpll_stop(clk);
	430	if (clk->clkdm)
	431	clkdm_clk_disable(clk->clkdm, hw->clk);
a1391d27 RN	432	}
	433
	434
	435	/* Non-CORE DPLL rate set code */
	436
a1391d27 RN	437	/**
	438	* omap3_noncore_dpll_set_rate - set non-core DPLL rate
	439	* @clk: struct clk * of DPLL to set
	440	* @rate: rounded target rate
	441	*
	442	* Set the DPLL CLKOUT to the target rate. If the DPLL can enter
	443	* low-power bypass, and the target rate is the bypass source clock
	444	* rate, then configure the DPLL for bypass. Otherwise, round the
	445	* target rate if it hasn't been done already, then program and lock
	446	* the DPLL. Returns -EINVAL upon error, or 0 upon success.
	447	*/
32cc0021 MT	448	int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
	449	unsigned long parent_rate)
	450	{
	451	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	452	struct clk *new_parent = NULL;
	453	u16 freqsel = 0;
	454	struct dpll_data *dd;
	455	int ret;
	456
	457	if (!hw \|\| !rate)
	458	return -EINVAL;
	459
	460	dd = clk->dpll_data;
	461	if (!dd)
	462	return -EINVAL;
	463
	464	__clk_prepare(dd->clk_bypass);
	465	clk_enable(dd->clk_bypass);
	466	__clk_prepare(dd->clk_ref);
	467	clk_enable(dd->clk_ref);
	468
	469	if (__clk_get_rate(dd->clk_bypass) == rate &&
	470	(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
	471	pr_debug("%s: %s: set rate: entering bypass.\n",
	472	__func__, __clk_get_name(hw->clk));
	473
	474	ret = _omap3_noncore_dpll_bypass(clk);
	475	if (!ret)
	476	new_parent = dd->clk_bypass;
	477	} else {
	478	if (dd->last_rounded_rate != rate)
	479	rate = __clk_round_rate(hw->clk, rate);
	480
	481	if (dd->last_rounded_rate == 0)
	482	return -EINVAL;
	483
	484	/* No freqsel on OMAP4 and OMAP3630 */
	485	if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
	486	freqsel = _omap3_dpll_compute_freqsel(clk,
	487	dd->last_rounded_n);
	488	if (!freqsel)
	489	WARN_ON(1);
	490	}
	491
	492	pr_debug("%s: %s: set rate: locking rate to %lu.\n",
	493	__func__, __clk_get_name(hw->clk), rate);
	494
	495	ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
	496	dd->last_rounded_n, freqsel);
	497	if (!ret)
	498	new_parent = dd->clk_ref;
	499	}
	500	/*
	501	* FIXME - this is all wrong. common code handles reparenting and
	502	* migrating prepare/enable counts. dplls should be a multiplexer
	503	* clock and this should be a set_parent operation so that all of that
	504	* stuff is inherited for free
	505	*/
	506
	507	if (!ret)
	508	__clk_reparent(hw->clk, new_parent);
	509
	510	clk_disable(dd->clk_ref);
	511	__clk_unprepare(dd->clk_ref);
512	clk_disable(dd->clk_bypass);
513	__clk_unprepare(dd->clk_bypass);
514
515	return 0;
516	}
a1391d27 RN	517
	518	/* DPLL autoidle read/set code */
	519
	520	/**
	521	* omap3_dpll_autoidle_read - read a DPLL's autoidle bits
	522	* @clk: struct clk * of the DPLL to read
	523	*
	524	* Return the DPLL's autoidle bits, shifted down to bit 0. Returns
	525	* -EINVAL if passed a null pointer or if the struct clk does not
	526	* appear to refer to a DPLL.
	527	*/
32cc0021	528	u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
a1391d27 RN	529	{
	530	const struct dpll_data *dd;
	531	u32 v;
	532
	533	if (!clk \|\| !clk->dpll_data)
	534	return -EINVAL;
	535
	536	dd = clk->dpll_data;
	537
d76316fe VB	538	if (!dd->autoidle_reg)
	539	return -EINVAL;
	540
a1391d27 RN	541	v = __raw_readl(dd->autoidle_reg);
	542	v &= dd->autoidle_mask;
	543	v >>= __ffs(dd->autoidle_mask);
	544
	545	return v;
	546	}
	547
	548	/**
	549	* omap3_dpll_allow_idle - enable DPLL autoidle bits
	550	* @clk: struct clk * of the DPLL to operate on
	551	*
	552	* Enable DPLL automatic idle control. This automatic idle mode
	553	* switching takes effect only when the DPLL is locked, at least on
	554	* OMAP3430. The DPLL will enter low-power stop when its downstream
	555	* clocks are gated. No return value.
	556	*/
32cc0021	557	void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
a1391d27 RN	558	{
	559	const struct dpll_data *dd;
	560	u32 v;
	561
	562	if (!clk \|\| !clk->dpll_data)
	563	return;
	564
	565	dd = clk->dpll_data;
	566
455db9c9	567	if (!dd->autoidle_reg)
d76316fe	568	return;
d76316fe	569
a1391d27 RN	570	/*
	571	* REVISIT: CORE DPLL can optionally enter low-power bypass
	572	* by writing 0x5 instead of 0x1. Add some mechanism to
	573	* optionally enter this mode.
	574	*/
	575	v = __raw_readl(dd->autoidle_reg);
	576	v &= ~dd->autoidle_mask;
	577	v \|= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
	578	__raw_writel(v, dd->autoidle_reg);
d76316fe	579
a1391d27 RN	580	}
	581
	582	/**
	583	* omap3_dpll_deny_idle - prevent DPLL from automatically idling
	584	* @clk: struct clk * of the DPLL to operate on
	585	*
	586	* Disable DPLL automatic idle control. No return value.
	587	*/
32cc0021	588	void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
a1391d27 RN	589	{
	590	const struct dpll_data *dd;
	591	u32 v;
	592
	593	if (!clk \|\| !clk->dpll_data)
	594	return;
	595
	596	dd = clk->dpll_data;
	597
455db9c9	598	if (!dd->autoidle_reg)
d76316fe	599	return;
d76316fe	600
a1391d27 RN	601	v = __raw_readl(dd->autoidle_reg);
	602	v &= ~dd->autoidle_mask;
	603	v \|= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
	604	__raw_writel(v, dd->autoidle_reg);
	605
	606	}
	607
	608	/* Clock control for DPLL outputs */
	609
	610	/**
	611	* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
	612	* @clk: DPLL output struct clk
	613	*
	614	* Using parent clock DPLL data, look up DPLL state. If locked, set our
	615	* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
	616	*/
32cc0021 MT	617	unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
	618	unsigned long parent_rate)
	619	{
	620	const struct dpll_data *dd;
	621	unsigned long rate;
	622	u32 v;
	623	struct clk_hw_omap *pclk = NULL;
	624	struct clk *parent;
	625
	626	/* Walk up the parents of clk, looking for a DPLL */
	627	do {
	628	do {
	629	parent = __clk_get_parent(hw->clk);
	630	hw = __clk_get_hw(parent);
	631	} while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
	632	if (!hw)
	633	break;
	634	pclk = to_clk_hw_omap(hw);
	635	} while (pclk && !pclk->dpll_data);
a1391d27	636
a032d33b PW	637	/* clk does not have a DPLL as a parent? error in the clock data */
	638	if (!pclk) {
	639	WARN_ON(1);
	640	return 0;
	641	}
a1391d27 RN	642
	643	dd = pclk->dpll_data;
	644
	645	WARN_ON(!dd->enable_mask);
	646
	647	v = __raw_readl(dd->control_reg) & dd->enable_mask;
	648	v >>= __ffs(dd->enable_mask);
358965d7	649	if ((v != OMAP3XXX_EN_DPLL_LOCKED) \|\| (dd->flags & DPLL_J_TYPE))
5dcc3b97	650	rate = parent_rate;
a1391d27	651	else
5dcc3b97	652	rate = parent_rate * 2;
a1391d27 RN	653	return rate;
a1391d27 RN	654	}
353cec46 VH	655
353cec46 VH	656	/* OMAP3/4 non-CORE DPLL clkops */
32cc0021 MT	657	const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
	658	.allow_idle = omap3_dpll_allow_idle,
	659	.deny_idle = omap3_dpll_deny_idle,
	660	};