Commit | Line | Data |
---|---|---|
a1391d27 RN |
1 | /* |
2 | * OMAP3/4 - specific DPLL control functions | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments, Inc. | |
5 | * Copyright (C) 2009 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
8 | * Testing and integration fixes by Jouni Högander | |
9 | * | |
10 | * Parts of this code are based on code written by | |
11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/limits.h> | |
27 | #include <linux/bitops.h> | |
28 | ||
16975a79 RN |
29 | #include <plat/cpu.h> |
30 | #include <plat/clock.h> | |
31 | #include <plat/sram.h> | |
a1391d27 RN |
32 | #include <asm/div64.h> |
33 | #include <asm/clkdev.h> | |
34 | ||
35 | #include "clock.h" | |
36 | #include "prm.h" | |
37 | #include "prm-regbits-34xx.h" | |
38 | #include "cm.h" | |
39 | #include "cm-regbits-34xx.h" | |
40 | ||
41 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | |
42 | #define DPLL_AUTOIDLE_DISABLE 0x0 | |
43 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | |
44 | ||
45 | #define MAX_DPLL_WAIT_TRIES 1000000 | |
46 | ||
60c3f651 | 47 | /* Private functions */ |
a1391d27 RN |
48 | |
49 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | |
50 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | |
51 | { | |
52 | const struct dpll_data *dd; | |
53 | u32 v; | |
54 | ||
55 | dd = clk->dpll_data; | |
56 | ||
57 | v = __raw_readl(dd->control_reg); | |
58 | v &= ~dd->enable_mask; | |
59 | v |= clken_bits << __ffs(dd->enable_mask); | |
60 | __raw_writel(v, dd->control_reg); | |
61 | } | |
62 | ||
63 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | |
64 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |
65 | { | |
66 | const struct dpll_data *dd; | |
67 | int i = 0; | |
68 | int ret = -EINVAL; | |
69 | ||
70 | dd = clk->dpll_data; | |
71 | ||
72 | state <<= __ffs(dd->idlest_mask); | |
73 | ||
74 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && | |
75 | i < MAX_DPLL_WAIT_TRIES) { | |
76 | i++; | |
77 | udelay(1); | |
78 | } | |
79 | ||
80 | if (i == MAX_DPLL_WAIT_TRIES) { | |
81 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | |
82 | clk->name, (state) ? "locked" : "bypassed"); | |
83 | } else { | |
84 | pr_debug("clock: %s transition to '%s' in %d loops\n", | |
85 | clk->name, (state) ? "locked" : "bypassed", i); | |
86 | ||
87 | ret = 0; | |
88 | } | |
89 | ||
90 | return ret; | |
91 | } | |
92 | ||
93 | /* From 3430 TRM ES2 4.7.6.2 */ | |
94 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | |
95 | { | |
96 | unsigned long fint; | |
97 | u16 f = 0; | |
98 | ||
99 | fint = clk->dpll_data->clk_ref->rate / n; | |
100 | ||
101 | pr_debug("clock: fint is %lu\n", fint); | |
102 | ||
103 | if (fint >= 750000 && fint <= 1000000) | |
104 | f = 0x3; | |
105 | else if (fint > 1000000 && fint <= 1250000) | |
106 | f = 0x4; | |
107 | else if (fint > 1250000 && fint <= 1500000) | |
108 | f = 0x5; | |
109 | else if (fint > 1500000 && fint <= 1750000) | |
110 | f = 0x6; | |
111 | else if (fint > 1750000 && fint <= 2100000) | |
112 | f = 0x7; | |
113 | else if (fint > 7500000 && fint <= 10000000) | |
114 | f = 0xB; | |
115 | else if (fint > 10000000 && fint <= 12500000) | |
116 | f = 0xC; | |
117 | else if (fint > 12500000 && fint <= 15000000) | |
118 | f = 0xD; | |
119 | else if (fint > 15000000 && fint <= 17500000) | |
120 | f = 0xE; | |
121 | else if (fint > 17500000 && fint <= 21000000) | |
122 | f = 0xF; | |
123 | else | |
124 | pr_debug("clock: unknown freqsel setting for %d\n", n); | |
125 | ||
126 | return f; | |
127 | } | |
128 | ||
a1391d27 RN |
129 | /* |
130 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | |
131 | * @clk: pointer to a DPLL struct clk | |
132 | * | |
133 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | |
134 | * readiness before returning. Will save and restore the DPLL's | |
135 | * autoidle state across the enable, per the CDP code. If the DPLL | |
136 | * locked successfully, return 0; if the DPLL did not lock in the time | |
137 | * allotted, or DPLL3 was passed in, return -EINVAL. | |
138 | */ | |
139 | static int _omap3_noncore_dpll_lock(struct clk *clk) | |
140 | { | |
141 | u8 ai; | |
142 | int r; | |
143 | ||
144 | pr_debug("clock: locking DPLL %s\n", clk->name); | |
145 | ||
146 | ai = omap3_dpll_autoidle_read(clk); | |
147 | ||
148 | omap3_dpll_deny_idle(clk); | |
149 | ||
150 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | |
151 | ||
152 | r = _omap3_wait_dpll_status(clk, 1); | |
153 | ||
154 | if (ai) | |
155 | omap3_dpll_allow_idle(clk); | |
156 | ||
157 | return r; | |
158 | } | |
159 | ||
160 | /* | |
161 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | |
162 | * @clk: pointer to a DPLL struct clk | |
163 | * | |
164 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | |
165 | * bypass mode, the DPLL's rate is set equal to its parent clock's | |
166 | * rate. Waits for the DPLL to report readiness before returning. | |
167 | * Will save and restore the DPLL's autoidle state across the enable, | |
168 | * per the CDP code. If the DPLL entered bypass mode successfully, | |
169 | * return 0; if the DPLL did not enter bypass in the time allotted, or | |
170 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | |
171 | * return -EINVAL. | |
172 | */ | |
173 | static int _omap3_noncore_dpll_bypass(struct clk *clk) | |
174 | { | |
175 | int r; | |
176 | u8 ai; | |
177 | ||
178 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | |
179 | return -EINVAL; | |
180 | ||
181 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | |
182 | clk->name); | |
183 | ||
184 | ai = omap3_dpll_autoidle_read(clk); | |
185 | ||
186 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | |
187 | ||
188 | r = _omap3_wait_dpll_status(clk, 0); | |
189 | ||
190 | if (ai) | |
191 | omap3_dpll_allow_idle(clk); | |
192 | else | |
193 | omap3_dpll_deny_idle(clk); | |
194 | ||
195 | return r; | |
196 | } | |
197 | ||
198 | /* | |
199 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | |
200 | * @clk: pointer to a DPLL struct clk | |
201 | * | |
202 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | |
203 | * restore the DPLL's autoidle state across the stop, per the CDP | |
204 | * code. If DPLL3 was passed in, or the DPLL does not support | |
205 | * low-power stop, return -EINVAL; otherwise, return 0. | |
206 | */ | |
207 | static int _omap3_noncore_dpll_stop(struct clk *clk) | |
208 | { | |
209 | u8 ai; | |
210 | ||
211 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | |
212 | return -EINVAL; | |
213 | ||
214 | pr_debug("clock: stopping DPLL %s\n", clk->name); | |
215 | ||
216 | ai = omap3_dpll_autoidle_read(clk); | |
217 | ||
218 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | |
219 | ||
220 | if (ai) | |
221 | omap3_dpll_allow_idle(clk); | |
222 | else | |
223 | omap3_dpll_deny_idle(clk); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
60c3f651 PW |
228 | /* |
229 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | |
230 | * @clk: struct clk * of DPLL to set | |
231 | * @m: DPLL multiplier to set | |
232 | * @n: DPLL divider to set | |
233 | * @freqsel: FREQSEL value to set | |
234 | * | |
235 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | |
236 | * lock.. Returns -EINVAL upon error, or 0 upon success. | |
237 | */ | |
238 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |
239 | { | |
240 | struct dpll_data *dd = clk->dpll_data; | |
241 | u32 v; | |
242 | ||
243 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | |
244 | _omap3_noncore_dpll_bypass(clk); | |
245 | ||
5eb75f55 VB |
246 | /* |
247 | * Set jitter correction. No jitter correction for OMAP4 and 3630 | |
248 | * since freqsel field is no longer present | |
249 | */ | |
250 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | |
60c3f651 PW |
251 | v = __raw_readl(dd->control_reg); |
252 | v &= ~dd->freqsel_mask; | |
253 | v |= freqsel << __ffs(dd->freqsel_mask); | |
254 | __raw_writel(v, dd->control_reg); | |
255 | } | |
256 | ||
257 | /* Set DPLL multiplier, divider */ | |
258 | v = __raw_readl(dd->mult_div1_reg); | |
259 | v &= ~(dd->mult_mask | dd->div1_mask); | |
260 | v |= m << __ffs(dd->mult_mask); | |
261 | v |= (n - 1) << __ffs(dd->div1_mask); | |
262 | __raw_writel(v, dd->mult_div1_reg); | |
263 | ||
264 | /* We let the clock framework set the other output dividers later */ | |
265 | ||
266 | /* REVISIT: Set ramp-up delay? */ | |
267 | ||
268 | _omap3_noncore_dpll_lock(clk); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | /* Public functions */ | |
274 | ||
275 | /** | |
276 | * omap3_dpll_recalc - recalculate DPLL rate | |
277 | * @clk: DPLL struct clk | |
278 | * | |
279 | * Recalculate and propagate the DPLL rate. | |
280 | */ | |
281 | unsigned long omap3_dpll_recalc(struct clk *clk) | |
282 | { | |
283 | return omap2_get_dpll_rate(clk); | |
284 | } | |
285 | ||
286 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | |
287 | ||
a1391d27 RN |
288 | /** |
289 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
290 | * @clk: pointer to a DPLL struct clk | |
291 | * | |
292 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
293 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
294 | * the same as the DPLL's parent clock, it will enter bypass; | |
295 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
296 | * indicate readiness before returning, unless the DPLL takes too long | |
297 | * to enter the target state. Intended to be used as the struct clk's | |
298 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
299 | * support low-power stop, or if the DPLL took too long to enter | |
300 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
301 | */ | |
302 | int omap3_noncore_dpll_enable(struct clk *clk) | |
303 | { | |
304 | int r; | |
305 | struct dpll_data *dd; | |
306 | ||
307 | dd = clk->dpll_data; | |
308 | if (!dd) | |
309 | return -EINVAL; | |
310 | ||
311 | if (clk->rate == dd->clk_bypass->rate) { | |
312 | WARN_ON(clk->parent != dd->clk_bypass); | |
313 | r = _omap3_noncore_dpll_bypass(clk); | |
314 | } else { | |
315 | WARN_ON(clk->parent != dd->clk_ref); | |
316 | r = _omap3_noncore_dpll_lock(clk); | |
317 | } | |
318 | /* | |
319 | *FIXME: this is dubious - if clk->rate has changed, what about | |
320 | * propagating? | |
321 | */ | |
322 | if (!r) | |
323 | clk->rate = omap2_get_dpll_rate(clk); | |
324 | ||
325 | return r; | |
326 | } | |
327 | ||
328 | /** | |
329 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop | |
330 | * @clk: pointer to a DPLL struct clk | |
331 | * | |
332 | * Instructs a non-CORE DPLL to enter low-power stop. This function is | |
333 | * intended for use in struct clkops. No return value. | |
334 | */ | |
335 | void omap3_noncore_dpll_disable(struct clk *clk) | |
336 | { | |
337 | _omap3_noncore_dpll_stop(clk); | |
338 | } | |
339 | ||
340 | ||
341 | /* Non-CORE DPLL rate set code */ | |
342 | ||
a1391d27 RN |
343 | /** |
344 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | |
345 | * @clk: struct clk * of DPLL to set | |
346 | * @rate: rounded target rate | |
347 | * | |
348 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | |
349 | * low-power bypass, and the target rate is the bypass source clock | |
350 | * rate, then configure the DPLL for bypass. Otherwise, round the | |
351 | * target rate if it hasn't been done already, then program and lock | |
352 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | |
353 | */ | |
354 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |
355 | { | |
356 | struct clk *new_parent = NULL; | |
16975a79 | 357 | u16 freqsel = 0; |
a1391d27 RN |
358 | struct dpll_data *dd; |
359 | int ret; | |
360 | ||
361 | if (!clk || !rate) | |
362 | return -EINVAL; | |
363 | ||
364 | dd = clk->dpll_data; | |
365 | if (!dd) | |
366 | return -EINVAL; | |
367 | ||
368 | if (rate == omap2_get_dpll_rate(clk)) | |
369 | return 0; | |
370 | ||
371 | /* | |
372 | * Ensure both the bypass and ref clocks are enabled prior to | |
373 | * doing anything; we need the bypass clock running to reprogram | |
374 | * the DPLL. | |
375 | */ | |
376 | omap2_clk_enable(dd->clk_bypass); | |
377 | omap2_clk_enable(dd->clk_ref); | |
378 | ||
379 | if (dd->clk_bypass->rate == rate && | |
380 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | |
381 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | |
382 | ||
383 | ret = _omap3_noncore_dpll_bypass(clk); | |
384 | if (!ret) | |
385 | new_parent = dd->clk_bypass; | |
386 | } else { | |
387 | if (dd->last_rounded_rate != rate) | |
388 | omap2_dpll_round_rate(clk, rate); | |
389 | ||
390 | if (dd->last_rounded_rate == 0) | |
391 | return -EINVAL; | |
392 | ||
5eb75f55 VB |
393 | /* No freqsel on OMAP4 and OMAP3630 */ |
394 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | |
16975a79 RN |
395 | freqsel = _omap3_dpll_compute_freqsel(clk, |
396 | dd->last_rounded_n); | |
397 | if (!freqsel) | |
398 | WARN_ON(1); | |
399 | } | |
a1391d27 RN |
400 | |
401 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | |
402 | clk->name, rate); | |
403 | ||
404 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | |
405 | dd->last_rounded_n, freqsel); | |
406 | if (!ret) | |
407 | new_parent = dd->clk_ref; | |
408 | } | |
409 | if (!ret) { | |
410 | /* | |
411 | * Switch the parent clock in the heirarchy, and make sure | |
412 | * that the new parent's usecount is correct. Note: we | |
413 | * enable the new parent before disabling the old to avoid | |
414 | * any unnecessary hardware disable->enable transitions. | |
415 | */ | |
416 | if (clk->usecount) { | |
417 | omap2_clk_enable(new_parent); | |
418 | omap2_clk_disable(clk->parent); | |
419 | } | |
420 | clk_reparent(clk, new_parent); | |
421 | clk->rate = rate; | |
422 | } | |
423 | omap2_clk_disable(dd->clk_ref); | |
424 | omap2_clk_disable(dd->clk_bypass); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | /* DPLL autoidle read/set code */ | |
430 | ||
431 | /** | |
432 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | |
433 | * @clk: struct clk * of the DPLL to read | |
434 | * | |
435 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | |
436 | * -EINVAL if passed a null pointer or if the struct clk does not | |
437 | * appear to refer to a DPLL. | |
438 | */ | |
439 | u32 omap3_dpll_autoidle_read(struct clk *clk) | |
440 | { | |
441 | const struct dpll_data *dd; | |
442 | u32 v; | |
443 | ||
444 | if (!clk || !clk->dpll_data) | |
445 | return -EINVAL; | |
446 | ||
447 | dd = clk->dpll_data; | |
448 | ||
449 | v = __raw_readl(dd->autoidle_reg); | |
450 | v &= dd->autoidle_mask; | |
451 | v >>= __ffs(dd->autoidle_mask); | |
452 | ||
453 | return v; | |
454 | } | |
455 | ||
456 | /** | |
457 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | |
458 | * @clk: struct clk * of the DPLL to operate on | |
459 | * | |
460 | * Enable DPLL automatic idle control. This automatic idle mode | |
461 | * switching takes effect only when the DPLL is locked, at least on | |
462 | * OMAP3430. The DPLL will enter low-power stop when its downstream | |
463 | * clocks are gated. No return value. | |
464 | */ | |
465 | void omap3_dpll_allow_idle(struct clk *clk) | |
466 | { | |
467 | const struct dpll_data *dd; | |
468 | u32 v; | |
469 | ||
470 | if (!clk || !clk->dpll_data) | |
471 | return; | |
472 | ||
473 | dd = clk->dpll_data; | |
474 | ||
475 | /* | |
476 | * REVISIT: CORE DPLL can optionally enter low-power bypass | |
477 | * by writing 0x5 instead of 0x1. Add some mechanism to | |
478 | * optionally enter this mode. | |
479 | */ | |
480 | v = __raw_readl(dd->autoidle_reg); | |
481 | v &= ~dd->autoidle_mask; | |
482 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | |
483 | __raw_writel(v, dd->autoidle_reg); | |
484 | } | |
485 | ||
486 | /** | |
487 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | |
488 | * @clk: struct clk * of the DPLL to operate on | |
489 | * | |
490 | * Disable DPLL automatic idle control. No return value. | |
491 | */ | |
492 | void omap3_dpll_deny_idle(struct clk *clk) | |
493 | { | |
494 | const struct dpll_data *dd; | |
495 | u32 v; | |
496 | ||
497 | if (!clk || !clk->dpll_data) | |
498 | return; | |
499 | ||
500 | dd = clk->dpll_data; | |
501 | ||
502 | v = __raw_readl(dd->autoidle_reg); | |
503 | v &= ~dd->autoidle_mask; | |
504 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | |
505 | __raw_writel(v, dd->autoidle_reg); | |
506 | ||
507 | } | |
508 | ||
509 | /* Clock control for DPLL outputs */ | |
510 | ||
511 | /** | |
512 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | |
513 | * @clk: DPLL output struct clk | |
514 | * | |
515 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | |
516 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | |
517 | */ | |
518 | unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |
519 | { | |
520 | const struct dpll_data *dd; | |
521 | unsigned long rate; | |
522 | u32 v; | |
523 | struct clk *pclk; | |
524 | ||
525 | /* Walk up the parents of clk, looking for a DPLL */ | |
526 | pclk = clk->parent; | |
527 | while (pclk && !pclk->dpll_data) | |
528 | pclk = pclk->parent; | |
529 | ||
530 | /* clk does not have a DPLL as a parent? */ | |
531 | WARN_ON(!pclk); | |
532 | ||
533 | dd = pclk->dpll_data; | |
534 | ||
535 | WARN_ON(!dd->enable_mask); | |
536 | ||
537 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | |
538 | v >>= __ffs(dd->enable_mask); | |
539 | if (v != OMAP3XXX_EN_DPLL_LOCKED) | |
540 | rate = clk->parent->rate; | |
541 | else | |
542 | rate = clk->parent->rate * 2; | |
543 | return rate; | |
544 | } |