Commit | Line | Data |
---|---|---|
97f67898 RN |
1 | /* |
2 | * OMAP4-specific DPLL control functions | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Rajendra Nayak | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/bitops.h> | |
17 | ||
dbc04161 | 18 | #include "soc.h" |
97f67898 | 19 | #include "clock.h" |
a1900f2e | 20 | #include "clock44xx.h" |
97f67898 RN |
21 | #include "cm-regbits-44xx.h" |
22 | ||
23 | /* Supported only on OMAP4 */ | |
32cc0021 | 24 | int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) |
97f67898 RN |
25 | { |
26 | u32 v; | |
27 | u32 mask; | |
28 | ||
29 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | |
30 | return -EINVAL; | |
31 | ||
32 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
33 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
34 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
35 | ||
36 | v = __raw_readl(clk->clksel_reg); | |
37 | v &= mask; | |
38 | v >>= __ffs(mask); | |
39 | ||
40 | return v; | |
41 | } | |
42 | ||
32cc0021 | 43 | void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
44 | { |
45 | u32 v; | |
46 | u32 mask; | |
47 | ||
48 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | |
49 | return; | |
50 | ||
51 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
52 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
53 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
54 | ||
55 | v = __raw_readl(clk->clksel_reg); | |
56 | /* Clear the bit to allow gatectrl */ | |
57 | v &= ~mask; | |
58 | __raw_writel(v, clk->clksel_reg); | |
59 | } | |
60 | ||
32cc0021 | 61 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
62 | { |
63 | u32 v; | |
64 | u32 mask; | |
65 | ||
66 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | |
67 | return; | |
68 | ||
69 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
70 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
71 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
72 | ||
73 | v = __raw_readl(clk->clksel_reg); | |
74 | /* Set the bit to deny gatectrl */ | |
75 | v |= mask; | |
76 | __raw_writel(v, clk->clksel_reg); | |
77 | } | |
70db8a62 | 78 | |
32cc0021 MT |
79 | const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { |
80 | .allow_idle = omap4_dpllmx_allow_gatectrl, | |
81 | .deny_idle = omap4_dpllmx_deny_gatectrl, | |
82 | }; | |
70db8a62 | 83 | |
a1900f2e MT |
84 | /** |
85 | * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit | |
86 | * @clk: struct clk * of the DPLL to compute the rate for | |
87 | * | |
88 | * Compute the output rate for the OMAP4 DPLL represented by @clk. | |
89 | * Takes the REGM4XEN bit into consideration, which is needed for the | |
90 | * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) | |
91 | * upon success, or 0 upon error. | |
92 | */ | |
32cc0021 MT |
93 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
94 | unsigned long parent_rate) | |
95 | { | |
96 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
97 | u32 v; |
98 | unsigned long rate; | |
99 | struct dpll_data *dd; | |
100 | ||
101 | if (!clk || !clk->dpll_data) | |
102 | return 0; | |
103 | ||
104 | dd = clk->dpll_data; | |
105 | ||
106 | rate = omap2_get_dpll_rate(clk); | |
107 | ||
108 | /* regm4xen adds a multiplier of 4 to DPLL calculations */ | |
109 | v = __raw_readl(dd->control_reg); | |
110 | if (v & OMAP4430_DPLL_REGM4XEN_MASK) | |
111 | rate *= OMAP4430_REGM4XEN_MULT; | |
112 | ||
113 | return rate; | |
114 | } | |
115 | ||
116 | /** | |
117 | * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit | |
118 | * @clk: struct clk * of the DPLL to round a rate for | |
119 | * @target_rate: the desired rate of the DPLL | |
120 | * | |
121 | * Compute the rate that would be programmed into the DPLL hardware | |
122 | * for @clk if set_rate() were to be provided with the rate | |
123 | * @target_rate. Takes the REGM4XEN bit into consideration, which is | |
124 | * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before | |
125 | * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or | |
126 | * ~0 if an error occurred in omap2_dpll_round_rate(). | |
127 | */ | |
32cc0021 MT |
128 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, |
129 | unsigned long target_rate, | |
130 | unsigned long *parent_rate) | |
131 | { | |
132 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
133 | u32 v; |
134 | struct dpll_data *dd; | |
135 | long r; | |
136 | ||
137 | if (!clk || !clk->dpll_data) | |
138 | return -EINVAL; | |
139 | ||
140 | dd = clk->dpll_data; | |
141 | ||
142 | /* regm4xen adds a multiplier of 4 to DPLL calculations */ | |
143 | v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK; | |
144 | ||
145 | if (v) | |
146 | target_rate = target_rate / OMAP4430_REGM4XEN_MULT; | |
147 | ||
32cc0021 | 148 | r = omap2_dpll_round_rate(hw, target_rate, NULL); |
a1900f2e MT |
149 | if (r == ~0) |
150 | return r; | |
151 | ||
152 | if (v) | |
153 | clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; | |
154 | ||
155 | return clk->dpll_data->last_rounded_rate; | |
156 | } |