Commit | Line | Data |
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2f70a1e9 VS |
1 | /* |
2 | * gpmc-nand.c | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Vimal Singh <vimalsingh@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
d5ce2b65 | 15 | #include <linux/mtd/nand.h> |
2203747c | 16 | #include <linux/platform_data/mtd-nand-omap2.h> |
2f70a1e9 VS |
17 | |
18 | #include <asm/mach/flash.h> | |
19 | ||
3ef5d007 | 20 | #include "gpmc.h" |
dbc04161 | 21 | #include "soc.h" |
bc3668ea AM |
22 | #include "gpmc-nand.h" |
23 | ||
24 | /* minimum size for IO mapping */ | |
25 | #define NAND_IO_SIZE 4 | |
dbc04161 | 26 | |
2ee30f05 AM |
27 | static struct resource gpmc_nand_resource[] = { |
28 | { | |
29 | .flags = IORESOURCE_MEM, | |
30 | }, | |
31 | { | |
32 | .flags = IORESOURCE_IRQ, | |
33 | }, | |
34 | { | |
35 | .flags = IORESOURCE_IRQ, | |
36 | }, | |
2f70a1e9 VS |
37 | }; |
38 | ||
39 | static struct platform_device gpmc_nand_device = { | |
40 | .name = "omap2-nand", | |
41 | .id = 0, | |
2ee30f05 AM |
42 | .num_resources = ARRAY_SIZE(gpmc_nand_resource), |
43 | .resource = gpmc_nand_resource, | |
2f70a1e9 VS |
44 | }; |
45 | ||
bc3668ea AM |
46 | static int omap2_nand_gpmc_retime( |
47 | struct omap_nand_platform_data *gpmc_nand_data, | |
48 | struct gpmc_timings *gpmc_t) | |
2f70a1e9 VS |
49 | { |
50 | struct gpmc_timings t; | |
51 | int err; | |
52 | ||
53 | memset(&t, 0, sizeof(t)); | |
bc3668ea | 54 | t.sync_clk = gpmc_t->sync_clk; |
a1bfdc60 AM |
55 | t.cs_on = gpmc_t->cs_on; |
56 | t.adv_on = gpmc_t->adv_on; | |
2f70a1e9 VS |
57 | |
58 | /* Read */ | |
a1bfdc60 | 59 | t.adv_rd_off = gpmc_t->adv_rd_off; |
2f70a1e9 | 60 | t.oe_on = t.adv_on; |
a1bfdc60 AM |
61 | t.access = gpmc_t->access; |
62 | t.oe_off = gpmc_t->oe_off; | |
63 | t.cs_rd_off = gpmc_t->cs_rd_off; | |
64 | t.rd_cycle = gpmc_t->rd_cycle; | |
2f70a1e9 VS |
65 | |
66 | /* Write */ | |
a1bfdc60 | 67 | t.adv_wr_off = gpmc_t->adv_wr_off; |
2f70a1e9 VS |
68 | t.we_on = t.oe_on; |
69 | if (cpu_is_omap34xx()) { | |
a1bfdc60 AM |
70 | t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; |
71 | t.wr_access = gpmc_t->wr_access; | |
2f70a1e9 | 72 | } |
a1bfdc60 AM |
73 | t.we_off = gpmc_t->we_off; |
74 | t.cs_wr_off = gpmc_t->cs_wr_off; | |
75 | t.wr_cycle = gpmc_t->wr_cycle; | |
2f70a1e9 VS |
76 | |
77 | /* Configure GPMC */ | |
d5ce2b65 SG |
78 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) |
79 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); | |
80 | else | |
81 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); | |
2c01946c SG |
82 | gpmc_cs_configure(gpmc_nand_data->cs, |
83 | GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); | |
2ee30f05 | 84 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); |
2f70a1e9 VS |
85 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); |
86 | if (err) | |
87 | return err; | |
88 | ||
89 | return 0; | |
90 | } | |
91 | ||
504f3c6d | 92 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) |
3852ccd6 AM |
93 | { |
94 | /* support only OMAP3 class */ | |
f50a0380 | 95 | if (!cpu_is_omap34xx() && !soc_is_am33xx()) { |
3852ccd6 AM |
96 | pr_err("BCH ecc is not supported on this CPU\n"); |
97 | return 0; | |
98 | } | |
99 | ||
100 | /* | |
f50a0380 DM |
101 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 |
102 | * and AM33xx derivates. Other chips may be added if confirmed to work. | |
3852ccd6 AM |
103 | */ |
104 | if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && | |
f50a0380 DM |
105 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && |
106 | (!soc_is_am33xx())) { | |
3852ccd6 AM |
107 | pr_err("BCH 4-bit mode is not supported on this CPU\n"); |
108 | return 0; | |
109 | } | |
110 | ||
111 | return 1; | |
112 | } | |
113 | ||
504f3c6d DM |
114 | int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, |
115 | struct gpmc_timings *gpmc_t) | |
2f70a1e9 | 116 | { |
2f70a1e9 VS |
117 | int err = 0; |
118 | struct device *dev = &gpmc_nand_device.dev; | |
119 | ||
2f70a1e9 VS |
120 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
121 | ||
122 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | |
2ee30f05 | 123 | (unsigned long *)&gpmc_nand_resource[0].start); |
2f70a1e9 VS |
124 | if (err < 0) { |
125 | dev_err(dev, "Cannot request GPMC CS\n"); | |
126 | return err; | |
127 | } | |
128 | ||
2ee30f05 AM |
129 | gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + |
130 | NAND_IO_SIZE - 1; | |
9222e3a7 | 131 | |
2ee30f05 AM |
132 | gpmc_nand_resource[1].start = |
133 | gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | |
134 | gpmc_nand_resource[2].start = | |
135 | gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | |
bc3668ea AM |
136 | |
137 | if (gpmc_t) { | |
138 | err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); | |
139 | if (err < 0) { | |
140 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); | |
141 | return err; | |
142 | } | |
2f70a1e9 VS |
143 | } |
144 | ||
145 | /* Enable RD PIN Monitoring Reg */ | |
146 | if (gpmc_nand_data->dev_ready) { | |
2c01946c | 147 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); |
2f70a1e9 VS |
148 | } |
149 | ||
d126d015 AM |
150 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
151 | ||
3852ccd6 AM |
152 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) |
153 | return -EINVAL; | |
154 | ||
2f70a1e9 VS |
155 | err = platform_device_register(&gpmc_nand_device); |
156 | if (err < 0) { | |
157 | dev_err(dev, "Unable to register NAND device\n"); | |
158 | goto out_free_cs; | |
159 | } | |
160 | ||
161 | return 0; | |
162 | ||
163 | out_free_cs: | |
164 | gpmc_cs_free(gpmc_nand_data->cs); | |
165 | ||
166 | return err; | |
167 | } |