Commit | Line | Data |
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2f70a1e9 VS |
1 | /* |
2 | * gpmc-nand.c | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Vimal Singh <vimalsingh@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
d5ce2b65 | 15 | #include <linux/mtd/nand.h> |
2203747c | 16 | #include <linux/platform_data/mtd-nand-omap2.h> |
2f70a1e9 VS |
17 | |
18 | #include <asm/mach/flash.h> | |
19 | ||
3ef5d007 | 20 | #include "gpmc.h" |
dbc04161 | 21 | #include "soc.h" |
bc3668ea AM |
22 | #include "gpmc-nand.h" |
23 | ||
24 | /* minimum size for IO mapping */ | |
25 | #define NAND_IO_SIZE 4 | |
dbc04161 | 26 | |
504f3c6d | 27 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) |
3852ccd6 | 28 | { |
0611c419 | 29 | /* platforms which support all ECC schemes */ |
2e091d13 | 30 | if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() || |
0611c419 PG |
31 | soc_is_omap54xx() || soc_is_dra7xx()) |
32 | return 1; | |
33 | ||
33753cd2 CF |
34 | if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW || |
35 | ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) { | |
36 | if (cpu_is_omap24xx()) | |
37 | return 0; | |
38 | else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0)) | |
39 | return 0; | |
40 | else | |
41 | return 1; | |
42 | } | |
43 | ||
0611c419 PG |
44 | /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes |
45 | * which require H/W based ECC error detection */ | |
46 | if ((cpu_is_omap34xx() || cpu_is_omap3630()) && | |
47 | ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) || | |
48 | (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) | |
3852ccd6 | 49 | return 0; |
3852ccd6 | 50 | |
0611c419 PG |
51 | /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ |
52 | if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) | |
53 | return 1; | |
54 | else | |
55 | return 0; | |
3852ccd6 AM |
56 | } |
57 | ||
d0020cc6 EG |
58 | /* This function will go away once the device-tree convertion is complete */ |
59 | static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data, | |
60 | struct gpmc_settings *s) | |
61 | { | |
62 | /* Enable RD PIN Monitoring Reg */ | |
63 | if (gpmc_nand_data->dev_ready) { | |
64 | s->wait_on_read = true; | |
65 | s->wait_on_write = true; | |
66 | } | |
bbc28cdb EG |
67 | |
68 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) | |
69 | s->device_width = GPMC_DEVWIDTH_16BIT; | |
70 | else | |
71 | s->device_width = GPMC_DEVWIDTH_8BIT; | |
d0020cc6 EG |
72 | } |
73 | ||
504f3c6d DM |
74 | int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, |
75 | struct gpmc_timings *gpmc_t) | |
2f70a1e9 | 76 | { |
2f70a1e9 | 77 | int err = 0; |
24db7ecc | 78 | struct gpmc_settings s; |
97a288ba RL |
79 | struct platform_device *pdev; |
80 | struct resource gpmc_nand_res[] = { | |
81 | { .flags = IORESOURCE_MEM, }, | |
82 | { .flags = IORESOURCE_IRQ, }, | |
83 | { .flags = IORESOURCE_IRQ, }, | |
84 | }; | |
24db7ecc | 85 | |
97a288ba | 86 | BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM); |
2f70a1e9 VS |
87 | |
88 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | |
97a288ba | 89 | (unsigned long *)&gpmc_nand_res[0].start); |
2f70a1e9 | 90 | if (err < 0) { |
97a288ba RL |
91 | pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n", |
92 | gpmc_nand_data->cs, err); | |
2f70a1e9 VS |
93 | return err; |
94 | } | |
97a288ba RL |
95 | gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1; |
96 | gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | |
97 | gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | |
bc3668ea AM |
98 | |
99 | if (gpmc_t) { | |
4d584361 | 100 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); |
bc3668ea | 101 | if (err < 0) { |
97a288ba | 102 | pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err); |
bc3668ea AM |
103 | return err; |
104 | } | |
e2e699b1 | 105 | } |
2f70a1e9 | 106 | |
97a288ba | 107 | memset(&s, 0, sizeof(struct gpmc_settings)); |
d0020cc6 | 108 | if (gpmc_nand_data->of_node) |
e2e699b1 | 109 | gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); |
d0020cc6 EG |
110 | else |
111 | gpmc_set_legacy(gpmc_nand_data, &s); | |
24db7ecc | 112 | |
e2e699b1 | 113 | s.device_nand = true; |
e2e699b1 EG |
114 | err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); |
115 | if (err < 0) | |
116 | goto out_free_cs; | |
24db7ecc | 117 | |
e2e699b1 EG |
118 | err = gpmc_configure(GPMC_CONFIG_WP, 0); |
119 | if (err < 0) | |
120 | goto out_free_cs; | |
2f70a1e9 | 121 | |
d126d015 AM |
122 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
123 | ||
0611c419 | 124 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { |
97a288ba RL |
125 | pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n"); |
126 | err = -EINVAL; | |
127 | goto out_free_cs; | |
0611c419 | 128 | } |
3852ccd6 | 129 | |
97a288ba RL |
130 | |
131 | pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs); | |
132 | if (pdev) { | |
133 | err = platform_device_add_resources(pdev, gpmc_nand_res, | |
134 | ARRAY_SIZE(gpmc_nand_res)); | |
135 | if (!err) | |
136 | pdev->dev.platform_data = gpmc_nand_data; | |
137 | } else { | |
138 | err = -ENOMEM; | |
139 | } | |
140 | if (err) | |
141 | goto out_free_pdev; | |
142 | ||
143 | err = platform_device_add(pdev); | |
144 | if (err) { | |
145 | dev_err(&pdev->dev, "Unable to register NAND device\n"); | |
146 | goto out_free_pdev; | |
2f70a1e9 VS |
147 | } |
148 | ||
149 | return 0; | |
150 | ||
97a288ba RL |
151 | out_free_pdev: |
152 | platform_device_put(pdev); | |
2f70a1e9 VS |
153 | out_free_cs: |
154 | gpmc_cs_free(gpmc_nand_data->cs); | |
155 | ||
156 | return err; | |
157 | } |