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2f70a1e9 VS |
1 | /* |
2 | * gpmc-nand.c | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Vimal Singh <vimalsingh@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
d5ce2b65 | 15 | #include <linux/mtd/nand.h> |
2203747c | 16 | #include <linux/platform_data/mtd-nand-omap2.h> |
2f70a1e9 VS |
17 | |
18 | #include <asm/mach/flash.h> | |
19 | ||
2f70a1e9 VS |
20 | #include <plat/gpmc.h> |
21 | ||
dbc04161 | 22 | #include "soc.h" |
bc3668ea AM |
23 | #include "gpmc-nand.h" |
24 | ||
25 | /* minimum size for IO mapping */ | |
26 | #define NAND_IO_SIZE 4 | |
dbc04161 | 27 | |
2ee30f05 AM |
28 | static struct resource gpmc_nand_resource[] = { |
29 | { | |
30 | .flags = IORESOURCE_MEM, | |
31 | }, | |
32 | { | |
33 | .flags = IORESOURCE_IRQ, | |
34 | }, | |
35 | { | |
36 | .flags = IORESOURCE_IRQ, | |
37 | }, | |
2f70a1e9 VS |
38 | }; |
39 | ||
40 | static struct platform_device gpmc_nand_device = { | |
41 | .name = "omap2-nand", | |
42 | .id = 0, | |
2ee30f05 AM |
43 | .num_resources = ARRAY_SIZE(gpmc_nand_resource), |
44 | .resource = gpmc_nand_resource, | |
2f70a1e9 VS |
45 | }; |
46 | ||
bc3668ea AM |
47 | static int omap2_nand_gpmc_retime( |
48 | struct omap_nand_platform_data *gpmc_nand_data, | |
49 | struct gpmc_timings *gpmc_t) | |
2f70a1e9 VS |
50 | { |
51 | struct gpmc_timings t; | |
52 | int err; | |
53 | ||
54 | memset(&t, 0, sizeof(t)); | |
bc3668ea AM |
55 | t.sync_clk = gpmc_t->sync_clk; |
56 | t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on); | |
57 | t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on); | |
2f70a1e9 VS |
58 | |
59 | /* Read */ | |
bc3668ea | 60 | t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off); |
2f70a1e9 | 61 | t.oe_on = t.adv_on; |
bc3668ea AM |
62 | t.access = gpmc_round_ns_to_ticks(gpmc_t->access); |
63 | t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off); | |
64 | t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off); | |
65 | t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle); | |
2f70a1e9 VS |
66 | |
67 | /* Write */ | |
bc3668ea | 68 | t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off); |
2f70a1e9 VS |
69 | t.we_on = t.oe_on; |
70 | if (cpu_is_omap34xx()) { | |
bc3668ea AM |
71 | t.wr_data_mux_bus = gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus); |
72 | t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access); | |
2f70a1e9 | 73 | } |
bc3668ea AM |
74 | t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off); |
75 | t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off); | |
76 | t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle); | |
2f70a1e9 VS |
77 | |
78 | /* Configure GPMC */ | |
d5ce2b65 SG |
79 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) |
80 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); | |
81 | else | |
82 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); | |
2c01946c SG |
83 | gpmc_cs_configure(gpmc_nand_data->cs, |
84 | GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); | |
2ee30f05 | 85 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); |
2f70a1e9 VS |
86 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); |
87 | if (err) | |
88 | return err; | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
3852ccd6 AM |
93 | static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) |
94 | { | |
95 | /* support only OMAP3 class */ | |
96 | if (!cpu_is_omap34xx()) { | |
97 | pr_err("BCH ecc is not supported on this CPU\n"); | |
98 | return 0; | |
99 | } | |
100 | ||
101 | /* | |
102 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. | |
103 | * Other chips may be added if confirmed to work. | |
104 | */ | |
105 | if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && | |
106 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { | |
107 | pr_err("BCH 4-bit mode is not supported on this CPU\n"); | |
108 | return 0; | |
109 | } | |
110 | ||
111 | return 1; | |
112 | } | |
113 | ||
bc3668ea AM |
114 | int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, |
115 | struct gpmc_timings *gpmc_t) | |
2f70a1e9 | 116 | { |
2f70a1e9 VS |
117 | int err = 0; |
118 | struct device *dev = &gpmc_nand_device.dev; | |
119 | ||
2f70a1e9 VS |
120 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
121 | ||
122 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | |
2ee30f05 | 123 | (unsigned long *)&gpmc_nand_resource[0].start); |
2f70a1e9 VS |
124 | if (err < 0) { |
125 | dev_err(dev, "Cannot request GPMC CS\n"); | |
126 | return err; | |
127 | } | |
128 | ||
2ee30f05 AM |
129 | gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + |
130 | NAND_IO_SIZE - 1; | |
9222e3a7 | 131 | |
2ee30f05 AM |
132 | gpmc_nand_resource[1].start = |
133 | gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | |
134 | gpmc_nand_resource[2].start = | |
135 | gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | |
bc3668ea AM |
136 | |
137 | if (gpmc_t) { | |
138 | err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); | |
139 | if (err < 0) { | |
140 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); | |
141 | return err; | |
142 | } | |
2f70a1e9 VS |
143 | } |
144 | ||
145 | /* Enable RD PIN Monitoring Reg */ | |
146 | if (gpmc_nand_data->dev_ready) { | |
2c01946c | 147 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); |
2f70a1e9 VS |
148 | } |
149 | ||
d126d015 AM |
150 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
151 | ||
3852ccd6 AM |
152 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) |
153 | return -EINVAL; | |
154 | ||
2f70a1e9 VS |
155 | err = platform_device_register(&gpmc_nand_device); |
156 | if (err < 0) { | |
157 | dev_err(dev, "Unable to register NAND device\n"); | |
158 | goto out_free_cs; | |
159 | } | |
160 | ||
161 | return 0; | |
162 | ||
163 | out_free_cs: | |
164 | gpmc_cs_free(gpmc_nand_data->cs); | |
165 | ||
166 | return err; | |
167 | } |