Commit | Line | Data |
---|---|---|
2f70a1e9 VS |
1 | /* |
2 | * gpmc-nand.c | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Vimal Singh <vimalsingh@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
d5ce2b65 | 15 | #include <linux/mtd/nand.h> |
2f70a1e9 VS |
16 | |
17 | #include <asm/mach/flash.h> | |
18 | ||
2c799cef | 19 | #include <plat/cpu.h> |
2f70a1e9 | 20 | #include <plat/nand.h> |
2f70a1e9 VS |
21 | #include <plat/gpmc.h> |
22 | ||
2ee30f05 AM |
23 | static struct resource gpmc_nand_resource[] = { |
24 | { | |
25 | .flags = IORESOURCE_MEM, | |
26 | }, | |
27 | { | |
28 | .flags = IORESOURCE_IRQ, | |
29 | }, | |
30 | { | |
31 | .flags = IORESOURCE_IRQ, | |
32 | }, | |
2f70a1e9 VS |
33 | }; |
34 | ||
35 | static struct platform_device gpmc_nand_device = { | |
36 | .name = "omap2-nand", | |
37 | .id = 0, | |
2ee30f05 AM |
38 | .num_resources = ARRAY_SIZE(gpmc_nand_resource), |
39 | .resource = gpmc_nand_resource, | |
2f70a1e9 VS |
40 | }; |
41 | ||
7a559c78 | 42 | static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) |
2f70a1e9 VS |
43 | { |
44 | struct gpmc_timings t; | |
45 | int err; | |
46 | ||
11e1ef2d | 47 | if (!gpmc_nand_data->gpmc_t) |
48 | return 0; | |
49 | ||
2f70a1e9 | 50 | memset(&t, 0, sizeof(t)); |
a3551f5b | 51 | t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk; |
2f70a1e9 VS |
52 | t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); |
53 | t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); | |
54 | ||
55 | /* Read */ | |
56 | t.adv_rd_off = gpmc_round_ns_to_ticks( | |
57 | gpmc_nand_data->gpmc_t->adv_rd_off); | |
58 | t.oe_on = t.adv_on; | |
59 | t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access); | |
60 | t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off); | |
61 | t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off); | |
62 | t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle); | |
63 | ||
64 | /* Write */ | |
65 | t.adv_wr_off = gpmc_round_ns_to_ticks( | |
66 | gpmc_nand_data->gpmc_t->adv_wr_off); | |
67 | t.we_on = t.oe_on; | |
68 | if (cpu_is_omap34xx()) { | |
69 | t.wr_data_mux_bus = gpmc_round_ns_to_ticks( | |
70 | gpmc_nand_data->gpmc_t->wr_data_mux_bus); | |
71 | t.wr_access = gpmc_round_ns_to_ticks( | |
72 | gpmc_nand_data->gpmc_t->wr_access); | |
73 | } | |
74 | t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off); | |
75 | t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off); | |
76 | t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); | |
77 | ||
78 | /* Configure GPMC */ | |
d5ce2b65 SG |
79 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) |
80 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); | |
81 | else | |
82 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); | |
2c01946c SG |
83 | gpmc_cs_configure(gpmc_nand_data->cs, |
84 | GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); | |
2ee30f05 | 85 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); |
2f70a1e9 VS |
86 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); |
87 | if (err) | |
88 | return err; | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
7a559c78 | 93 | int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) |
2f70a1e9 | 94 | { |
2f70a1e9 VS |
95 | int err = 0; |
96 | struct device *dev = &gpmc_nand_device.dev; | |
97 | ||
2f70a1e9 VS |
98 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
99 | ||
100 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | |
2ee30f05 | 101 | (unsigned long *)&gpmc_nand_resource[0].start); |
2f70a1e9 VS |
102 | if (err < 0) { |
103 | dev_err(dev, "Cannot request GPMC CS\n"); | |
104 | return err; | |
105 | } | |
106 | ||
2ee30f05 AM |
107 | gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + |
108 | NAND_IO_SIZE - 1; | |
9222e3a7 | 109 | |
2ee30f05 AM |
110 | gpmc_nand_resource[1].start = |
111 | gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | |
112 | gpmc_nand_resource[2].start = | |
113 | gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | |
2c01946c | 114 | /* Set timings in GPMC */ |
7a559c78 | 115 | err = omap2_nand_gpmc_retime(gpmc_nand_data); |
2f70a1e9 | 116 | if (err < 0) { |
2c01946c | 117 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); |
2f70a1e9 VS |
118 | return err; |
119 | } | |
120 | ||
121 | /* Enable RD PIN Monitoring Reg */ | |
122 | if (gpmc_nand_data->dev_ready) { | |
2c01946c | 123 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); |
2f70a1e9 VS |
124 | } |
125 | ||
d126d015 AM |
126 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
127 | ||
2f70a1e9 VS |
128 | err = platform_device_register(&gpmc_nand_device); |
129 | if (err < 0) { | |
130 | dev_err(dev, "Unable to register NAND device\n"); | |
131 | goto out_free_cs; | |
132 | } | |
133 | ||
134 | return 0; | |
135 | ||
136 | out_free_cs: | |
137 | gpmc_cs_free(gpmc_nand_data->cs); | |
138 | ||
139 | return err; | |
140 | } |