Commit | Line | Data |
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2f70a1e9 VS |
1 | /* |
2 | * gpmc-nand.c | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Vimal Singh <vimalsingh@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
d5ce2b65 | 15 | #include <linux/mtd/nand.h> |
2203747c | 16 | #include <linux/platform_data/mtd-nand-omap2.h> |
2f70a1e9 VS |
17 | |
18 | #include <asm/mach/flash.h> | |
19 | ||
3ef5d007 | 20 | #include "gpmc.h" |
dbc04161 | 21 | #include "soc.h" |
bc3668ea AM |
22 | #include "gpmc-nand.h" |
23 | ||
24 | /* minimum size for IO mapping */ | |
25 | #define NAND_IO_SIZE 4 | |
dbc04161 | 26 | |
2ee30f05 AM |
27 | static struct resource gpmc_nand_resource[] = { |
28 | { | |
29 | .flags = IORESOURCE_MEM, | |
30 | }, | |
31 | { | |
32 | .flags = IORESOURCE_IRQ, | |
33 | }, | |
34 | { | |
35 | .flags = IORESOURCE_IRQ, | |
36 | }, | |
2f70a1e9 VS |
37 | }; |
38 | ||
39 | static struct platform_device gpmc_nand_device = { | |
40 | .name = "omap2-nand", | |
41 | .id = 0, | |
2ee30f05 AM |
42 | .num_resources = ARRAY_SIZE(gpmc_nand_resource), |
43 | .resource = gpmc_nand_resource, | |
2f70a1e9 VS |
44 | }; |
45 | ||
504f3c6d | 46 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) |
3852ccd6 AM |
47 | { |
48 | /* support only OMAP3 class */ | |
f50a0380 | 49 | if (!cpu_is_omap34xx() && !soc_is_am33xx()) { |
3852ccd6 AM |
50 | pr_err("BCH ecc is not supported on this CPU\n"); |
51 | return 0; | |
52 | } | |
53 | ||
54 | /* | |
f50a0380 DM |
55 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 |
56 | * and AM33xx derivates. Other chips may be added if confirmed to work. | |
3852ccd6 AM |
57 | */ |
58 | if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && | |
f50a0380 DM |
59 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && |
60 | (!soc_is_am33xx())) { | |
3852ccd6 AM |
61 | pr_err("BCH 4-bit mode is not supported on this CPU\n"); |
62 | return 0; | |
63 | } | |
64 | ||
65 | return 1; | |
66 | } | |
67 | ||
504f3c6d DM |
68 | int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, |
69 | struct gpmc_timings *gpmc_t) | |
2f70a1e9 | 70 | { |
2f70a1e9 | 71 | int err = 0; |
24db7ecc | 72 | struct gpmc_settings s; |
2f70a1e9 VS |
73 | struct device *dev = &gpmc_nand_device.dev; |
74 | ||
24db7ecc JH |
75 | memset(&s, 0, sizeof(struct gpmc_settings)); |
76 | ||
2f70a1e9 VS |
77 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
78 | ||
79 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | |
2ee30f05 | 80 | (unsigned long *)&gpmc_nand_resource[0].start); |
2f70a1e9 | 81 | if (err < 0) { |
097c9dae EG |
82 | dev_err(dev, "Cannot request GPMC CS %d, error %d\n", |
83 | gpmc_nand_data->cs, err); | |
2f70a1e9 VS |
84 | return err; |
85 | } | |
86 | ||
2ee30f05 AM |
87 | gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + |
88 | NAND_IO_SIZE - 1; | |
9222e3a7 | 89 | |
2ee30f05 AM |
90 | gpmc_nand_resource[1].start = |
91 | gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | |
92 | gpmc_nand_resource[2].start = | |
93 | gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | |
bc3668ea AM |
94 | |
95 | if (gpmc_t) { | |
4d584361 | 96 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); |
bc3668ea AM |
97 | if (err < 0) { |
98 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); | |
99 | return err; | |
100 | } | |
e2e699b1 | 101 | } |
2f70a1e9 | 102 | |
e2e699b1 EG |
103 | if (gpmc_nand_data->of_node) { |
104 | gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); | |
105 | } else { | |
106 | /* Enable RD PIN Monitoring Reg */ | |
107 | if (gpmc_nand_data->dev_ready) { | |
108 | s.wait_on_read = true; | |
109 | s.wait_on_write = true; | |
24db7ecc | 110 | } |
e2e699b1 | 111 | } |
24db7ecc | 112 | |
e2e699b1 | 113 | s.device_nand = true; |
f40739fa | 114 | |
e2e699b1 EG |
115 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) |
116 | s.device_width = GPMC_DEVWIDTH_16BIT; | |
117 | else | |
118 | s.device_width = GPMC_DEVWIDTH_8BIT; | |
24db7ecc | 119 | |
e2e699b1 EG |
120 | err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); |
121 | if (err < 0) | |
122 | goto out_free_cs; | |
24db7ecc | 123 | |
e2e699b1 EG |
124 | err = gpmc_configure(GPMC_CONFIG_WP, 0); |
125 | if (err < 0) | |
126 | goto out_free_cs; | |
2f70a1e9 | 127 | |
d126d015 AM |
128 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
129 | ||
3852ccd6 AM |
130 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) |
131 | return -EINVAL; | |
132 | ||
2f70a1e9 VS |
133 | err = platform_device_register(&gpmc_nand_device); |
134 | if (err < 0) { | |
135 | dev_err(dev, "Unable to register NAND device\n"); | |
136 | goto out_free_cs; | |
137 | } | |
138 | ||
139 | return 0; | |
140 | ||
141 | out_free_cs: | |
142 | gpmc_cs_free(gpmc_nand_data->cs); | |
143 | ||
144 | return err; | |
145 | } |