Commit | Line | Data |
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aa62e90f JY |
1 | /* |
2 | * linux/arch/arm/mach-omap2/gpmc-onenand.c | |
3 | * | |
4 | * Copyright (C) 2006 - 2009 Nokia Corporation | |
5 | * Contacts: Juha Yrjola | |
6 | * Tony Lindgren | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
d44b28c4 | 13 | #include <linux/string.h> |
aa62e90f JY |
14 | #include <linux/kernel.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/mtd/onenand_regs.h> | |
17 | #include <linux/io.h> | |
2203747c | 18 | #include <linux/platform_data/mtd-onenand-omap2.h> |
46376884 | 19 | #include <linux/err.h> |
aa62e90f JY |
20 | |
21 | #include <asm/mach/flash.h> | |
22 | ||
3ef5d007 | 23 | #include "gpmc.h" |
dbc04161 | 24 | #include "soc.h" |
b6ab13e7 | 25 | #include "gpmc-onenand.h" |
dbc04161 | 26 | |
681988ba AM |
27 | #define ONENAND_IO_SIZE SZ_128K |
28 | ||
46376884 AM |
29 | #define ONENAND_FLAG_SYNCREAD (1 << 0) |
30 | #define ONENAND_FLAG_SYNCWRITE (1 << 1) | |
31 | #define ONENAND_FLAG_HF (1 << 2) | |
32 | #define ONENAND_FLAG_VHF (1 << 3) | |
33 | ||
34 | static unsigned onenand_flags; | |
35 | static unsigned latency; | |
46376884 | 36 | |
aa62e90f JY |
37 | static struct omap_onenand_platform_data *gpmc_onenand_data; |
38 | ||
681988ba AM |
39 | static struct resource gpmc_onenand_resource = { |
40 | .flags = IORESOURCE_MEM, | |
41 | }; | |
42 | ||
aa62e90f JY |
43 | static struct platform_device gpmc_onenand_device = { |
44 | .name = "omap2-onenand", | |
45 | .id = -1, | |
681988ba AM |
46 | .num_resources = 1, |
47 | .resource = &gpmc_onenand_resource, | |
aa62e90f JY |
48 | }; |
49 | ||
46376884 | 50 | static struct gpmc_timings omap2_onenand_calc_async_timings(void) |
aa62e90f | 51 | { |
4f4426f9 | 52 | struct gpmc_device_timings dev_t; |
aa62e90f JY |
53 | struct gpmc_timings t; |
54 | ||
55 | const int t_cer = 15; | |
56 | const int t_avdp = 12; | |
57 | const int t_aavdh = 7; | |
58 | const int t_ce = 76; | |
59 | const int t_aa = 76; | |
60 | const int t_oe = 20; | |
61 | const int t_cez = 20; /* max of t_cez, t_oez */ | |
aa62e90f JY |
62 | const int t_wpl = 40; |
63 | const int t_wph = 30; | |
64 | ||
4f4426f9 AM |
65 | memset(&dev_t, 0, sizeof(dev_t)); |
66 | ||
67 | dev_t.mux = true; | |
68 | dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; | |
69 | dev_t.t_avdp_w = dev_t.t_avdp_r; | |
70 | dev_t.t_aavdh = t_aavdh * 1000; | |
71 | dev_t.t_aa = t_aa * 1000; | |
72 | dev_t.t_ce = t_ce * 1000; | |
73 | dev_t.t_oe = t_oe * 1000; | |
74 | dev_t.t_cez_r = t_cez * 1000; | |
75 | dev_t.t_cez_w = dev_t.t_cez_r; | |
76 | dev_t.t_wpl = t_wpl * 1000; | |
77 | dev_t.t_wph = t_wph * 1000; | |
78 | ||
79 | gpmc_calc_timings(&t, &dev_t); | |
aa62e90f | 80 | |
46376884 AM |
81 | return t; |
82 | } | |
83 | ||
84 | static int gpmc_set_async_mode(int cs, struct gpmc_timings *t) | |
85 | { | |
aa62e90f JY |
86 | /* Configure GPMC for asynchronous read */ |
87 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, | |
88 | GPMC_CONFIG1_DEVICESIZE_16 | | |
89 | GPMC_CONFIG1_MUXADDDATA); | |
90 | ||
46376884 AM |
91 | return gpmc_cs_set_timings(cs, t); |
92 | } | |
93 | ||
94 | static void omap2_onenand_set_async_mode(void __iomem *onenand_base) | |
95 | { | |
96 | u32 reg; | |
6d453e84 AH |
97 | |
98 | /* Ensure sync read and sync write are disabled */ | |
99 | reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); | |
100 | reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; | |
101 | writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); | |
aa62e90f JY |
102 | } |
103 | ||
46376884 | 104 | static void set_onenand_cfg(void __iomem *onenand_base) |
aa62e90f JY |
105 | { |
106 | u32 reg; | |
107 | ||
108 | reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); | |
109 | reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9)); | |
110 | reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | | |
111 | ONENAND_SYS_CFG1_BL_16; | |
46376884 | 112 | if (onenand_flags & ONENAND_FLAG_SYNCREAD) |
aa62e90f JY |
113 | reg |= ONENAND_SYS_CFG1_SYNC_READ; |
114 | else | |
115 | reg &= ~ONENAND_SYS_CFG1_SYNC_READ; | |
46376884 | 116 | if (onenand_flags & ONENAND_FLAG_SYNCWRITE) |
aa62e90f JY |
117 | reg |= ONENAND_SYS_CFG1_SYNC_WRITE; |
118 | else | |
119 | reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE; | |
46376884 | 120 | if (onenand_flags & ONENAND_FLAG_HF) |
aa62e90f JY |
121 | reg |= ONENAND_SYS_CFG1_HF; |
122 | else | |
123 | reg &= ~ONENAND_SYS_CFG1_HF; | |
46376884 | 124 | if (onenand_flags & ONENAND_FLAG_VHF) |
1435ca0f AH |
125 | reg |= ONENAND_SYS_CFG1_VHF; |
126 | else | |
127 | reg &= ~ONENAND_SYS_CFG1_VHF; | |
aa62e90f JY |
128 | writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); |
129 | } | |
130 | ||
5714b7ed | 131 | static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, |
757ef791 | 132 | void __iomem *onenand_base) |
5714b7ed AH |
133 | { |
134 | u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); | |
757ef791 | 135 | int freq; |
5714b7ed AH |
136 | |
137 | switch ((ver >> 4) & 0xf) { | |
138 | case 0: | |
139 | freq = 40; | |
140 | break; | |
141 | case 1: | |
142 | freq = 54; | |
143 | break; | |
144 | case 2: | |
145 | freq = 66; | |
146 | break; | |
147 | case 3: | |
148 | freq = 83; | |
149 | break; | |
150 | case 4: | |
151 | freq = 104; | |
152 | break; | |
153 | default: | |
154 | freq = 54; | |
155 | break; | |
156 | } | |
157 | ||
158 | return freq; | |
159 | } | |
160 | ||
46376884 AM |
161 | static struct gpmc_timings |
162 | omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, | |
757ef791 | 163 | int freq) |
aa62e90f | 164 | { |
4f4426f9 | 165 | struct gpmc_device_timings dev_t; |
aa62e90f JY |
166 | struct gpmc_timings t; |
167 | const int t_cer = 15; | |
168 | const int t_avdp = 12; | |
169 | const int t_cez = 20; /* max of t_cez, t_oez */ | |
aa62e90f JY |
170 | const int t_wpl = 40; |
171 | const int t_wph = 30; | |
172 | int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; | |
4f4426f9 | 173 | int div, gpmc_clk_ns; |
aa62e90f | 174 | |
46376884 AM |
175 | if (cfg->flags & ONENAND_SYNC_READ) |
176 | onenand_flags = ONENAND_FLAG_SYNCREAD; | |
177 | else if (cfg->flags & ONENAND_SYNC_READWRITE) | |
178 | onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; | |
aa62e90f JY |
179 | |
180 | switch (freq) { | |
4931445b AH |
181 | case 104: |
182 | min_gpmc_clk_period = 9600; /* 104 MHz */ | |
183 | t_ces = 3; | |
184 | t_avds = 4; | |
185 | t_avdh = 2; | |
186 | t_ach = 3; | |
187 | t_aavdh = 6; | |
1435ca0f | 188 | t_rdyo = 6; |
4931445b | 189 | break; |
aa62e90f | 190 | case 83: |
a3551f5b | 191 | min_gpmc_clk_period = 12000; /* 83 MHz */ |
aa62e90f JY |
192 | t_ces = 5; |
193 | t_avds = 4; | |
194 | t_avdh = 2; | |
195 | t_ach = 6; | |
196 | t_aavdh = 6; | |
197 | t_rdyo = 9; | |
198 | break; | |
199 | case 66: | |
a3551f5b | 200 | min_gpmc_clk_period = 15000; /* 66 MHz */ |
aa62e90f JY |
201 | t_ces = 6; |
202 | t_avds = 5; | |
203 | t_avdh = 2; | |
204 | t_ach = 6; | |
205 | t_aavdh = 6; | |
206 | t_rdyo = 11; | |
207 | break; | |
208 | default: | |
a3551f5b | 209 | min_gpmc_clk_period = 18500; /* 54 MHz */ |
aa62e90f JY |
210 | t_ces = 7; |
211 | t_avds = 7; | |
212 | t_avdh = 7; | |
213 | t_ach = 9; | |
214 | t_aavdh = 7; | |
215 | t_rdyo = 15; | |
46376884 | 216 | onenand_flags &= ~ONENAND_FLAG_SYNCWRITE; |
aa62e90f JY |
217 | break; |
218 | } | |
219 | ||
1b47ca1a | 220 | div = gpmc_calc_divider(min_gpmc_clk_period); |
aa62e90f JY |
221 | gpmc_clk_ns = gpmc_ticks_to_ns(div); |
222 | if (gpmc_clk_ns < 15) /* >66Mhz */ | |
46376884 AM |
223 | onenand_flags |= ONENAND_FLAG_HF; |
224 | else | |
225 | onenand_flags &= ~ONENAND_FLAG_HF; | |
1435ca0f | 226 | if (gpmc_clk_ns < 12) /* >83Mhz */ |
46376884 AM |
227 | onenand_flags |= ONENAND_FLAG_VHF; |
228 | else | |
229 | onenand_flags &= ~ONENAND_FLAG_VHF; | |
230 | if (onenand_flags & ONENAND_FLAG_VHF) | |
1435ca0f | 231 | latency = 8; |
46376884 | 232 | else if (onenand_flags & ONENAND_FLAG_HF) |
aa62e90f JY |
233 | latency = 6; |
234 | else if (gpmc_clk_ns >= 25) /* 40 MHz*/ | |
235 | latency = 3; | |
236 | else | |
237 | latency = 4; | |
238 | ||
46376884 | 239 | /* Set synchronous read timings */ |
4f4426f9 | 240 | memset(&dev_t, 0, sizeof(dev_t)); |
aa62e90f | 241 | |
4f4426f9 AM |
242 | dev_t.mux = true; |
243 | dev_t.sync_read = true; | |
46376884 | 244 | if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { |
4f4426f9 | 245 | dev_t.sync_write = true; |
aa62e90f | 246 | } else { |
4f4426f9 AM |
247 | dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; |
248 | dev_t.t_wpl = t_wpl * 1000; | |
249 | dev_t.t_wph = t_wph * 1000; | |
250 | dev_t.t_aavdh = t_aavdh * 1000; | |
aa62e90f | 251 | } |
4f4426f9 AM |
252 | dev_t.ce_xdelay = true; |
253 | dev_t.avd_xdelay = true; | |
254 | dev_t.oe_xdelay = true; | |
255 | dev_t.we_xdelay = true; | |
256 | dev_t.clk = min_gpmc_clk_period; | |
257 | dev_t.t_bacc = dev_t.clk; | |
258 | dev_t.t_ces = t_ces * 1000; | |
259 | dev_t.t_avds = t_avds * 1000; | |
260 | dev_t.t_avdh = t_avdh * 1000; | |
261 | dev_t.t_ach = t_ach * 1000; | |
262 | dev_t.cyc_iaa = (latency + 1); | |
263 | dev_t.t_cez_r = t_cez * 1000; | |
264 | dev_t.t_cez_w = dev_t.t_cez_r; | |
265 | dev_t.cyc_aavdh_oe = 1; | |
266 | dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; | |
267 | ||
268 | gpmc_calc_timings(&t, &dev_t); | |
aa62e90f | 269 | |
46376884 AM |
270 | return t; |
271 | } | |
272 | ||
273 | static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t) | |
274 | { | |
275 | unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD; | |
276 | unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE; | |
277 | ||
aa62e90f JY |
278 | /* Configure GPMC for synchronous read */ |
279 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, | |
280 | GPMC_CONFIG1_WRAPBURST_SUPP | | |
281 | GPMC_CONFIG1_READMULTIPLE_SUPP | | |
282 | (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) | | |
283 | (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) | | |
284 | (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) | | |
aa62e90f JY |
285 | GPMC_CONFIG1_PAGE_LEN(2) | |
286 | (cpu_is_omap34xx() ? 0 : | |
287 | (GPMC_CONFIG1_WAIT_READ_MON | | |
288 | GPMC_CONFIG1_WAIT_PIN_SEL(0))) | | |
289 | GPMC_CONFIG1_DEVICESIZE_16 | | |
290 | GPMC_CONFIG1_DEVICETYPE_NOR | | |
291 | GPMC_CONFIG1_MUXADDDATA); | |
292 | ||
46376884 AM |
293 | return gpmc_cs_set_timings(cs, t); |
294 | } | |
295 | ||
296 | static int omap2_onenand_setup_async(void __iomem *onenand_base) | |
297 | { | |
298 | struct gpmc_timings t; | |
299 | int ret; | |
300 | ||
301 | omap2_onenand_set_async_mode(onenand_base); | |
302 | ||
303 | t = omap2_onenand_calc_async_timings(); | |
304 | ||
305 | ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); | |
306 | if (IS_ERR_VALUE(ret)) | |
307 | return ret; | |
308 | ||
309 | omap2_onenand_set_async_mode(onenand_base); | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) | |
315 | { | |
316 | int ret, freq = *freq_ptr; | |
317 | struct gpmc_timings t; | |
46376884 AM |
318 | |
319 | if (!freq) { | |
320 | /* Very first call freq is not known */ | |
757ef791 | 321 | freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base); |
46376884 AM |
322 | set_onenand_cfg(onenand_base); |
323 | } | |
324 | ||
757ef791 | 325 | t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); |
aa62e90f | 326 | |
46376884 AM |
327 | ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); |
328 | if (IS_ERR_VALUE(ret)) | |
329 | return ret; | |
330 | ||
331 | set_onenand_cfg(onenand_base); | |
aa62e90f | 332 | |
3ad2d861 AH |
333 | *freq_ptr = freq; |
334 | ||
aa62e90f JY |
335 | return 0; |
336 | } | |
337 | ||
3ad2d861 | 338 | static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) |
aa62e90f JY |
339 | { |
340 | struct device *dev = &gpmc_onenand_device.dev; | |
46376884 AM |
341 | unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE; |
342 | int ret; | |
aa62e90f | 343 | |
46376884 AM |
344 | ret = omap2_onenand_setup_async(onenand_base); |
345 | if (ret) { | |
346 | dev_err(dev, "unable to set to async mode\n"); | |
347 | return ret; | |
aa62e90f JY |
348 | } |
349 | ||
46376884 AM |
350 | if (!(gpmc_onenand_data->flags & l)) |
351 | return 0; | |
352 | ||
353 | ret = omap2_onenand_setup_sync(onenand_base, freq_ptr); | |
354 | if (ret) | |
355 | dev_err(dev, "unable to set to sync mode\n"); | |
356 | return ret; | |
aa62e90f JY |
357 | } |
358 | ||
359 | void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) | |
360 | { | |
681988ba AM |
361 | int err; |
362 | ||
aa62e90f JY |
363 | gpmc_onenand_data = _onenand_data; |
364 | gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; | |
365 | gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; | |
366 | ||
367 | if (cpu_is_omap24xx() && | |
368 | (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { | |
369 | printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n"); | |
370 | gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE; | |
371 | gpmc_onenand_data->flags |= ONENAND_SYNC_READ; | |
372 | } | |
373 | ||
eb77b6a7 AM |
374 | if (cpu_is_omap34xx()) |
375 | gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX; | |
376 | else | |
377 | gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX; | |
378 | ||
681988ba AM |
379 | err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, |
380 | (unsigned long *)&gpmc_onenand_resource.start); | |
381 | if (err < 0) { | |
382 | pr_err("%s: Cannot request GPMC CS\n", __func__); | |
383 | return; | |
384 | } | |
385 | ||
386 | gpmc_onenand_resource.end = gpmc_onenand_resource.start + | |
387 | ONENAND_IO_SIZE - 1; | |
388 | ||
aa62e90f | 389 | if (platform_device_register(&gpmc_onenand_device) < 0) { |
681988ba AM |
390 | pr_err("%s: Unable to register OneNAND device\n", __func__); |
391 | gpmc_cs_free(gpmc_onenand_data->cs); | |
aa62e90f JY |
392 | return; |
393 | } | |
394 | } |