Commit | Line | Data |
---|---|---|
4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
4bbbc1ad JY |
17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/clk.h> | |
f37e4580 ID |
21 | #include <linux/ioport.h> |
22 | #include <linux/spinlock.h> | |
fced80c7 | 23 | #include <linux/io.h> |
fd1dc87d | 24 | #include <linux/module.h> |
4bbbc1ad | 25 | |
7f245162 | 26 | #include <asm/mach-types.h> |
ce491cf8 | 27 | #include <plat/gpmc.h> |
4bbbc1ad | 28 | |
ce491cf8 | 29 | #include <plat/sdrc.h> |
72d0f1c3 | 30 | |
fd1dc87d | 31 | /* GPMC register offsets */ |
4bbbc1ad JY |
32 | #define GPMC_REVISION 0x00 |
33 | #define GPMC_SYSCONFIG 0x10 | |
34 | #define GPMC_SYSSTATUS 0x14 | |
35 | #define GPMC_IRQSTATUS 0x18 | |
36 | #define GPMC_IRQENABLE 0x1c | |
37 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
38 | #define GPMC_ERR_ADDRESS 0x44 | |
39 | #define GPMC_ERR_TYPE 0x48 | |
40 | #define GPMC_CONFIG 0x50 | |
41 | #define GPMC_STATUS 0x54 | |
42 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
43 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 44 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
45 | #define GPMC_PREFETCH_STATUS 0x1f0 |
46 | #define GPMC_ECC_CONFIG 0x1f4 | |
47 | #define GPMC_ECC_CONTROL 0x1f8 | |
48 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 49 | #define GPMC_ECC1_RESULT 0x200 |
4bbbc1ad | 50 | |
948d38e7 | 51 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad JY |
52 | #define GPMC_CS_SIZE 0x30 |
53 | ||
f37e4580 ID |
54 | #define GPMC_MEM_START 0x00000000 |
55 | #define GPMC_MEM_END 0x3FFFFFFF | |
56 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | |
57 | ||
58 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
59 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
60 | ||
59e9c5ae | 61 | #define PREFETCH_FIFOTHRESHOLD (0x40 << 8) |
62 | #define CS_NUM_SHIFT 24 | |
63 | #define ENABLE_PREFETCH (0x1 << 7) | |
64 | #define DMA_MPU_MODE 2 | |
65 | ||
a2d3e7ba RN |
66 | /* Structure to save gpmc cs context */ |
67 | struct gpmc_cs_config { | |
68 | u32 config1; | |
69 | u32 config2; | |
70 | u32 config3; | |
71 | u32 config4; | |
72 | u32 config5; | |
73 | u32 config6; | |
74 | u32 config7; | |
75 | int is_valid; | |
76 | }; | |
77 | ||
78 | /* | |
79 | * Structure to save/restore gpmc context | |
80 | * to support core off on OMAP3 | |
81 | */ | |
82 | struct omap3_gpmc_regs { | |
83 | u32 sysconfig; | |
84 | u32 irqenable; | |
85 | u32 timeout_ctrl; | |
86 | u32 config; | |
87 | u32 prefetch_config1; | |
88 | u32 prefetch_config2; | |
89 | u32 prefetch_control; | |
90 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
91 | }; | |
92 | ||
f37e4580 ID |
93 | static struct resource gpmc_mem_root; |
94 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 95 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
948d38e7 SG |
96 | static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ |
97 | static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ | |
f37e4580 | 98 | |
fd1dc87d | 99 | static void __iomem *gpmc_base; |
4bbbc1ad | 100 | |
fd1dc87d | 101 | static struct clk *gpmc_l3_clk; |
4bbbc1ad JY |
102 | |
103 | static void gpmc_write_reg(int idx, u32 val) | |
104 | { | |
105 | __raw_writel(val, gpmc_base + idx); | |
106 | } | |
107 | ||
108 | static u32 gpmc_read_reg(int idx) | |
109 | { | |
110 | return __raw_readl(gpmc_base + idx); | |
111 | } | |
112 | ||
948d38e7 SG |
113 | static void gpmc_cs_write_byte(int cs, int idx, u8 val) |
114 | { | |
115 | void __iomem *reg_addr; | |
116 | ||
117 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | |
118 | __raw_writeb(val, reg_addr); | |
119 | } | |
120 | ||
121 | static u8 gpmc_cs_read_byte(int cs, int idx) | |
122 | { | |
123 | void __iomem *reg_addr; | |
124 | ||
125 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | |
126 | return __raw_readb(reg_addr); | |
127 | } | |
128 | ||
4bbbc1ad JY |
129 | void gpmc_cs_write_reg(int cs, int idx, u32 val) |
130 | { | |
131 | void __iomem *reg_addr; | |
132 | ||
948d38e7 | 133 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
4bbbc1ad JY |
134 | __raw_writel(val, reg_addr); |
135 | } | |
136 | ||
137 | u32 gpmc_cs_read_reg(int cs, int idx) | |
138 | { | |
fd1dc87d PW |
139 | void __iomem *reg_addr; |
140 | ||
948d38e7 | 141 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
fd1dc87d | 142 | return __raw_readl(reg_addr); |
4bbbc1ad JY |
143 | } |
144 | ||
fd1dc87d | 145 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
1c22cc13 | 146 | unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 147 | { |
fd1dc87d PW |
148 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
149 | ||
150 | if (rate == 0) { | |
151 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
152 | return 0; | |
153 | } | |
154 | ||
155 | rate /= 1000; | |
156 | rate = 1000000000 / rate; /* In picoseconds */ | |
157 | ||
158 | return rate; | |
4bbbc1ad JY |
159 | } |
160 | ||
161 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |
162 | { | |
163 | unsigned long tick_ps; | |
164 | ||
165 | /* Calculate in picosecs to yield more exact results */ | |
166 | tick_ps = gpmc_get_fclk_period(); | |
167 | ||
168 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
169 | } | |
170 | ||
fd1dc87d PW |
171 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
172 | { | |
173 | return ticks * gpmc_get_fclk_period() / 1000; | |
174 | } | |
175 | ||
23300597 KS |
176 | unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) |
177 | { | |
178 | unsigned long ticks = gpmc_ns_to_ticks(time_ns); | |
179 | ||
180 | return ticks * gpmc_get_fclk_period() / 1000; | |
181 | } | |
182 | ||
4bbbc1ad JY |
183 | #ifdef DEBUG |
184 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
2aab6468 | 185 | int time, const char *name) |
4bbbc1ad JY |
186 | #else |
187 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
188 | int time) | |
189 | #endif | |
190 | { | |
191 | u32 l; | |
192 | int ticks, mask, nr_bits; | |
193 | ||
194 | if (time == 0) | |
195 | ticks = 0; | |
196 | else | |
197 | ticks = gpmc_ns_to_ticks(time); | |
198 | nr_bits = end_bit - st_bit + 1; | |
1c22cc13 DB |
199 | if (ticks >= 1 << nr_bits) { |
200 | #ifdef DEBUG | |
201 | printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", | |
202 | cs, name, time, ticks, 1 << nr_bits); | |
203 | #endif | |
4bbbc1ad | 204 | return -1; |
1c22cc13 | 205 | } |
4bbbc1ad JY |
206 | |
207 | mask = (1 << nr_bits) - 1; | |
208 | l = gpmc_cs_read_reg(cs, reg); | |
209 | #ifdef DEBUG | |
1c22cc13 DB |
210 | printk(KERN_INFO |
211 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 212 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 213 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
214 | #endif |
215 | l &= ~(mask << st_bit); | |
216 | l |= ticks << st_bit; | |
217 | gpmc_cs_write_reg(cs, reg, l); | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
222 | #ifdef DEBUG | |
223 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
224 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
225 | t->field, #field) < 0) \ | |
226 | return -1 | |
227 | #else | |
228 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
229 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
230 | return -1 | |
231 | #endif | |
232 | ||
233 | int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) | |
234 | { | |
235 | int div; | |
236 | u32 l; | |
237 | ||
238 | l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1); | |
239 | div = l / gpmc_get_fclk_period(); | |
240 | if (div > 4) | |
241 | return -1; | |
1c22cc13 | 242 | if (div <= 0) |
4bbbc1ad JY |
243 | div = 1; |
244 | ||
245 | return div; | |
246 | } | |
247 | ||
248 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
249 | { | |
250 | int div; | |
251 | u32 l; | |
252 | ||
253 | div = gpmc_cs_calc_divider(cs, t->sync_clk); | |
254 | if (div < 0) | |
255 | return -1; | |
256 | ||
257 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
258 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
259 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
260 | ||
261 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
262 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
263 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
264 | ||
265 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
266 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
267 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
268 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
269 | ||
270 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
271 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
272 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
273 | ||
274 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
275 | ||
cc26b3b0 SMK |
276 | if (cpu_is_omap34xx()) { |
277 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); | |
278 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); | |
279 | } | |
280 | ||
1c22cc13 DB |
281 | /* caller is expected to have initialized CONFIG1 to cover |
282 | * at least sync vs async | |
283 | */ | |
284 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
285 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 286 | #ifdef DEBUG |
1c22cc13 DB |
287 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
288 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 289 | #endif |
1c22cc13 DB |
290 | l &= ~0x03; |
291 | l |= (div - 1); | |
292 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
293 | } | |
4bbbc1ad JY |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
f37e4580 ID |
298 | static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
299 | { | |
300 | u32 l; | |
301 | u32 mask; | |
302 | ||
303 | mask = (1 << GPMC_SECTION_SHIFT) - size; | |
304 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
305 | l &= ~0x3f; | |
306 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
307 | l &= ~(0x0f << 8); | |
308 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 309 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
310 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
311 | } | |
312 | ||
313 | static void gpmc_cs_disable_mem(int cs) | |
314 | { | |
315 | u32 l; | |
316 | ||
317 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 318 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
319 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
320 | } | |
321 | ||
322 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
323 | { | |
324 | u32 l; | |
325 | u32 mask; | |
326 | ||
327 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
328 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
329 | mask = (l >> 8) & 0x0f; | |
330 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
331 | } | |
332 | ||
333 | static int gpmc_cs_mem_enabled(int cs) | |
334 | { | |
335 | u32 l; | |
336 | ||
337 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 338 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
339 | } |
340 | ||
c40fae95 | 341 | int gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 342 | { |
c40fae95 TL |
343 | if (cs > GPMC_CS_NUM) |
344 | return -ENODEV; | |
345 | ||
f37e4580 ID |
346 | gpmc_cs_map &= ~(1 << cs); |
347 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
c40fae95 TL |
348 | |
349 | return 0; | |
f37e4580 ID |
350 | } |
351 | ||
c40fae95 | 352 | int gpmc_cs_reserved(int cs) |
f37e4580 | 353 | { |
c40fae95 TL |
354 | if (cs > GPMC_CS_NUM) |
355 | return -ENODEV; | |
356 | ||
f37e4580 ID |
357 | return gpmc_cs_map & (1 << cs); |
358 | } | |
359 | ||
360 | static unsigned long gpmc_mem_align(unsigned long size) | |
361 | { | |
362 | int order; | |
363 | ||
364 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
365 | order = GPMC_CHUNK_SHIFT - 1; | |
366 | do { | |
367 | size >>= 1; | |
368 | order++; | |
369 | } while (size); | |
370 | size = 1 << order; | |
371 | return size; | |
372 | } | |
373 | ||
374 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
375 | { | |
376 | struct resource *res = &gpmc_cs_mem[cs]; | |
377 | int r; | |
378 | ||
379 | size = gpmc_mem_align(size); | |
380 | spin_lock(&gpmc_mem_lock); | |
381 | res->start = base; | |
382 | res->end = base + size - 1; | |
383 | r = request_resource(&gpmc_mem_root, res); | |
384 | spin_unlock(&gpmc_mem_lock); | |
385 | ||
386 | return r; | |
387 | } | |
388 | ||
389 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) | |
390 | { | |
391 | struct resource *res = &gpmc_cs_mem[cs]; | |
392 | int r = -1; | |
393 | ||
394 | if (cs > GPMC_CS_NUM) | |
395 | return -ENODEV; | |
396 | ||
397 | size = gpmc_mem_align(size); | |
398 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
399 | return -ENOMEM; | |
400 | ||
401 | spin_lock(&gpmc_mem_lock); | |
402 | if (gpmc_cs_reserved(cs)) { | |
403 | r = -EBUSY; | |
404 | goto out; | |
405 | } | |
406 | if (gpmc_cs_mem_enabled(cs)) | |
407 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
408 | if (r < 0) | |
409 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
410 | size, NULL, NULL); | |
411 | if (r < 0) | |
412 | goto out; | |
413 | ||
6d135242 | 414 | gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
f37e4580 ID |
415 | *base = res->start; |
416 | gpmc_cs_set_reserved(cs, 1); | |
417 | out: | |
418 | spin_unlock(&gpmc_mem_lock); | |
419 | return r; | |
420 | } | |
fd1dc87d | 421 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
422 | |
423 | void gpmc_cs_free(int cs) | |
424 | { | |
425 | spin_lock(&gpmc_mem_lock); | |
e7fdc605 | 426 | if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
427 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
428 | BUG(); | |
429 | spin_unlock(&gpmc_mem_lock); | |
430 | return; | |
431 | } | |
432 | gpmc_cs_disable_mem(cs); | |
433 | release_resource(&gpmc_cs_mem[cs]); | |
434 | gpmc_cs_set_reserved(cs, 0); | |
435 | spin_unlock(&gpmc_mem_lock); | |
436 | } | |
fd1dc87d | 437 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 438 | |
948d38e7 SG |
439 | /** |
440 | * gpmc_read_status - read access request to get the different gpmc status | |
441 | * @cmd: command type | |
442 | * @return status | |
443 | */ | |
444 | int gpmc_read_status(int cmd) | |
445 | { | |
446 | int status = -EINVAL; | |
447 | u32 regval = 0; | |
448 | ||
449 | switch (cmd) { | |
450 | case GPMC_GET_IRQ_STATUS: | |
451 | status = gpmc_read_reg(GPMC_IRQSTATUS); | |
452 | break; | |
453 | ||
454 | case GPMC_PREFETCH_FIFO_CNT: | |
455 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | |
456 | status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); | |
457 | break; | |
458 | ||
459 | case GPMC_PREFETCH_COUNT: | |
460 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | |
461 | status = GPMC_PREFETCH_STATUS_COUNT(regval); | |
462 | break; | |
463 | ||
464 | case GPMC_STATUS_BUFFER: | |
465 | regval = gpmc_read_reg(GPMC_STATUS); | |
466 | /* 1 : buffer is available to write */ | |
467 | status = regval & GPMC_STATUS_BUFF_EMPTY; | |
468 | break; | |
469 | ||
470 | default: | |
471 | printk(KERN_ERR "gpmc_read_status: Not supported\n"); | |
472 | } | |
473 | return status; | |
474 | } | |
475 | EXPORT_SYMBOL(gpmc_read_status); | |
476 | ||
477 | /** | |
478 | * gpmc_cs_configure - write request to configure gpmc | |
479 | * @cs: chip select number | |
480 | * @cmd: command type | |
481 | * @wval: value to write | |
482 | * @return status of the operation | |
483 | */ | |
484 | int gpmc_cs_configure(int cs, int cmd, int wval) | |
485 | { | |
486 | int err = 0; | |
487 | u32 regval = 0; | |
488 | ||
489 | switch (cmd) { | |
490 | case GPMC_SET_IRQ_STATUS: | |
491 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
492 | break; | |
493 | ||
494 | case GPMC_CONFIG_WP: | |
495 | regval = gpmc_read_reg(GPMC_CONFIG); | |
496 | if (wval) | |
497 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
498 | else | |
499 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
500 | gpmc_write_reg(GPMC_CONFIG, regval); | |
501 | break; | |
502 | ||
503 | case GPMC_CONFIG_RDY_BSY: | |
504 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
505 | if (wval) | |
506 | regval |= WR_RD_PIN_MONITORING; | |
507 | else | |
508 | regval &= ~WR_RD_PIN_MONITORING; | |
509 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
510 | break; | |
511 | ||
512 | case GPMC_CONFIG_DEV_SIZE: | |
513 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
514 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); | |
515 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
516 | break; | |
517 | ||
518 | case GPMC_CONFIG_DEV_TYPE: | |
519 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
520 | regval |= GPMC_CONFIG1_DEVICETYPE(wval); | |
521 | if (wval == GPMC_DEVICETYPE_NOR) | |
522 | regval |= GPMC_CONFIG1_MUXADDDATA; | |
523 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
524 | break; | |
525 | ||
526 | default: | |
527 | printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); | |
528 | err = -EINVAL; | |
529 | } | |
530 | ||
531 | return err; | |
532 | } | |
533 | EXPORT_SYMBOL(gpmc_cs_configure); | |
534 | ||
535 | /** | |
536 | * gpmc_nand_read - nand specific read access request | |
537 | * @cs: chip select number | |
538 | * @cmd: command type | |
539 | */ | |
540 | int gpmc_nand_read(int cs, int cmd) | |
541 | { | |
542 | int rval = -EINVAL; | |
543 | ||
544 | switch (cmd) { | |
545 | case GPMC_NAND_DATA: | |
546 | rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA); | |
547 | break; | |
548 | ||
549 | default: | |
550 | printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n"); | |
551 | } | |
552 | return rval; | |
553 | } | |
554 | EXPORT_SYMBOL(gpmc_nand_read); | |
555 | ||
556 | /** | |
557 | * gpmc_nand_write - nand specific write request | |
558 | * @cs: chip select number | |
559 | * @cmd: command type | |
560 | * @wval: value to write | |
561 | */ | |
562 | int gpmc_nand_write(int cs, int cmd, int wval) | |
563 | { | |
564 | int err = 0; | |
565 | ||
566 | switch (cmd) { | |
567 | case GPMC_NAND_COMMAND: | |
568 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval); | |
569 | break; | |
570 | ||
571 | case GPMC_NAND_ADDRESS: | |
572 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval); | |
573 | break; | |
574 | ||
575 | case GPMC_NAND_DATA: | |
576 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval); | |
577 | ||
578 | default: | |
579 | printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n"); | |
580 | err = -EINVAL; | |
581 | } | |
582 | return err; | |
583 | } | |
584 | EXPORT_SYMBOL(gpmc_nand_write); | |
585 | ||
586 | ||
587 | ||
59e9c5ae | 588 | /** |
589 | * gpmc_prefetch_enable - configures and starts prefetch transfer | |
948d38e7 | 590 | * @cs: cs (chip select) number |
59e9c5ae | 591 | * @dma_mode: dma mode enable (1) or disable (0) |
592 | * @u32_count: number of bytes to be transferred | |
593 | * @is_write: prefetch read(0) or write post(1) mode | |
594 | */ | |
595 | int gpmc_prefetch_enable(int cs, int dma_mode, | |
596 | unsigned int u32_count, int is_write) | |
597 | { | |
59e9c5ae | 598 | |
599 | if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { | |
600 | /* Set the amount of bytes to be prefetched */ | |
601 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); | |
602 | ||
603 | /* Set dma/mpu mode, the prefetch read / post write and | |
604 | * enable the engine. Set which cs is has requested for. | |
605 | */ | |
948d38e7 | 606 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | |
59e9c5ae | 607 | PREFETCH_FIFOTHRESHOLD | |
608 | ENABLE_PREFETCH | | |
609 | (dma_mode << DMA_MPU_MODE) | | |
948d38e7 SG |
610 | (0x1 & is_write))); |
611 | ||
612 | /* Start the prefetch engine */ | |
613 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); | |
59e9c5ae | 614 | } else { |
615 | return -EBUSY; | |
616 | } | |
59e9c5ae | 617 | |
618 | return 0; | |
619 | } | |
620 | EXPORT_SYMBOL(gpmc_prefetch_enable); | |
621 | ||
622 | /** | |
623 | * gpmc_prefetch_reset - disables and stops the prefetch engine | |
624 | */ | |
948d38e7 | 625 | int gpmc_prefetch_reset(int cs) |
59e9c5ae | 626 | { |
948d38e7 SG |
627 | u32 config1; |
628 | ||
629 | /* check if the same module/cs is trying to reset */ | |
630 | config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
631 | if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) | |
632 | return -EINVAL; | |
633 | ||
59e9c5ae | 634 | /* Stop the PFPW engine */ |
635 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); | |
636 | ||
637 | /* Reset/disable the PFPW engine */ | |
638 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); | |
948d38e7 SG |
639 | |
640 | return 0; | |
59e9c5ae | 641 | } |
642 | EXPORT_SYMBOL(gpmc_prefetch_reset); | |
643 | ||
fd1dc87d | 644 | static void __init gpmc_mem_init(void) |
f37e4580 ID |
645 | { |
646 | int cs; | |
647 | unsigned long boot_rom_space = 0; | |
648 | ||
7f245162 KP |
649 | /* never allocate the first page, to facilitate bug detection; |
650 | * even if we didn't boot from ROM. | |
651 | */ | |
652 | boot_rom_space = BOOT_ROM_SPACE; | |
653 | /* In apollon the CS0 is mapped as 0x0000 0000 */ | |
654 | if (machine_is_omap_apollon()) | |
655 | boot_rom_space = 0; | |
f37e4580 ID |
656 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; |
657 | gpmc_mem_root.end = GPMC_MEM_END; | |
658 | ||
659 | /* Reserve all regions that has been set up by bootloader */ | |
660 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
661 | u32 base, size; | |
662 | ||
663 | if (!gpmc_cs_mem_enabled(cs)) | |
664 | continue; | |
665 | gpmc_cs_get_memconf(cs, &base, &size); | |
666 | if (gpmc_cs_insert_mem(cs, base, size) < 0) | |
667 | BUG(); | |
668 | } | |
4bbbc1ad JY |
669 | } |
670 | ||
671 | void __init gpmc_init(void) | |
672 | { | |
673 | u32 l; | |
8d08436d | 674 | char *ck = NULL; |
fd1dc87d PW |
675 | |
676 | if (cpu_is_omap24xx()) { | |
677 | ck = "core_l3_ck"; | |
678 | if (cpu_is_omap2420()) | |
679 | l = OMAP2420_GPMC_BASE; | |
680 | else | |
681 | l = OMAP34XX_GPMC_BASE; | |
682 | } else if (cpu_is_omap34xx()) { | |
683 | ck = "gpmc_fck"; | |
684 | l = OMAP34XX_GPMC_BASE; | |
44169075 | 685 | } else if (cpu_is_omap44xx()) { |
d79b1267 | 686 | ck = "gpmc_ck"; |
44169075 | 687 | l = OMAP44XX_GPMC_BASE; |
fd1dc87d | 688 | } |
4bbbc1ad | 689 | |
8d08436d KH |
690 | if (WARN_ON(!ck)) |
691 | return; | |
692 | ||
fd1dc87d PW |
693 | gpmc_l3_clk = clk_get(NULL, ck); |
694 | if (IS_ERR(gpmc_l3_clk)) { | |
695 | printk(KERN_ERR "Could not get GPMC clock %s\n", ck); | |
85d7a070 | 696 | BUG(); |
fd1dc87d PW |
697 | } |
698 | ||
699 | gpmc_base = ioremap(l, SZ_4K); | |
700 | if (!gpmc_base) { | |
701 | clk_put(gpmc_l3_clk); | |
702 | printk(KERN_ERR "Could not get GPMC register memory\n"); | |
85d7a070 | 703 | BUG(); |
fd1dc87d PW |
704 | } |
705 | ||
1daa8c1d OJ |
706 | clk_enable(gpmc_l3_clk); |
707 | ||
4bbbc1ad JY |
708 | l = gpmc_read_reg(GPMC_REVISION); |
709 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | |
710 | /* Set smart idle mode and automatic L3 clock gating */ | |
711 | l = gpmc_read_reg(GPMC_SYSCONFIG); | |
712 | l &= 0x03 << 3; | |
713 | l |= (0x02 << 3) | (1 << 0); | |
714 | gpmc_write_reg(GPMC_SYSCONFIG, l); | |
f37e4580 | 715 | gpmc_mem_init(); |
4bbbc1ad | 716 | } |
a2d3e7ba RN |
717 | |
718 | #ifdef CONFIG_ARCH_OMAP3 | |
719 | static struct omap3_gpmc_regs gpmc_context; | |
720 | ||
b2fa3b7c | 721 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
722 | { |
723 | int i; | |
b2fa3b7c | 724 | |
a2d3e7ba RN |
725 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
726 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
727 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
728 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
729 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
730 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
731 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
732 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
733 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | |
734 | if (gpmc_context.cs_context[i].is_valid) { | |
735 | gpmc_context.cs_context[i].config1 = | |
736 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
737 | gpmc_context.cs_context[i].config2 = | |
738 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
739 | gpmc_context.cs_context[i].config3 = | |
740 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
741 | gpmc_context.cs_context[i].config4 = | |
742 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
743 | gpmc_context.cs_context[i].config5 = | |
744 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
745 | gpmc_context.cs_context[i].config6 = | |
746 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
747 | gpmc_context.cs_context[i].config7 = | |
748 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
749 | } | |
750 | } | |
751 | } | |
752 | ||
b2fa3b7c | 753 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
754 | { |
755 | int i; | |
b2fa3b7c | 756 | |
a2d3e7ba RN |
757 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
758 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
759 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
760 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
761 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
762 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
763 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
764 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
765 | if (gpmc_context.cs_context[i].is_valid) { | |
766 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
767 | gpmc_context.cs_context[i].config1); | |
768 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
769 | gpmc_context.cs_context[i].config2); | |
770 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
771 | gpmc_context.cs_context[i].config3); | |
772 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
773 | gpmc_context.cs_context[i].config4); | |
774 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
775 | gpmc_context.cs_context[i].config5); | |
776 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
777 | gpmc_context.cs_context[i].config6); | |
778 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
779 | gpmc_context.cs_context[i].config7); | |
780 | } | |
781 | } | |
782 | } | |
783 | #endif /* CONFIG_ARCH_OMAP3 */ | |
948d38e7 SG |
784 | |
785 | /** | |
786 | * gpmc_enable_hwecc - enable hardware ecc functionality | |
787 | * @cs: chip select number | |
788 | * @mode: read/write mode | |
789 | * @dev_width: device bus width(1 for x16, 0 for x8) | |
790 | * @ecc_size: bytes for which ECC will be generated | |
791 | */ | |
792 | int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) | |
793 | { | |
794 | unsigned int val; | |
795 | ||
796 | /* check if ecc module is in used */ | |
797 | if (gpmc_ecc_used != -EINVAL) | |
798 | return -EINVAL; | |
799 | ||
800 | gpmc_ecc_used = cs; | |
801 | ||
802 | /* clear ecc and enable bits */ | |
803 | val = ((0x00000001<<8) | 0x00000001); | |
804 | gpmc_write_reg(GPMC_ECC_CONTROL, val); | |
805 | ||
806 | /* program ecc and result sizes */ | |
807 | val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); | |
808 | gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val); | |
809 | ||
810 | switch (mode) { | |
811 | case GPMC_ECC_READ: | |
812 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | |
813 | break; | |
814 | case GPMC_ECC_READSYN: | |
815 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x100); | |
816 | break; | |
817 | case GPMC_ECC_WRITE: | |
818 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | |
819 | break; | |
820 | default: | |
821 | printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); | |
822 | break; | |
823 | } | |
824 | ||
825 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
826 | val = (dev_width << 7) | (cs << 1) | (0x1); | |
827 | gpmc_write_reg(GPMC_ECC_CONFIG, val); | |
828 | return 0; | |
829 | } | |
830 | ||
831 | /** | |
832 | * gpmc_calculate_ecc - generate non-inverted ecc bytes | |
833 | * @cs: chip select number | |
834 | * @dat: data pointer over which ecc is computed | |
835 | * @ecc_code: ecc code buffer | |
836 | * | |
837 | * Using non-inverted ECC is considered ugly since writing a blank | |
838 | * page (padding) will clear the ECC bytes. This is not a problem as long | |
839 | * no one is trying to write data on the seemingly unused page. Reading | |
840 | * an erased page will produce an ECC mismatch between generated and read | |
841 | * ECC bytes that has to be dealt with separately. | |
842 | */ | |
843 | int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code) | |
844 | { | |
845 | unsigned int val = 0x0; | |
846 | ||
847 | if (gpmc_ecc_used != cs) | |
848 | return -EINVAL; | |
849 | ||
850 | /* read ecc result */ | |
851 | val = gpmc_read_reg(GPMC_ECC1_RESULT); | |
852 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
853 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
854 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
855 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
856 | ||
857 | gpmc_ecc_used = -EINVAL; | |
858 | return 0; | |
859 | } |