[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.c

/*
 * GPMC support functions
 *
 * Copyright (C) 2005-2006 Nokia Corporation
 *
 * Author: Juha Yrjola
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>

#include <asm/io.h>
#include <asm/mach-types.h>
#include <mach/gpmc.h>

#undef DEBUG

#ifdef CONFIG_ARCH_OMAP2420
#define GPMC_BASE		0x6800a000
#endif

#ifdef CONFIG_ARCH_OMAP2430
#define GPMC_BASE		0x6E000000
#endif

#define GPMC_REVISION		0x00
#define GPMC_SYSCONFIG		0x10
#define GPMC_SYSSTATUS		0x14
#define GPMC_IRQSTATUS		0x18
#define GPMC_IRQENABLE		0x1c
#define GPMC_TIMEOUT_CONTROL	0x40
#define GPMC_ERR_ADDRESS	0x44
#define GPMC_ERR_TYPE		0x48
#define GPMC_CONFIG		0x50
#define GPMC_STATUS		0x54
#define GPMC_PREFETCH_CONFIG1	0x1e0
#define GPMC_PREFETCH_CONFIG2	0x1e4
#define GPMC_PREFETCH_CONTROL	0x1ec
#define GPMC_PREFETCH_STATUS	0x1f0
#define GPMC_ECC_CONFIG		0x1f4
#define GPMC_ECC_CONTROL	0x1f8
#define GPMC_ECC_SIZE_CONFIG	0x1fc

#define GPMC_CS0		0x60
#define GPMC_CS_SIZE		0x30

#define GPMC_CS_NUM		8
#define GPMC_MEM_START		0x00000000
#define GPMC_MEM_END		0x3FFFFFFF
#define BOOT_ROM_SPACE		0x100000	/* 1MB */

#define GPMC_CHUNK_SHIFT	24		/* 16 MB */
#define GPMC_SECTION_SHIFT	28		/* 128 MB */

static struct resource	gpmc_mem_root;
static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned		gpmc_cs_map;

static void __iomem *gpmc_base = IO_ADDRESS(GPMC_BASE);
static void __iomem *gpmc_cs_base = IO_ADDRESS(GPMC_BASE) + GPMC_CS0;

static struct clk *gpmc_fck;

static void gpmc_write_reg(int idx, u32 val)
{
	__raw_writel(val, gpmc_base + idx);
}

static u32 gpmc_read_reg(int idx)
{
	return __raw_readl(gpmc_base + idx);
}

void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
	void __iomem *reg_addr;

	reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
	__raw_writel(val, reg_addr);
}

u32 gpmc_cs_read_reg(int cs, int idx)
{
	return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
}

unsigned long gpmc_get_fclk_period(void)
{
	/* In picoseconds */
	return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
}

unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
	unsigned long tick_ps;

	/* Calculate in picosecs to yield more exact results */
	tick_ps = gpmc_get_fclk_period();

	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}

unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
{
	unsigned long ticks = gpmc_ns_to_ticks(time_ns);

	return ticks * gpmc_get_fclk_period() / 1000;
}

#ifdef DEBUG
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time, const char *name)
#else
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time)
#endif
{
	u32 l;
	int ticks, mask, nr_bits;

	if (time == 0)
		ticks = 0;
	else
		ticks = gpmc_ns_to_ticks(time);
	nr_bits = end_bit - st_bit + 1;
	if (ticks >= 1 << nr_bits) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
				cs, name, time, ticks, 1 << nr_bits);
#endif
		return -1;
	}

	mask = (1 << nr_bits) - 1;
	l = gpmc_cs_read_reg(cs, reg);
#ifdef DEBUG
	printk(KERN_INFO
		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
			(l >> st_bit) & mask, time);
#endif
	l &= ~(mask << st_bit);
	l |= ticks << st_bit;
	gpmc_cs_write_reg(cs, reg, l);

	return 0;
}

#ifdef DEBUG
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
			t->field, #field) < 0)			\
		return -1
#else
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
		return -1
#endif

int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
{
	int div;
	u32 l;

	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	div = l / gpmc_get_fclk_period();
	if (div > 4)
		return -1;
	if (div <= 0)
		div = 1;

	return div;
}

int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
	int div;
	u32 l;

	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	if (div < 0)
		return -1;

	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);

	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);

	/* caller is expected to have initialized CONFIG1 to cover
	 * at least sync vs async
	 */
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
				cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif
		l &= ~0x03;
		l |= (div - 1);
		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	}

	return 0;
}

static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
{
	u32 l;
	u32 mask;

	mask = (1 << GPMC_SECTION_SHIFT) - size;
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~0x3f;
	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	l &= ~(0x0f << 8);
	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	l |= 1 << 6;		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_disable_mem(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~(1 << 6);		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
{
	u32 l;
	u32 mask;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	mask = (l >> 8) & 0x0f;
	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
}

static int gpmc_cs_mem_enabled(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	return l & (1 << 6);
}

int gpmc_cs_set_reserved(int cs, int reserved)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	gpmc_cs_map &= ~(1 << cs);
	gpmc_cs_map |= (reserved ? 1 : 0) << cs;

	return 0;
}

int gpmc_cs_reserved(int cs)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	return gpmc_cs_map & (1 << cs);
}

static unsigned long gpmc_mem_align(unsigned long size)
{
	int order;

	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	order = GPMC_CHUNK_SHIFT - 1;
	do {
		size >>= 1;
		order++;
	} while (size);
	size = 1 << order;
	return size;
}

static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
{
	struct resource	*res = &gpmc_cs_mem[cs];
	int r;

	size = gpmc_mem_align(size);
	spin_lock(&gpmc_mem_lock);
	res->start = base;
	res->end = base + size - 1;
	r = request_resource(&gpmc_mem_root, res);
	spin_unlock(&gpmc_mem_lock);

	return r;
}

int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
	struct resource *res = &gpmc_cs_mem[cs];
	int r = -1;

	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	size = gpmc_mem_align(size);
	if (size > (1 << GPMC_SECTION_SHIFT))
		return -ENOMEM;

	spin_lock(&gpmc_mem_lock);
	if (gpmc_cs_reserved(cs)) {
		r = -EBUSY;
		goto out;
	}
	if (gpmc_cs_mem_enabled(cs))
		r = adjust_resource(res, res->start & ~(size - 1), size);
	if (r < 0)
		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
				      size, NULL, NULL);
	if (r < 0)
		goto out;

	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
	*base = res->start;
	gpmc_cs_set_reserved(cs, 1);
out:
	spin_unlock(&gpmc_mem_lock);
	return r;
}

void gpmc_cs_free(int cs)
{
	spin_lock(&gpmc_mem_lock);
	if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
		BUG();
		spin_unlock(&gpmc_mem_lock);
		return;
	}
	gpmc_cs_disable_mem(cs);
	release_resource(&gpmc_cs_mem[cs]);
	gpmc_cs_set_reserved(cs, 0);
	spin_unlock(&gpmc_mem_lock);
}

void __init gpmc_mem_init(void)
{
	int cs;
	unsigned long boot_rom_space = 0;

	/* never allocate the first page, to facilitate bug detection;
	 * even if we didn't boot from ROM.
	 */
	boot_rom_space = BOOT_ROM_SPACE;
	/* In apollon the CS0 is mapped as 0x0000 0000 */
	if (machine_is_omap_apollon())
		boot_rom_space = 0;
	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	gpmc_mem_root.end = GPMC_MEM_END;

	/* Reserve all regions that has been set up by bootloader */
	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
		u32 base, size;

		if (!gpmc_cs_mem_enabled(cs))
			continue;
		gpmc_cs_get_memconf(cs, &base, &size);
		if (gpmc_cs_insert_mem(cs, base, size) < 0)
			BUG();
	}
}

void __init gpmc_init(void)
{
	u32 l;

	gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
	if (IS_ERR(gpmc_fck))
		WARN_ON(1);
	else
		clk_enable(gpmc_fck);

	l = gpmc_read_reg(GPMC_REVISION);
	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	/* Set smart idle mode and automatic L3 clock gating */
	l = gpmc_read_reg(GPMC_SYSCONFIG);
	l &= 0x03 << 3;
	l |= (0x02 << 3) | (1 << 0);
	gpmc_write_reg(GPMC_SYSCONFIG, l);

	gpmc_mem_init();
}
Commit	Line	Data
4bbbc1ad JY	1	/*
	2	* GPMC support functions
	3	*
	4	* Copyright (C) 2005-2006 Nokia Corporation
	5	*
	6	* Author: Juha Yrjola
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
f37e4580 ID	16	#include <linux/ioport.h>
f37e4580 ID	17	#include <linux/spinlock.h>
4bbbc1ad JY	18
4bbbc1ad JY	19	#include <asm/io.h>
7f245162	20	#include <asm/mach-types.h>
a09e64fb	21	#include <mach/gpmc.h>
4bbbc1ad JY	22
	23	#undef DEBUG
	24
72d0f1c3	25	#ifdef CONFIG_ARCH_OMAP2420
4bbbc1ad	26	#define GPMC_BASE 0x6800a000
72d0f1c3 SMK	27	#endif
	28
	29	#ifdef CONFIG_ARCH_OMAP2430
	30	#define GPMC_BASE 0x6E000000
	31	#endif
	32
4bbbc1ad JY	33	#define GPMC_REVISION 0x00
	34	#define GPMC_SYSCONFIG 0x10
	35	#define GPMC_SYSSTATUS 0x14
	36	#define GPMC_IRQSTATUS 0x18
	37	#define GPMC_IRQENABLE 0x1c
	38	#define GPMC_TIMEOUT_CONTROL 0x40
	39	#define GPMC_ERR_ADDRESS 0x44
	40	#define GPMC_ERR_TYPE 0x48
	41	#define GPMC_CONFIG 0x50
	42	#define GPMC_STATUS 0x54
	43	#define GPMC_PREFETCH_CONFIG1 0x1e0
	44	#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b	45	#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad JY	46	#define GPMC_PREFETCH_STATUS 0x1f0
	47	#define GPMC_ECC_CONFIG 0x1f4
	48	#define GPMC_ECC_CONTROL 0x1f8
	49	#define GPMC_ECC_SIZE_CONFIG 0x1fc
	50
	51	#define GPMC_CS0 0x60
	52	#define GPMC_CS_SIZE 0x30
	53
f37e4580 ID	54	#define GPMC_CS_NUM 8
	55	#define GPMC_MEM_START 0x00000000
	56	#define GPMC_MEM_END 0x3FFFFFFF
	57	#define BOOT_ROM_SPACE 0x100000 /* 1MB */
	58
	59	#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
	60	#define GPMC_SECTION_SHIFT 28 /* 128 MB */
	61
	62	static struct resource gpmc_mem_root;
	63	static struct resource gpmc_cs_mem[GPMC_CS_NUM];
87b247c4	64	static DEFINE_SPINLOCK(gpmc_mem_lock);
f37e4580 ID	65	static unsigned gpmc_cs_map;
f37e4580 ID	66
e8a91c95 RK	67	static void __iomem *gpmc_base = IO_ADDRESS(GPMC_BASE);
e8a91c95 RK	68	static void __iomem *gpmc_cs_base = IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
4bbbc1ad	69
44595982	70	static struct clk *gpmc_fck;
4bbbc1ad JY	71
	72	static void gpmc_write_reg(int idx, u32 val)
	73	{
	74	__raw_writel(val, gpmc_base + idx);
	75	}
	76
	77	static u32 gpmc_read_reg(int idx)
	78	{
	79	return __raw_readl(gpmc_base + idx);
	80	}
	81
	82	void gpmc_cs_write_reg(int cs, int idx, u32 val)
	83	{
	84	void __iomem *reg_addr;
	85
	86	reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
	87	__raw_writel(val, reg_addr);
	88	}
	89
	90	u32 gpmc_cs_read_reg(int cs, int idx)
	91	{
	92	return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
	93	}
	94
1c22cc13	95	unsigned long gpmc_get_fclk_period(void)
4bbbc1ad JY	96	{
4bbbc1ad JY	97	/* In picoseconds */
44595982	98	return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
4bbbc1ad JY	99	}
	100
	101	unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
	102	{
	103	unsigned long tick_ps;
	104
	105	/* Calculate in picosecs to yield more exact results */
	106	tick_ps = gpmc_get_fclk_period();
	107
	108	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
	109	}
	110
23300597 KS	111	unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
	112	{
	113	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
	114
	115	return ticks * gpmc_get_fclk_period() / 1000;
	116	}
	117
4bbbc1ad JY	118	#ifdef DEBUG
4bbbc1ad JY	119	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468	120	int time, const char *name)
4bbbc1ad JY	121	#else
	122	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
	123	int time)
	124	#endif
	125	{
	126	u32 l;
	127	int ticks, mask, nr_bits;
	128
	129	if (time == 0)
	130	ticks = 0;
	131	else
	132	ticks = gpmc_ns_to_ticks(time);
	133	nr_bits = end_bit - st_bit + 1;
1c22cc13 DB	134	if (ticks >= 1 << nr_bits) {
	135	#ifdef DEBUG
	136	printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
	137	cs, name, time, ticks, 1 << nr_bits);
	138	#endif
4bbbc1ad	139	return -1;
1c22cc13	140	}
4bbbc1ad JY	141
	142	mask = (1 << nr_bits) - 1;
	143	l = gpmc_cs_read_reg(cs, reg);
	144	#ifdef DEBUG
1c22cc13 DB	145	printk(KERN_INFO
1c22cc13 DB	146	"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
2aab6468	147	cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
1c22cc13	148	(l >> st_bit) & mask, time);
4bbbc1ad JY	149	#endif
	150	l &= ~(mask << st_bit);
	151	l \|= ticks << st_bit;
	152	gpmc_cs_write_reg(cs, reg, l);
	153
	154	return 0;
	155	}
	156
	157	#ifdef DEBUG
	158	#define GPMC_SET_ONE(reg, st, end, field) \
	159	if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
	160	t->field, #field) < 0) \
	161	return -1
	162	#else
	163	#define GPMC_SET_ONE(reg, st, end, field) \
	164	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
	165	return -1
	166	#endif
	167
	168	int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
	169	{
	170	int div;
	171	u32 l;
	172
	173	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	174	div = l / gpmc_get_fclk_period();
	175	if (div > 4)
	176	return -1;
1c22cc13	177	if (div <= 0)
4bbbc1ad JY	178	div = 1;
	179
	180	return div;
	181	}
	182
	183	int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
	184	{
	185	int div;
	186	u32 l;
	187
	188	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	189	if (div < 0)
	190	return -1;
	191
	192	GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
	193	GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
	194	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
	195
	196	GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
	197	GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
	198	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
	199
	200	GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
	201	GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
	202	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	203	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
	204
	205	GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
	206	GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
	207	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
	208
	209	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
	210
1c22cc13 DB	211	/* caller is expected to have initialized CONFIG1 to cover
	212	* at least sync vs async
	213	*/
	214	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	215	if (l & (GPMC_CONFIG1_READTYPE_SYNC \| GPMC_CONFIG1_WRITETYPE_SYNC)) {
4bbbc1ad	216	#ifdef DEBUG
1c22cc13 DB	217	printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
1c22cc13 DB	218	cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad	219	#endif
1c22cc13 DB	220	l &= ~0x03;
	221	l \|= (div - 1);
	222	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	223	}
4bbbc1ad JY	224
	225	return 0;
	226	}
	227
f37e4580 ID	228	static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
	229	{
	230	u32 l;
	231	u32 mask;
	232
	233	mask = (1 << GPMC_SECTION_SHIFT) - size;
	234	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	235	l &= ~0x3f;
	236	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	237	l &= ~(0x0f << 8);
	238	l \|= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	239	l \|= 1 << 6; /* CSVALID */
	240	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	241	}
	242
	243	static void gpmc_cs_disable_mem(int cs)
	244	{
	245	u32 l;
	246
	247	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	248	l &= ~(1 << 6); /* CSVALID */
	249	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	250	}
	251
	252	static void gpmc_cs_get_memconf(int cs, u32 base, u32 size)
	253	{
	254	u32 l;
	255	u32 mask;
	256
	257	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	258	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	259	mask = (l >> 8) & 0x0f;
	260	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
	261	}
	262
	263	static int gpmc_cs_mem_enabled(int cs)
	264	{
	265	u32 l;
	266
	267	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	268	return l & (1 << 6);
	269	}
	270
c40fae95	271	int gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad	272	{
c40fae95 TL	273	if (cs > GPMC_CS_NUM)
	274	return -ENODEV;
	275
f37e4580 ID	276	gpmc_cs_map &= ~(1 << cs);
f37e4580 ID	277	gpmc_cs_map \|= (reserved ? 1 : 0) << cs;
c40fae95 TL	278
c40fae95 TL	279	return 0;
f37e4580 ID	280	}
f37e4580 ID	281
c40fae95	282	int gpmc_cs_reserved(int cs)
f37e4580	283	{
c40fae95 TL	284	if (cs > GPMC_CS_NUM)
	285	return -ENODEV;
	286
f37e4580 ID	287	return gpmc_cs_map & (1 << cs);
	288	}
	289
	290	static unsigned long gpmc_mem_align(unsigned long size)
	291	{
	292	int order;
	293
	294	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	295	order = GPMC_CHUNK_SHIFT - 1;
	296	do {
	297	size >>= 1;
	298	order++;
	299	} while (size);
	300	size = 1 << order;
	301	return size;
	302	}
	303
	304	static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
	305	{
	306	struct resource *res = &gpmc_cs_mem[cs];
	307	int r;
	308
	309	size = gpmc_mem_align(size);
	310	spin_lock(&gpmc_mem_lock);
	311	res->start = base;
	312	res->end = base + size - 1;
	313	r = request_resource(&gpmc_mem_root, res);
	314	spin_unlock(&gpmc_mem_lock);
	315
	316	return r;
	317	}
	318
	319	int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
	320	{
	321	struct resource *res = &gpmc_cs_mem[cs];
	322	int r = -1;
	323
	324	if (cs > GPMC_CS_NUM)
	325	return -ENODEV;
	326
	327	size = gpmc_mem_align(size);
	328	if (size > (1 << GPMC_SECTION_SHIFT))
	329	return -ENOMEM;
	330
	331	spin_lock(&gpmc_mem_lock);
	332	if (gpmc_cs_reserved(cs)) {
	333	r = -EBUSY;
	334	goto out;
	335	}
	336	if (gpmc_cs_mem_enabled(cs))
	337	r = adjust_resource(res, res->start & ~(size - 1), size);
	338	if (r < 0)
	339	r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
	340	size, NULL, NULL);
	341	if (r < 0)
	342	goto out;
	343
	344	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
	345	*base = res->start;
	346	gpmc_cs_set_reserved(cs, 1);
	347	out:
	348	spin_unlock(&gpmc_mem_lock);
	349	return r;
	350	}
351
352	void gpmc_cs_free(int cs)
353	{
354	spin_lock(&gpmc_mem_lock);
355	if (cs >= GPMC_CS_NUM \|\| !gpmc_cs_reserved(cs)) {
356	printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
357	BUG();
358	spin_unlock(&gpmc_mem_lock);
359	return;
360	}
361	gpmc_cs_disable_mem(cs);
362	release_resource(&gpmc_cs_mem[cs]);
363	gpmc_cs_set_reserved(cs, 0);
364	spin_unlock(&gpmc_mem_lock);
365	}
366
367	void __init gpmc_mem_init(void)
368	{
369	int cs;
370	unsigned long boot_rom_space = 0;
371
7f245162 KP	372	/* never allocate the first page, to facilitate bug detection;
	373	* even if we didn't boot from ROM.
	374	*/
	375	boot_rom_space = BOOT_ROM_SPACE;
	376	/* In apollon the CS0 is mapped as 0x0000 0000 */
	377	if (machine_is_omap_apollon())
	378	boot_rom_space = 0;
f37e4580 ID	379	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	380	gpmc_mem_root.end = GPMC_MEM_END;
	381
	382	/* Reserve all regions that has been set up by bootloader */
	383	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
	384	u32 base, size;
	385
	386	if (!gpmc_cs_mem_enabled(cs))
	387	continue;
	388	gpmc_cs_get_memconf(cs, &base, &size);
	389	if (gpmc_cs_insert_mem(cs, base, size) < 0)
	390	BUG();
	391	}
4bbbc1ad JY	392	}
	393
	394	void __init gpmc_init(void)
	395	{
	396	u32 l;
	397
44595982 PW	398	gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
	399	if (IS_ERR(gpmc_fck))
	400	WARN_ON(1);
	401	else
	402	clk_enable(gpmc_fck);
4bbbc1ad JY	403
	404	l = gpmc_read_reg(GPMC_REVISION);
	405	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	406	/* Set smart idle mode and automatic L3 clock gating */
	407	l = gpmc_read_reg(GPMC_SYSCONFIG);
	408	l &= 0x03 << 3;
	409	l \|= (0x02 << 3) \| (1 << 0);
	410	gpmc_write_reg(GPMC_SYSCONFIG, l);
f37e4580 ID	411
f37e4580 ID	412	gpmc_mem_init();
4bbbc1ad	413	}