[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.c

/*
 * GPMC support functions
 *
 * Copyright (C) 2005-2006 Nokia Corporation
 *
 * Author: Juha Yrjola
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/module.h>

#include <asm/mach-types.h>
#include <mach/gpmc.h>

#include <mach/sdrc.h>

/* GPMC register offsets */
#define GPMC_REVISION		0x00
#define GPMC_SYSCONFIG		0x10
#define GPMC_SYSSTATUS		0x14
#define GPMC_IRQSTATUS		0x18
#define GPMC_IRQENABLE		0x1c
#define GPMC_TIMEOUT_CONTROL	0x40
#define GPMC_ERR_ADDRESS	0x44
#define GPMC_ERR_TYPE		0x48
#define GPMC_CONFIG		0x50
#define GPMC_STATUS		0x54
#define GPMC_PREFETCH_CONFIG1	0x1e0
#define GPMC_PREFETCH_CONFIG2	0x1e4
#define GPMC_PREFETCH_CONTROL	0x1ec
#define GPMC_PREFETCH_STATUS	0x1f0
#define GPMC_ECC_CONFIG		0x1f4
#define GPMC_ECC_CONTROL	0x1f8
#define GPMC_ECC_SIZE_CONFIG	0x1fc

#define GPMC_CS0		0x60
#define GPMC_CS_SIZE		0x30

#define GPMC_MEM_START		0x00000000
#define GPMC_MEM_END		0x3FFFFFFF
#define BOOT_ROM_SPACE		0x100000	/* 1MB */

#define GPMC_CHUNK_SHIFT	24		/* 16 MB */
#define GPMC_SECTION_SHIFT	28		/* 128 MB */

static struct resource	gpmc_mem_root;
static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned		gpmc_cs_map;

static void __iomem *gpmc_base;

static struct clk *gpmc_l3_clk;

static void gpmc_write_reg(int idx, u32 val)
{
	__raw_writel(val, gpmc_base + idx);
}

static u32 gpmc_read_reg(int idx)
{
	return __raw_readl(gpmc_base + idx);
}

void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
	void __iomem *reg_addr;

	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
	__raw_writel(val, reg_addr);
}

u32 gpmc_cs_read_reg(int cs, int idx)
{
	void __iomem *reg_addr;

	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
	return __raw_readl(reg_addr);
}

/* TODO: Add support for gpmc_fck to clock framework and use it */
unsigned long gpmc_get_fclk_period(void)
{
	unsigned long rate = clk_get_rate(gpmc_l3_clk);

	if (rate == 0) {
		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
		return 0;
	}

	rate /= 1000;
	rate = 1000000000 / rate;	/* In picoseconds */

	return rate;
}

unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
	unsigned long tick_ps;

	/* Calculate in picosecs to yield more exact results */
	tick_ps = gpmc_get_fclk_period();

	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}

unsigned int gpmc_ticks_to_ns(unsigned int ticks)
{
	return ticks * gpmc_get_fclk_period() / 1000;
}

unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
{
	unsigned long ticks = gpmc_ns_to_ticks(time_ns);

	return ticks * gpmc_get_fclk_period() / 1000;
}

#ifdef DEBUG
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time, const char *name)
#else
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time)
#endif
{
	u32 l;
	int ticks, mask, nr_bits;

	if (time == 0)
		ticks = 0;
	else
		ticks = gpmc_ns_to_ticks(time);
	nr_bits = end_bit - st_bit + 1;
	if (ticks >= 1 << nr_bits) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
				cs, name, time, ticks, 1 << nr_bits);
#endif
		return -1;
	}

	mask = (1 << nr_bits) - 1;
	l = gpmc_cs_read_reg(cs, reg);
#ifdef DEBUG
	printk(KERN_INFO
		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
			(l >> st_bit) & mask, time);
#endif
	l &= ~(mask << st_bit);
	l |= ticks << st_bit;
	gpmc_cs_write_reg(cs, reg, l);

	return 0;
}

#ifdef DEBUG
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
			t->field, #field) < 0)			\
		return -1
#else
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
		return -1
#endif

int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
{
	int div;
	u32 l;

	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	div = l / gpmc_get_fclk_period();
	if (div > 4)
		return -1;
	if (div <= 0)
		div = 1;

	return div;
}

int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
	int div;
	u32 l;

	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	if (div < 0)
		return -1;

	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);

	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);

	if (cpu_is_omap34xx()) {
		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
	}

	/* caller is expected to have initialized CONFIG1 to cover
	 * at least sync vs async
	 */
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
				cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif
		l &= ~0x03;
		l |= (div - 1);
		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	}

	return 0;
}

static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
{
	u32 l;
	u32 mask;

	mask = (1 << GPMC_SECTION_SHIFT) - size;
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~0x3f;
	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	l &= ~(0x0f << 8);
	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	l |= 1 << 6;		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_disable_mem(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~(1 << 6);		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
{
	u32 l;
	u32 mask;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	mask = (l >> 8) & 0x0f;
	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
}

static int gpmc_cs_mem_enabled(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	return l & (1 << 6);
}

int gpmc_cs_set_reserved(int cs, int reserved)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	gpmc_cs_map &= ~(1 << cs);
	gpmc_cs_map |= (reserved ? 1 : 0) << cs;

	return 0;
}

int gpmc_cs_reserved(int cs)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	return gpmc_cs_map & (1 << cs);
}

static unsigned long gpmc_mem_align(unsigned long size)
{
	int order;

	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	order = GPMC_CHUNK_SHIFT - 1;
	do {
		size >>= 1;
		order++;
	} while (size);
	size = 1 << order;
	return size;
}

static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
{
	struct resource	*res = &gpmc_cs_mem[cs];
	int r;

	size = gpmc_mem_align(size);
	spin_lock(&gpmc_mem_lock);
	res->start = base;
	res->end = base + size - 1;
	r = request_resource(&gpmc_mem_root, res);
	spin_unlock(&gpmc_mem_lock);

	return r;
}

int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
	struct resource *res = &gpmc_cs_mem[cs];
	int r = -1;

	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	size = gpmc_mem_align(size);
	if (size > (1 << GPMC_SECTION_SHIFT))
		return -ENOMEM;

	spin_lock(&gpmc_mem_lock);
	if (gpmc_cs_reserved(cs)) {
		r = -EBUSY;
		goto out;
	}
	if (gpmc_cs_mem_enabled(cs))
		r = adjust_resource(res, res->start & ~(size - 1), size);
	if (r < 0)
		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
				      size, NULL, NULL);
	if (r < 0)
		goto out;

	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
	*base = res->start;
	gpmc_cs_set_reserved(cs, 1);
out:
	spin_unlock(&gpmc_mem_lock);
	return r;
}
EXPORT_SYMBOL(gpmc_cs_request);

void gpmc_cs_free(int cs)
{
	spin_lock(&gpmc_mem_lock);
	if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
		BUG();
		spin_unlock(&gpmc_mem_lock);
		return;
	}
	gpmc_cs_disable_mem(cs);
	release_resource(&gpmc_cs_mem[cs]);
	gpmc_cs_set_reserved(cs, 0);
	spin_unlock(&gpmc_mem_lock);
}
EXPORT_SYMBOL(gpmc_cs_free);

static void __init gpmc_mem_init(void)
{
	int cs;
	unsigned long boot_rom_space = 0;

	/* never allocate the first page, to facilitate bug detection;
	 * even if we didn't boot from ROM.
	 */
	boot_rom_space = BOOT_ROM_SPACE;
	/* In apollon the CS0 is mapped as 0x0000 0000 */
	if (machine_is_omap_apollon())
		boot_rom_space = 0;
	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	gpmc_mem_root.end = GPMC_MEM_END;

	/* Reserve all regions that has been set up by bootloader */
	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
		u32 base, size;

		if (!gpmc_cs_mem_enabled(cs))
			continue;
		gpmc_cs_get_memconf(cs, &base, &size);
		if (gpmc_cs_insert_mem(cs, base, size) < 0)
			BUG();
	}
}

void __init gpmc_init(void)
{
	u32 l;
	char *ck;

	if (cpu_is_omap24xx()) {
		ck = "core_l3_ck";
		if (cpu_is_omap2420())
			l = OMAP2420_GPMC_BASE;
		else
			l = OMAP34XX_GPMC_BASE;
	} else if (cpu_is_omap34xx()) {
		ck = "gpmc_fck";
		l = OMAP34XX_GPMC_BASE;
	}

	gpmc_l3_clk = clk_get(NULL, ck);
	if (IS_ERR(gpmc_l3_clk)) {
		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
		return -ENODEV;
	}

	gpmc_base = ioremap(l, SZ_4K);
	if (!gpmc_base) {
		clk_put(gpmc_l3_clk);
		printk(KERN_ERR "Could not get GPMC register memory\n");
		return -ENOMEM;
	}

	BUG_ON(IS_ERR(gpmc_l3_clk));

	l = gpmc_read_reg(GPMC_REVISION);
	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	/* Set smart idle mode and automatic L3 clock gating */
	l = gpmc_read_reg(GPMC_SYSCONFIG);
	l &= 0x03 << 3;
	l |= (0x02 << 3) | (1 << 0);
	gpmc_write_reg(GPMC_SYSCONFIG, l);

	gpmc_mem_init();
}
Commit	Line	Data
4bbbc1ad JY	1	/*
	2	* GPMC support functions
	3	*
	4	* Copyright (C) 2005-2006 Nokia Corporation
	5	*
	6	* Author: Juha Yrjola
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
fd1dc87d PW	12	#undef DEBUG
fd1dc87d PW	13
4bbbc1ad JY	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
f37e4580 ID	18	#include <linux/ioport.h>
f37e4580 ID	19	#include <linux/spinlock.h>
fced80c7	20	#include <linux/io.h>
fd1dc87d	21	#include <linux/module.h>
4bbbc1ad	22
7f245162	23	#include <asm/mach-types.h>
a09e64fb	24	#include <mach/gpmc.h>
4bbbc1ad	25
646e3ed1	26	#include <mach/sdrc.h>
72d0f1c3	27
fd1dc87d	28	/* GPMC register offsets */
4bbbc1ad JY	29	#define GPMC_REVISION 0x00
	30	#define GPMC_SYSCONFIG 0x10
	31	#define GPMC_SYSSTATUS 0x14
	32	#define GPMC_IRQSTATUS 0x18
	33	#define GPMC_IRQENABLE 0x1c
	34	#define GPMC_TIMEOUT_CONTROL 0x40
	35	#define GPMC_ERR_ADDRESS 0x44
	36	#define GPMC_ERR_TYPE 0x48
	37	#define GPMC_CONFIG 0x50
	38	#define GPMC_STATUS 0x54
	39	#define GPMC_PREFETCH_CONFIG1 0x1e0
	40	#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b	41	#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad JY	42	#define GPMC_PREFETCH_STATUS 0x1f0
	43	#define GPMC_ECC_CONFIG 0x1f4
	44	#define GPMC_ECC_CONTROL 0x1f8
	45	#define GPMC_ECC_SIZE_CONFIG 0x1fc
	46
	47	#define GPMC_CS0 0x60
	48	#define GPMC_CS_SIZE 0x30
	49
f37e4580 ID	50	#define GPMC_MEM_START 0x00000000
	51	#define GPMC_MEM_END 0x3FFFFFFF
	52	#define BOOT_ROM_SPACE 0x100000 /* 1MB */
	53
	54	#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
	55	#define GPMC_SECTION_SHIFT 28 /* 128 MB */
	56
	57	static struct resource gpmc_mem_root;
	58	static struct resource gpmc_cs_mem[GPMC_CS_NUM];
87b247c4	59	static DEFINE_SPINLOCK(gpmc_mem_lock);
f37e4580 ID	60	static unsigned gpmc_cs_map;
f37e4580 ID	61
fd1dc87d	62	static void __iomem *gpmc_base;
4bbbc1ad	63
fd1dc87d	64	static struct clk *gpmc_l3_clk;
4bbbc1ad JY	65
	66	static void gpmc_write_reg(int idx, u32 val)
	67	{
	68	__raw_writel(val, gpmc_base + idx);
	69	}
	70
	71	static u32 gpmc_read_reg(int idx)
	72	{
	73	return __raw_readl(gpmc_base + idx);
	74	}
	75
	76	void gpmc_cs_write_reg(int cs, int idx, u32 val)
	77	{
	78	void __iomem *reg_addr;
	79
fd1dc87d	80	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
4bbbc1ad JY	81	__raw_writel(val, reg_addr);
	82	}
	83
	84	u32 gpmc_cs_read_reg(int cs, int idx)
	85	{
fd1dc87d PW	86	void __iomem *reg_addr;
	87
	88	reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
	89	return __raw_readl(reg_addr);
4bbbc1ad JY	90	}
4bbbc1ad JY	91
fd1dc87d	92	/* TODO: Add support for gpmc_fck to clock framework and use it */
1c22cc13	93	unsigned long gpmc_get_fclk_period(void)
4bbbc1ad	94	{
fd1dc87d PW	95	unsigned long rate = clk_get_rate(gpmc_l3_clk);
	96
	97	if (rate == 0) {
	98	printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
	99	return 0;
	100	}
	101
	102	rate /= 1000;
	103	rate = 1000000000 / rate; /* In picoseconds */
	104
	105	return rate;
4bbbc1ad JY	106	}
	107
	108	unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
	109	{
	110	unsigned long tick_ps;
	111
	112	/* Calculate in picosecs to yield more exact results */
	113	tick_ps = gpmc_get_fclk_period();
	114
	115	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
	116	}
	117
fd1dc87d PW	118	unsigned int gpmc_ticks_to_ns(unsigned int ticks)
	119	{
	120	return ticks * gpmc_get_fclk_period() / 1000;
	121	}
	122
23300597 KS	123	unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
	124	{
	125	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
	126
	127	return ticks * gpmc_get_fclk_period() / 1000;
	128	}
	129
4bbbc1ad JY	130	#ifdef DEBUG
4bbbc1ad JY	131	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468	132	int time, const char *name)
4bbbc1ad JY	133	#else
	134	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
	135	int time)
	136	#endif
	137	{
	138	u32 l;
	139	int ticks, mask, nr_bits;
	140
	141	if (time == 0)
	142	ticks = 0;
	143	else
	144	ticks = gpmc_ns_to_ticks(time);
	145	nr_bits = end_bit - st_bit + 1;
1c22cc13 DB	146	if (ticks >= 1 << nr_bits) {
	147	#ifdef DEBUG
	148	printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
	149	cs, name, time, ticks, 1 << nr_bits);
	150	#endif
4bbbc1ad	151	return -1;
1c22cc13	152	}
4bbbc1ad JY	153
	154	mask = (1 << nr_bits) - 1;
	155	l = gpmc_cs_read_reg(cs, reg);
	156	#ifdef DEBUG
1c22cc13 DB	157	printk(KERN_INFO
1c22cc13 DB	158	"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
2aab6468	159	cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
1c22cc13	160	(l >> st_bit) & mask, time);
4bbbc1ad JY	161	#endif
	162	l &= ~(mask << st_bit);
	163	l \|= ticks << st_bit;
	164	gpmc_cs_write_reg(cs, reg, l);
	165
	166	return 0;
	167	}
	168
	169	#ifdef DEBUG
	170	#define GPMC_SET_ONE(reg, st, end, field) \
	171	if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
	172	t->field, #field) < 0) \
	173	return -1
	174	#else
	175	#define GPMC_SET_ONE(reg, st, end, field) \
	176	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
	177	return -1
	178	#endif
	179
	180	int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
	181	{
	182	int div;
	183	u32 l;
	184
	185	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	186	div = l / gpmc_get_fclk_period();
	187	if (div > 4)
	188	return -1;
1c22cc13	189	if (div <= 0)
4bbbc1ad JY	190	div = 1;
	191
	192	return div;
	193	}
	194
	195	int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
	196	{
	197	int div;
	198	u32 l;
	199
	200	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	201	if (div < 0)
	202	return -1;
	203
	204	GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
	205	GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
	206	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
	207
	208	GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
	209	GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
	210	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
	211
	212	GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
	213	GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
	214	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	215	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
	216
	217	GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
	218	GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
	219	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
	220
	221	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
	222
cc26b3b0 SMK	223	if (cpu_is_omap34xx()) {
	224	GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
	225	GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
	226	}
	227
1c22cc13 DB	228	/* caller is expected to have initialized CONFIG1 to cover
	229	* at least sync vs async
	230	*/
	231	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	232	if (l & (GPMC_CONFIG1_READTYPE_SYNC \| GPMC_CONFIG1_WRITETYPE_SYNC)) {
4bbbc1ad	233	#ifdef DEBUG
1c22cc13 DB	234	printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
1c22cc13 DB	235	cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad	236	#endif
1c22cc13 DB	237	l &= ~0x03;
	238	l \|= (div - 1);
	239	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	240	}
4bbbc1ad JY	241
	242	return 0;
	243	}
	244
f37e4580 ID	245	static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
	246	{
	247	u32 l;
	248	u32 mask;
	249
	250	mask = (1 << GPMC_SECTION_SHIFT) - size;
	251	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	252	l &= ~0x3f;
	253	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	254	l &= ~(0x0f << 8);
	255	l \|= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	256	l \|= 1 << 6; /* CSVALID */
	257	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	258	}
	259
	260	static void gpmc_cs_disable_mem(int cs)
	261	{
	262	u32 l;
	263
	264	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	265	l &= ~(1 << 6); /* CSVALID */
	266	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	267	}
	268
	269	static void gpmc_cs_get_memconf(int cs, u32 base, u32 size)
	270	{
	271	u32 l;
	272	u32 mask;
	273
	274	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	275	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	276	mask = (l >> 8) & 0x0f;
	277	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
	278	}
	279
	280	static int gpmc_cs_mem_enabled(int cs)
	281	{
	282	u32 l;
	283
	284	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	285	return l & (1 << 6);
	286	}
	287
c40fae95	288	int gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad	289	{
c40fae95 TL	290	if (cs > GPMC_CS_NUM)
	291	return -ENODEV;
	292
f37e4580 ID	293	gpmc_cs_map &= ~(1 << cs);
f37e4580 ID	294	gpmc_cs_map \|= (reserved ? 1 : 0) << cs;
c40fae95 TL	295
c40fae95 TL	296	return 0;
f37e4580 ID	297	}
f37e4580 ID	298
c40fae95	299	int gpmc_cs_reserved(int cs)
f37e4580	300	{
c40fae95 TL	301	if (cs > GPMC_CS_NUM)
	302	return -ENODEV;
	303
f37e4580 ID	304	return gpmc_cs_map & (1 << cs);
	305	}
	306
	307	static unsigned long gpmc_mem_align(unsigned long size)
	308	{
	309	int order;
	310
	311	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	312	order = GPMC_CHUNK_SHIFT - 1;
	313	do {
	314	size >>= 1;
	315	order++;
	316	} while (size);
	317	size = 1 << order;
	318	return size;
	319	}
	320
	321	static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
	322	{
	323	struct resource *res = &gpmc_cs_mem[cs];
	324	int r;
	325
	326	size = gpmc_mem_align(size);
	327	spin_lock(&gpmc_mem_lock);
	328	res->start = base;
	329	res->end = base + size - 1;
	330	r = request_resource(&gpmc_mem_root, res);
	331	spin_unlock(&gpmc_mem_lock);
	332
	333	return r;
	334	}
	335
	336	int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
	337	{
	338	struct resource *res = &gpmc_cs_mem[cs];
	339	int r = -1;
	340
	341	if (cs > GPMC_CS_NUM)
	342	return -ENODEV;
	343
	344	size = gpmc_mem_align(size);
	345	if (size > (1 << GPMC_SECTION_SHIFT))
	346	return -ENOMEM;
	347
	348	spin_lock(&gpmc_mem_lock);
	349	if (gpmc_cs_reserved(cs)) {
	350	r = -EBUSY;
	351	goto out;
	352	}
	353	if (gpmc_cs_mem_enabled(cs))
	354	r = adjust_resource(res, res->start & ~(size - 1), size);
	355	if (r < 0)
	356	r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
	357	size, NULL, NULL);
	358	if (r < 0)
	359	goto out;
	360
	361	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
	362	*base = res->start;
	363	gpmc_cs_set_reserved(cs, 1);
	364	out:
	365	spin_unlock(&gpmc_mem_lock);
	366	return r;
	367	}
fd1dc87d	368	EXPORT_SYMBOL(gpmc_cs_request);
f37e4580 ID	369
	370	void gpmc_cs_free(int cs)
	371	{
	372	spin_lock(&gpmc_mem_lock);
	373	if (cs >= GPMC_CS_NUM \|\| !gpmc_cs_reserved(cs)) {
	374	printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
	375	BUG();
	376	spin_unlock(&gpmc_mem_lock);
	377	return;
	378	}
	379	gpmc_cs_disable_mem(cs);
	380	release_resource(&gpmc_cs_mem[cs]);
	381	gpmc_cs_set_reserved(cs, 0);
	382	spin_unlock(&gpmc_mem_lock);
	383	}
fd1dc87d	384	EXPORT_SYMBOL(gpmc_cs_free);
f37e4580	385
fd1dc87d	386	static void __init gpmc_mem_init(void)
f37e4580 ID	387	{
	388	int cs;
	389	unsigned long boot_rom_space = 0;
	390
7f245162 KP	391	/* never allocate the first page, to facilitate bug detection;
	392	* even if we didn't boot from ROM.
	393	*/
	394	boot_rom_space = BOOT_ROM_SPACE;
	395	/* In apollon the CS0 is mapped as 0x0000 0000 */
	396	if (machine_is_omap_apollon())
	397	boot_rom_space = 0;
f37e4580 ID	398	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	399	gpmc_mem_root.end = GPMC_MEM_END;
	400
	401	/* Reserve all regions that has been set up by bootloader */
	402	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
	403	u32 base, size;
	404
	405	if (!gpmc_cs_mem_enabled(cs))
	406	continue;
	407	gpmc_cs_get_memconf(cs, &base, &size);
	408	if (gpmc_cs_insert_mem(cs, base, size) < 0)
	409	BUG();
	410	}
4bbbc1ad JY	411	}
	412
	413	void __init gpmc_init(void)
	414	{
	415	u32 l;
fd1dc87d PW	416	char *ck;
	417
	418	if (cpu_is_omap24xx()) {
	419	ck = "core_l3_ck";
	420	if (cpu_is_omap2420())
	421	l = OMAP2420_GPMC_BASE;
	422	else
	423	l = OMAP34XX_GPMC_BASE;
	424	} else if (cpu_is_omap34xx()) {
	425	ck = "gpmc_fck";
	426	l = OMAP34XX_GPMC_BASE;
	427	}
4bbbc1ad	428
fd1dc87d PW	429	gpmc_l3_clk = clk_get(NULL, ck);
	430	if (IS_ERR(gpmc_l3_clk)) {
	431	printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
	432	return -ENODEV;
	433	}
	434
	435	gpmc_base = ioremap(l, SZ_4K);
	436	if (!gpmc_base) {
	437	clk_put(gpmc_l3_clk);
	438	printk(KERN_ERR "Could not get GPMC register memory\n");
	439	return -ENOMEM;
	440	}
	441
	442	BUG_ON(IS_ERR(gpmc_l3_clk));
4bbbc1ad JY	443
	444	l = gpmc_read_reg(GPMC_REVISION);
	445	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	446	/* Set smart idle mode and automatic L3 clock gating */
	447	l = gpmc_read_reg(GPMC_SYSCONFIG);
	448	l &= 0x03 << 3;
	449	l \|= (0x02 << 3) \| (1 << 0);
	450	gpmc_write_reg(GPMC_SYSCONFIG, l);
f37e4580 ID	451
f37e4580 ID	452	gpmc_mem_init();
4bbbc1ad	453	}