Commit | Line | Data |
---|---|---|
4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
db97eb7d | 17 | #include <linux/irq.h> |
4bbbc1ad JY |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
f37e4580 ID |
22 | #include <linux/ioport.h> |
23 | #include <linux/spinlock.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fd1dc87d | 25 | #include <linux/module.h> |
db97eb7d | 26 | #include <linux/interrupt.h> |
4bbbc1ad | 27 | |
7f245162 | 28 | #include <asm/mach-types.h> |
ce491cf8 | 29 | #include <plat/gpmc.h> |
4bbbc1ad | 30 | |
ce491cf8 | 31 | #include <plat/sdrc.h> |
72d0f1c3 | 32 | |
fd1dc87d | 33 | /* GPMC register offsets */ |
4bbbc1ad JY |
34 | #define GPMC_REVISION 0x00 |
35 | #define GPMC_SYSCONFIG 0x10 | |
36 | #define GPMC_SYSSTATUS 0x14 | |
37 | #define GPMC_IRQSTATUS 0x18 | |
38 | #define GPMC_IRQENABLE 0x1c | |
39 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
40 | #define GPMC_ERR_ADDRESS 0x44 | |
41 | #define GPMC_ERR_TYPE 0x48 | |
42 | #define GPMC_CONFIG 0x50 | |
43 | #define GPMC_STATUS 0x54 | |
44 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
45 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 46 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
47 | #define GPMC_PREFETCH_STATUS 0x1f0 |
48 | #define GPMC_ECC_CONFIG 0x1f4 | |
49 | #define GPMC_ECC_CONTROL 0x1f8 | |
50 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 51 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 52 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
4bbbc1ad | 53 | |
2c65e744 YY |
54 | /* GPMC ECC control settings */ |
55 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
56 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
57 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
58 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
59 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
60 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
61 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
62 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
63 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
64 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
65 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
66 | ||
948d38e7 | 67 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad JY |
68 | #define GPMC_CS_SIZE 0x30 |
69 | ||
f37e4580 ID |
70 | #define GPMC_MEM_START 0x00000000 |
71 | #define GPMC_MEM_END 0x3FFFFFFF | |
72 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | |
73 | ||
74 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
75 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
76 | ||
59e9c5ae | 77 | #define CS_NUM_SHIFT 24 |
78 | #define ENABLE_PREFETCH (0x1 << 7) | |
79 | #define DMA_MPU_MODE 2 | |
80 | ||
6b6c32fc AM |
81 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
82 | */ | |
83 | #define GPMC_NR_IRQ 2 | |
84 | ||
85 | struct gpmc_client_irq { | |
86 | unsigned irq; | |
87 | u32 bitmask; | |
88 | }; | |
89 | ||
a2d3e7ba RN |
90 | /* Structure to save gpmc cs context */ |
91 | struct gpmc_cs_config { | |
92 | u32 config1; | |
93 | u32 config2; | |
94 | u32 config3; | |
95 | u32 config4; | |
96 | u32 config5; | |
97 | u32 config6; | |
98 | u32 config7; | |
99 | int is_valid; | |
100 | }; | |
101 | ||
102 | /* | |
103 | * Structure to save/restore gpmc context | |
104 | * to support core off on OMAP3 | |
105 | */ | |
106 | struct omap3_gpmc_regs { | |
107 | u32 sysconfig; | |
108 | u32 irqenable; | |
109 | u32 timeout_ctrl; | |
110 | u32 config; | |
111 | u32 prefetch_config1; | |
112 | u32 prefetch_config2; | |
113 | u32 prefetch_control; | |
114 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
115 | }; | |
116 | ||
6b6c32fc AM |
117 | static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; |
118 | static struct irq_chip gpmc_irq_chip; | |
119 | static unsigned gpmc_irq_start; | |
120 | ||
f37e4580 ID |
121 | static struct resource gpmc_mem_root; |
122 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 123 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
948d38e7 SG |
124 | static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ |
125 | static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ | |
f37e4580 | 126 | |
fd1dc87d | 127 | static void __iomem *gpmc_base; |
4bbbc1ad | 128 | |
fd1dc87d | 129 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 130 | |
db97eb7d SG |
131 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
132 | ||
4bbbc1ad JY |
133 | static void gpmc_write_reg(int idx, u32 val) |
134 | { | |
135 | __raw_writel(val, gpmc_base + idx); | |
136 | } | |
137 | ||
138 | static u32 gpmc_read_reg(int idx) | |
139 | { | |
140 | return __raw_readl(gpmc_base + idx); | |
141 | } | |
142 | ||
948d38e7 SG |
143 | static void gpmc_cs_write_byte(int cs, int idx, u8 val) |
144 | { | |
145 | void __iomem *reg_addr; | |
146 | ||
147 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | |
148 | __raw_writeb(val, reg_addr); | |
149 | } | |
150 | ||
151 | static u8 gpmc_cs_read_byte(int cs, int idx) | |
152 | { | |
153 | void __iomem *reg_addr; | |
154 | ||
155 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | |
156 | return __raw_readb(reg_addr); | |
157 | } | |
158 | ||
4bbbc1ad JY |
159 | void gpmc_cs_write_reg(int cs, int idx, u32 val) |
160 | { | |
161 | void __iomem *reg_addr; | |
162 | ||
948d38e7 | 163 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
4bbbc1ad JY |
164 | __raw_writel(val, reg_addr); |
165 | } | |
166 | ||
167 | u32 gpmc_cs_read_reg(int cs, int idx) | |
168 | { | |
fd1dc87d PW |
169 | void __iomem *reg_addr; |
170 | ||
948d38e7 | 171 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
fd1dc87d | 172 | return __raw_readl(reg_addr); |
4bbbc1ad JY |
173 | } |
174 | ||
fd1dc87d | 175 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
1c22cc13 | 176 | unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 177 | { |
fd1dc87d PW |
178 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
179 | ||
180 | if (rate == 0) { | |
181 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
182 | return 0; | |
183 | } | |
184 | ||
185 | rate /= 1000; | |
186 | rate = 1000000000 / rate; /* In picoseconds */ | |
187 | ||
188 | return rate; | |
4bbbc1ad JY |
189 | } |
190 | ||
191 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |
192 | { | |
193 | unsigned long tick_ps; | |
194 | ||
195 | /* Calculate in picosecs to yield more exact results */ | |
196 | tick_ps = gpmc_get_fclk_period(); | |
197 | ||
198 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
199 | } | |
200 | ||
a3551f5b AH |
201 | unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
202 | { | |
203 | unsigned long tick_ps; | |
204 | ||
205 | /* Calculate in picosecs to yield more exact results */ | |
206 | tick_ps = gpmc_get_fclk_period(); | |
207 | ||
208 | return (time_ps + tick_ps - 1) / tick_ps; | |
209 | } | |
210 | ||
fd1dc87d PW |
211 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
212 | { | |
213 | return ticks * gpmc_get_fclk_period() / 1000; | |
214 | } | |
215 | ||
23300597 KS |
216 | unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) |
217 | { | |
218 | unsigned long ticks = gpmc_ns_to_ticks(time_ns); | |
219 | ||
220 | return ticks * gpmc_get_fclk_period() / 1000; | |
221 | } | |
222 | ||
4bbbc1ad JY |
223 | #ifdef DEBUG |
224 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
2aab6468 | 225 | int time, const char *name) |
4bbbc1ad JY |
226 | #else |
227 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
228 | int time) | |
229 | #endif | |
230 | { | |
231 | u32 l; | |
232 | int ticks, mask, nr_bits; | |
233 | ||
234 | if (time == 0) | |
235 | ticks = 0; | |
236 | else | |
237 | ticks = gpmc_ns_to_ticks(time); | |
238 | nr_bits = end_bit - st_bit + 1; | |
1c22cc13 DB |
239 | if (ticks >= 1 << nr_bits) { |
240 | #ifdef DEBUG | |
241 | printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", | |
242 | cs, name, time, ticks, 1 << nr_bits); | |
243 | #endif | |
4bbbc1ad | 244 | return -1; |
1c22cc13 | 245 | } |
4bbbc1ad JY |
246 | |
247 | mask = (1 << nr_bits) - 1; | |
248 | l = gpmc_cs_read_reg(cs, reg); | |
249 | #ifdef DEBUG | |
1c22cc13 DB |
250 | printk(KERN_INFO |
251 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 252 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 253 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
254 | #endif |
255 | l &= ~(mask << st_bit); | |
256 | l |= ticks << st_bit; | |
257 | gpmc_cs_write_reg(cs, reg, l); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | #ifdef DEBUG | |
263 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
264 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
265 | t->field, #field) < 0) \ | |
266 | return -1 | |
267 | #else | |
268 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
269 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
270 | return -1 | |
271 | #endif | |
272 | ||
273 | int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) | |
274 | { | |
275 | int div; | |
276 | u32 l; | |
277 | ||
a3551f5b | 278 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
4bbbc1ad JY |
279 | div = l / gpmc_get_fclk_period(); |
280 | if (div > 4) | |
281 | return -1; | |
1c22cc13 | 282 | if (div <= 0) |
4bbbc1ad JY |
283 | div = 1; |
284 | ||
285 | return div; | |
286 | } | |
287 | ||
288 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
289 | { | |
290 | int div; | |
291 | u32 l; | |
292 | ||
293 | div = gpmc_cs_calc_divider(cs, t->sync_clk); | |
294 | if (div < 0) | |
295 | return -1; | |
296 | ||
297 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
298 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
299 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
300 | ||
301 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
302 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
303 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
304 | ||
305 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
306 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
307 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
308 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
309 | ||
310 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
311 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
312 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
313 | ||
314 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
315 | ||
cc26b3b0 SMK |
316 | if (cpu_is_omap34xx()) { |
317 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); | |
318 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); | |
319 | } | |
320 | ||
1c22cc13 DB |
321 | /* caller is expected to have initialized CONFIG1 to cover |
322 | * at least sync vs async | |
323 | */ | |
324 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
325 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 326 | #ifdef DEBUG |
1c22cc13 DB |
327 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
328 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 329 | #endif |
1c22cc13 DB |
330 | l &= ~0x03; |
331 | l |= (div - 1); | |
332 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
333 | } | |
4bbbc1ad JY |
334 | |
335 | return 0; | |
336 | } | |
337 | ||
f37e4580 ID |
338 | static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
339 | { | |
340 | u32 l; | |
341 | u32 mask; | |
342 | ||
343 | mask = (1 << GPMC_SECTION_SHIFT) - size; | |
344 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
345 | l &= ~0x3f; | |
346 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
347 | l &= ~(0x0f << 8); | |
348 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 349 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
350 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
351 | } | |
352 | ||
353 | static void gpmc_cs_disable_mem(int cs) | |
354 | { | |
355 | u32 l; | |
356 | ||
357 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 358 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
359 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
360 | } | |
361 | ||
362 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
363 | { | |
364 | u32 l; | |
365 | u32 mask; | |
366 | ||
367 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
368 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
369 | mask = (l >> 8) & 0x0f; | |
370 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
371 | } | |
372 | ||
373 | static int gpmc_cs_mem_enabled(int cs) | |
374 | { | |
375 | u32 l; | |
376 | ||
377 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 378 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
379 | } |
380 | ||
c40fae95 | 381 | int gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 382 | { |
c40fae95 TL |
383 | if (cs > GPMC_CS_NUM) |
384 | return -ENODEV; | |
385 | ||
f37e4580 ID |
386 | gpmc_cs_map &= ~(1 << cs); |
387 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
c40fae95 TL |
388 | |
389 | return 0; | |
f37e4580 ID |
390 | } |
391 | ||
c40fae95 | 392 | int gpmc_cs_reserved(int cs) |
f37e4580 | 393 | { |
c40fae95 TL |
394 | if (cs > GPMC_CS_NUM) |
395 | return -ENODEV; | |
396 | ||
f37e4580 ID |
397 | return gpmc_cs_map & (1 << cs); |
398 | } | |
399 | ||
400 | static unsigned long gpmc_mem_align(unsigned long size) | |
401 | { | |
402 | int order; | |
403 | ||
404 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
405 | order = GPMC_CHUNK_SHIFT - 1; | |
406 | do { | |
407 | size >>= 1; | |
408 | order++; | |
409 | } while (size); | |
410 | size = 1 << order; | |
411 | return size; | |
412 | } | |
413 | ||
414 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
415 | { | |
416 | struct resource *res = &gpmc_cs_mem[cs]; | |
417 | int r; | |
418 | ||
419 | size = gpmc_mem_align(size); | |
420 | spin_lock(&gpmc_mem_lock); | |
421 | res->start = base; | |
422 | res->end = base + size - 1; | |
423 | r = request_resource(&gpmc_mem_root, res); | |
424 | spin_unlock(&gpmc_mem_lock); | |
425 | ||
426 | return r; | |
427 | } | |
428 | ||
429 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) | |
430 | { | |
431 | struct resource *res = &gpmc_cs_mem[cs]; | |
432 | int r = -1; | |
433 | ||
434 | if (cs > GPMC_CS_NUM) | |
435 | return -ENODEV; | |
436 | ||
437 | size = gpmc_mem_align(size); | |
438 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
439 | return -ENOMEM; | |
440 | ||
441 | spin_lock(&gpmc_mem_lock); | |
442 | if (gpmc_cs_reserved(cs)) { | |
443 | r = -EBUSY; | |
444 | goto out; | |
445 | } | |
446 | if (gpmc_cs_mem_enabled(cs)) | |
447 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
448 | if (r < 0) | |
449 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
450 | size, NULL, NULL); | |
451 | if (r < 0) | |
452 | goto out; | |
453 | ||
6d135242 | 454 | gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
f37e4580 ID |
455 | *base = res->start; |
456 | gpmc_cs_set_reserved(cs, 1); | |
457 | out: | |
458 | spin_unlock(&gpmc_mem_lock); | |
459 | return r; | |
460 | } | |
fd1dc87d | 461 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
462 | |
463 | void gpmc_cs_free(int cs) | |
464 | { | |
465 | spin_lock(&gpmc_mem_lock); | |
e7fdc605 | 466 | if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
467 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
468 | BUG(); | |
469 | spin_unlock(&gpmc_mem_lock); | |
470 | return; | |
471 | } | |
472 | gpmc_cs_disable_mem(cs); | |
473 | release_resource(&gpmc_cs_mem[cs]); | |
474 | gpmc_cs_set_reserved(cs, 0); | |
475 | spin_unlock(&gpmc_mem_lock); | |
476 | } | |
fd1dc87d | 477 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 478 | |
948d38e7 SG |
479 | /** |
480 | * gpmc_read_status - read access request to get the different gpmc status | |
481 | * @cmd: command type | |
482 | * @return status | |
483 | */ | |
484 | int gpmc_read_status(int cmd) | |
485 | { | |
486 | int status = -EINVAL; | |
487 | u32 regval = 0; | |
488 | ||
489 | switch (cmd) { | |
490 | case GPMC_GET_IRQ_STATUS: | |
491 | status = gpmc_read_reg(GPMC_IRQSTATUS); | |
492 | break; | |
493 | ||
494 | case GPMC_PREFETCH_FIFO_CNT: | |
495 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | |
496 | status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); | |
497 | break; | |
498 | ||
499 | case GPMC_PREFETCH_COUNT: | |
500 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | |
501 | status = GPMC_PREFETCH_STATUS_COUNT(regval); | |
502 | break; | |
503 | ||
504 | case GPMC_STATUS_BUFFER: | |
505 | regval = gpmc_read_reg(GPMC_STATUS); | |
506 | /* 1 : buffer is available to write */ | |
507 | status = regval & GPMC_STATUS_BUFF_EMPTY; | |
508 | break; | |
509 | ||
510 | default: | |
511 | printk(KERN_ERR "gpmc_read_status: Not supported\n"); | |
512 | } | |
513 | return status; | |
514 | } | |
515 | EXPORT_SYMBOL(gpmc_read_status); | |
516 | ||
517 | /** | |
518 | * gpmc_cs_configure - write request to configure gpmc | |
519 | * @cs: chip select number | |
520 | * @cmd: command type | |
521 | * @wval: value to write | |
522 | * @return status of the operation | |
523 | */ | |
524 | int gpmc_cs_configure(int cs, int cmd, int wval) | |
525 | { | |
526 | int err = 0; | |
527 | u32 regval = 0; | |
528 | ||
529 | switch (cmd) { | |
db97eb7d SG |
530 | case GPMC_ENABLE_IRQ: |
531 | gpmc_write_reg(GPMC_IRQENABLE, wval); | |
532 | break; | |
533 | ||
948d38e7 SG |
534 | case GPMC_SET_IRQ_STATUS: |
535 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
536 | break; | |
537 | ||
538 | case GPMC_CONFIG_WP: | |
539 | regval = gpmc_read_reg(GPMC_CONFIG); | |
540 | if (wval) | |
541 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
542 | else | |
543 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
544 | gpmc_write_reg(GPMC_CONFIG, regval); | |
545 | break; | |
546 | ||
547 | case GPMC_CONFIG_RDY_BSY: | |
548 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
549 | if (wval) | |
550 | regval |= WR_RD_PIN_MONITORING; | |
551 | else | |
552 | regval &= ~WR_RD_PIN_MONITORING; | |
553 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
554 | break; | |
555 | ||
556 | case GPMC_CONFIG_DEV_SIZE: | |
557 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
8ef5d844 YY |
558 | |
559 | /* clear 2 target bits */ | |
560 | regval &= ~GPMC_CONFIG1_DEVICESIZE(3); | |
561 | ||
562 | /* set the proper value */ | |
948d38e7 | 563 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); |
8ef5d844 | 564 | |
948d38e7 SG |
565 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); |
566 | break; | |
567 | ||
568 | case GPMC_CONFIG_DEV_TYPE: | |
569 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
570 | regval |= GPMC_CONFIG1_DEVICETYPE(wval); | |
571 | if (wval == GPMC_DEVICETYPE_NOR) | |
572 | regval |= GPMC_CONFIG1_MUXADDDATA; | |
573 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
574 | break; | |
575 | ||
576 | default: | |
577 | printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); | |
578 | err = -EINVAL; | |
579 | } | |
580 | ||
581 | return err; | |
582 | } | |
583 | EXPORT_SYMBOL(gpmc_cs_configure); | |
584 | ||
585 | /** | |
586 | * gpmc_nand_read - nand specific read access request | |
587 | * @cs: chip select number | |
588 | * @cmd: command type | |
589 | */ | |
590 | int gpmc_nand_read(int cs, int cmd) | |
591 | { | |
592 | int rval = -EINVAL; | |
593 | ||
594 | switch (cmd) { | |
595 | case GPMC_NAND_DATA: | |
596 | rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA); | |
597 | break; | |
598 | ||
599 | default: | |
600 | printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n"); | |
601 | } | |
602 | return rval; | |
603 | } | |
604 | EXPORT_SYMBOL(gpmc_nand_read); | |
605 | ||
606 | /** | |
607 | * gpmc_nand_write - nand specific write request | |
608 | * @cs: chip select number | |
609 | * @cmd: command type | |
610 | * @wval: value to write | |
611 | */ | |
612 | int gpmc_nand_write(int cs, int cmd, int wval) | |
613 | { | |
614 | int err = 0; | |
615 | ||
616 | switch (cmd) { | |
617 | case GPMC_NAND_COMMAND: | |
618 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval); | |
619 | break; | |
620 | ||
621 | case GPMC_NAND_ADDRESS: | |
622 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval); | |
623 | break; | |
624 | ||
625 | case GPMC_NAND_DATA: | |
626 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval); | |
627 | ||
628 | default: | |
629 | printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n"); | |
630 | err = -EINVAL; | |
631 | } | |
632 | return err; | |
633 | } | |
634 | EXPORT_SYMBOL(gpmc_nand_write); | |
635 | ||
636 | ||
637 | ||
59e9c5ae | 638 | /** |
639 | * gpmc_prefetch_enable - configures and starts prefetch transfer | |
948d38e7 | 640 | * @cs: cs (chip select) number |
317379a9 | 641 | * @fifo_th: fifo threshold to be used for read/ write |
59e9c5ae | 642 | * @dma_mode: dma mode enable (1) or disable (0) |
643 | * @u32_count: number of bytes to be transferred | |
644 | * @is_write: prefetch read(0) or write post(1) mode | |
645 | */ | |
317379a9 | 646 | int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, |
59e9c5ae | 647 | unsigned int u32_count, int is_write) |
648 | { | |
59e9c5ae | 649 | |
317379a9 SG |
650 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { |
651 | pr_err("gpmc: fifo threshold is not supported\n"); | |
652 | return -1; | |
653 | } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { | |
59e9c5ae | 654 | /* Set the amount of bytes to be prefetched */ |
655 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); | |
656 | ||
657 | /* Set dma/mpu mode, the prefetch read / post write and | |
658 | * enable the engine. Set which cs is has requested for. | |
659 | */ | |
948d38e7 | 660 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | |
317379a9 | 661 | PREFETCH_FIFOTHRESHOLD(fifo_th) | |
59e9c5ae | 662 | ENABLE_PREFETCH | |
663 | (dma_mode << DMA_MPU_MODE) | | |
948d38e7 SG |
664 | (0x1 & is_write))); |
665 | ||
666 | /* Start the prefetch engine */ | |
667 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); | |
59e9c5ae | 668 | } else { |
669 | return -EBUSY; | |
670 | } | |
59e9c5ae | 671 | |
672 | return 0; | |
673 | } | |
674 | EXPORT_SYMBOL(gpmc_prefetch_enable); | |
675 | ||
676 | /** | |
677 | * gpmc_prefetch_reset - disables and stops the prefetch engine | |
678 | */ | |
948d38e7 | 679 | int gpmc_prefetch_reset(int cs) |
59e9c5ae | 680 | { |
948d38e7 SG |
681 | u32 config1; |
682 | ||
683 | /* check if the same module/cs is trying to reset */ | |
684 | config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
685 | if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) | |
686 | return -EINVAL; | |
687 | ||
59e9c5ae | 688 | /* Stop the PFPW engine */ |
689 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); | |
690 | ||
691 | /* Reset/disable the PFPW engine */ | |
692 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); | |
948d38e7 SG |
693 | |
694 | return 0; | |
59e9c5ae | 695 | } |
696 | EXPORT_SYMBOL(gpmc_prefetch_reset); | |
697 | ||
52bd138d AM |
698 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
699 | { | |
700 | reg->gpmc_status = gpmc_base + GPMC_STATUS; | |
701 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | |
702 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
703 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
704 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
705 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
706 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
707 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
708 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
709 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
710 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
711 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
712 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
713 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
714 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
715 | reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; | |
716 | } | |
717 | ||
6b6c32fc AM |
718 | int gpmc_get_client_irq(unsigned irq_config) |
719 | { | |
720 | int i; | |
721 | ||
722 | if (hweight32(irq_config) > 1) | |
723 | return 0; | |
724 | ||
725 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
726 | if (gpmc_client_irq[i].bitmask & irq_config) | |
727 | return gpmc_client_irq[i].irq; | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
732 | static int gpmc_irq_endis(unsigned irq, bool endis) | |
733 | { | |
734 | int i; | |
735 | u32 regval; | |
736 | ||
737 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
738 | if (irq == gpmc_client_irq[i].irq) { | |
739 | regval = gpmc_read_reg(GPMC_IRQENABLE); | |
740 | if (endis) | |
741 | regval |= gpmc_client_irq[i].bitmask; | |
742 | else | |
743 | regval &= ~gpmc_client_irq[i].bitmask; | |
744 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
745 | break; | |
746 | } | |
747 | ||
748 | return 0; | |
749 | } | |
750 | ||
751 | static void gpmc_irq_disable(struct irq_data *p) | |
752 | { | |
753 | gpmc_irq_endis(p->irq, false); | |
754 | } | |
755 | ||
756 | static void gpmc_irq_enable(struct irq_data *p) | |
757 | { | |
758 | gpmc_irq_endis(p->irq, true); | |
759 | } | |
760 | ||
761 | static void gpmc_irq_noop(struct irq_data *data) { } | |
762 | ||
763 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | |
764 | ||
765 | static int gpmc_setup_irq(int gpmc_irq) | |
766 | { | |
767 | int i; | |
768 | u32 regval; | |
769 | ||
770 | if (!gpmc_irq) | |
771 | return -EINVAL; | |
772 | ||
773 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | |
774 | if (IS_ERR_VALUE(gpmc_irq_start)) { | |
775 | pr_err("irq_alloc_descs failed\n"); | |
776 | return gpmc_irq_start; | |
777 | } | |
778 | ||
779 | gpmc_irq_chip.name = "gpmc"; | |
780 | gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; | |
781 | gpmc_irq_chip.irq_enable = gpmc_irq_enable; | |
782 | gpmc_irq_chip.irq_disable = gpmc_irq_disable; | |
783 | gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; | |
784 | gpmc_irq_chip.irq_ack = gpmc_irq_noop; | |
785 | gpmc_irq_chip.irq_mask = gpmc_irq_noop; | |
786 | gpmc_irq_chip.irq_unmask = gpmc_irq_noop; | |
787 | ||
788 | gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; | |
789 | gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; | |
790 | ||
791 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
792 | gpmc_client_irq[i].irq = gpmc_irq_start + i; | |
793 | irq_set_chip_and_handler(gpmc_client_irq[i].irq, | |
794 | &gpmc_irq_chip, handle_simple_irq); | |
795 | set_irq_flags(gpmc_client_irq[i].irq, | |
796 | IRQF_VALID | IRQF_NOAUTOEN); | |
797 | } | |
798 | ||
799 | /* Disable interrupts */ | |
800 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
801 | ||
802 | /* clear interrupts */ | |
803 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
804 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
805 | ||
806 | return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); | |
807 | } | |
808 | ||
fd1dc87d | 809 | static void __init gpmc_mem_init(void) |
f37e4580 ID |
810 | { |
811 | int cs; | |
812 | unsigned long boot_rom_space = 0; | |
813 | ||
7f245162 KP |
814 | /* never allocate the first page, to facilitate bug detection; |
815 | * even if we didn't boot from ROM. | |
816 | */ | |
817 | boot_rom_space = BOOT_ROM_SPACE; | |
818 | /* In apollon the CS0 is mapped as 0x0000 0000 */ | |
819 | if (machine_is_omap_apollon()) | |
820 | boot_rom_space = 0; | |
f37e4580 ID |
821 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; |
822 | gpmc_mem_root.end = GPMC_MEM_END; | |
823 | ||
824 | /* Reserve all regions that has been set up by bootloader */ | |
825 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
826 | u32 base, size; | |
827 | ||
828 | if (!gpmc_cs_mem_enabled(cs)) | |
829 | continue; | |
830 | gpmc_cs_get_memconf(cs, &base, &size); | |
831 | if (gpmc_cs_insert_mem(cs, base, size) < 0) | |
832 | BUG(); | |
833 | } | |
4bbbc1ad JY |
834 | } |
835 | ||
db97eb7d | 836 | static int __init gpmc_init(void) |
4bbbc1ad | 837 | { |
6b6c32fc AM |
838 | u32 l; |
839 | int ret = -EINVAL; | |
77aded2f | 840 | int gpmc_irq; |
8d08436d | 841 | char *ck = NULL; |
fd1dc87d PW |
842 | |
843 | if (cpu_is_omap24xx()) { | |
844 | ck = "core_l3_ck"; | |
845 | if (cpu_is_omap2420()) | |
846 | l = OMAP2420_GPMC_BASE; | |
847 | else | |
848 | l = OMAP34XX_GPMC_BASE; | |
77aded2f | 849 | gpmc_irq = INT_34XX_GPMC_IRQ; |
fd1dc87d PW |
850 | } else if (cpu_is_omap34xx()) { |
851 | ck = "gpmc_fck"; | |
852 | l = OMAP34XX_GPMC_BASE; | |
77aded2f | 853 | gpmc_irq = INT_34XX_GPMC_IRQ; |
1a5da219 S |
854 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
855 | /* Base address and irq number are same for OMAP4/5 */ | |
d79b1267 | 856 | ck = "gpmc_ck"; |
44169075 | 857 | l = OMAP44XX_GPMC_BASE; |
77aded2f | 858 | gpmc_irq = OMAP44XX_IRQ_GPMC; |
fd1dc87d | 859 | } |
4bbbc1ad | 860 | |
8d08436d | 861 | if (WARN_ON(!ck)) |
db97eb7d | 862 | return ret; |
8d08436d | 863 | |
fd1dc87d PW |
864 | gpmc_l3_clk = clk_get(NULL, ck); |
865 | if (IS_ERR(gpmc_l3_clk)) { | |
866 | printk(KERN_ERR "Could not get GPMC clock %s\n", ck); | |
85d7a070 | 867 | BUG(); |
fd1dc87d PW |
868 | } |
869 | ||
870 | gpmc_base = ioremap(l, SZ_4K); | |
871 | if (!gpmc_base) { | |
872 | clk_put(gpmc_l3_clk); | |
873 | printk(KERN_ERR "Could not get GPMC register memory\n"); | |
85d7a070 | 874 | BUG(); |
fd1dc87d PW |
875 | } |
876 | ||
1daa8c1d OJ |
877 | clk_enable(gpmc_l3_clk); |
878 | ||
4bbbc1ad JY |
879 | l = gpmc_read_reg(GPMC_REVISION); |
880 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | |
881 | /* Set smart idle mode and automatic L3 clock gating */ | |
882 | l = gpmc_read_reg(GPMC_SYSCONFIG); | |
883 | l &= 0x03 << 3; | |
884 | l |= (0x02 << 3) | (1 << 0); | |
885 | gpmc_write_reg(GPMC_SYSCONFIG, l); | |
f37e4580 | 886 | gpmc_mem_init(); |
db97eb7d | 887 | |
6b6c32fc | 888 | ret = gpmc_setup_irq(gpmc_irq); |
db97eb7d SG |
889 | if (ret) |
890 | pr_err("gpmc: irq-%d could not claim: err %d\n", | |
77aded2f | 891 | gpmc_irq, ret); |
db97eb7d SG |
892 | return ret; |
893 | } | |
894 | postcore_initcall(gpmc_init); | |
895 | ||
896 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) | |
897 | { | |
6b6c32fc AM |
898 | int i; |
899 | u32 regval; | |
900 | ||
901 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
902 | ||
903 | if (!regval) | |
904 | return IRQ_NONE; | |
905 | ||
906 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
907 | if (regval & gpmc_client_irq[i].bitmask) | |
908 | generic_handle_irq(gpmc_client_irq[i].irq); | |
db97eb7d | 909 | |
6b6c32fc | 910 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
db97eb7d SG |
911 | |
912 | return IRQ_HANDLED; | |
4bbbc1ad | 913 | } |
a2d3e7ba RN |
914 | |
915 | #ifdef CONFIG_ARCH_OMAP3 | |
916 | static struct omap3_gpmc_regs gpmc_context; | |
917 | ||
b2fa3b7c | 918 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
919 | { |
920 | int i; | |
b2fa3b7c | 921 | |
a2d3e7ba RN |
922 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
923 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
924 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
925 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
926 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
927 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
928 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
929 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
930 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | |
931 | if (gpmc_context.cs_context[i].is_valid) { | |
932 | gpmc_context.cs_context[i].config1 = | |
933 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
934 | gpmc_context.cs_context[i].config2 = | |
935 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
936 | gpmc_context.cs_context[i].config3 = | |
937 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
938 | gpmc_context.cs_context[i].config4 = | |
939 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
940 | gpmc_context.cs_context[i].config5 = | |
941 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
942 | gpmc_context.cs_context[i].config6 = | |
943 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
944 | gpmc_context.cs_context[i].config7 = | |
945 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
946 | } | |
947 | } | |
948 | } | |
949 | ||
b2fa3b7c | 950 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
951 | { |
952 | int i; | |
b2fa3b7c | 953 | |
a2d3e7ba RN |
954 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
955 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
956 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
957 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
958 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
959 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
960 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
961 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
962 | if (gpmc_context.cs_context[i].is_valid) { | |
963 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
964 | gpmc_context.cs_context[i].config1); | |
965 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
966 | gpmc_context.cs_context[i].config2); | |
967 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
968 | gpmc_context.cs_context[i].config3); | |
969 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
970 | gpmc_context.cs_context[i].config4); | |
971 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
972 | gpmc_context.cs_context[i].config5); | |
973 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
974 | gpmc_context.cs_context[i].config6); | |
975 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
976 | gpmc_context.cs_context[i].config7); | |
977 | } | |
978 | } | |
979 | } | |
980 | #endif /* CONFIG_ARCH_OMAP3 */ | |
948d38e7 SG |
981 | |
982 | /** | |
983 | * gpmc_enable_hwecc - enable hardware ecc functionality | |
984 | * @cs: chip select number | |
985 | * @mode: read/write mode | |
986 | * @dev_width: device bus width(1 for x16, 0 for x8) | |
987 | * @ecc_size: bytes for which ECC will be generated | |
988 | */ | |
989 | int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) | |
990 | { | |
991 | unsigned int val; | |
992 | ||
993 | /* check if ecc module is in used */ | |
994 | if (gpmc_ecc_used != -EINVAL) | |
995 | return -EINVAL; | |
996 | ||
997 | gpmc_ecc_used = cs; | |
998 | ||
999 | /* clear ecc and enable bits */ | |
2c65e744 YY |
1000 | gpmc_write_reg(GPMC_ECC_CONTROL, |
1001 | GPMC_ECC_CTRL_ECCCLEAR | | |
1002 | GPMC_ECC_CTRL_ECCREG1); | |
948d38e7 SG |
1003 | |
1004 | /* program ecc and result sizes */ | |
1005 | val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); | |
1006 | gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val); | |
1007 | ||
1008 | switch (mode) { | |
1009 | case GPMC_ECC_READ: | |
2c65e744 YY |
1010 | case GPMC_ECC_WRITE: |
1011 | gpmc_write_reg(GPMC_ECC_CONTROL, | |
1012 | GPMC_ECC_CTRL_ECCCLEAR | | |
1013 | GPMC_ECC_CTRL_ECCREG1); | |
948d38e7 SG |
1014 | break; |
1015 | case GPMC_ECC_READSYN: | |
2c65e744 YY |
1016 | gpmc_write_reg(GPMC_ECC_CONTROL, |
1017 | GPMC_ECC_CTRL_ECCCLEAR | | |
1018 | GPMC_ECC_CTRL_ECCDISABLE); | |
948d38e7 SG |
1019 | break; |
1020 | default: | |
1021 | printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); | |
1022 | break; | |
1023 | } | |
1024 | ||
1025 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
1026 | val = (dev_width << 7) | (cs << 1) | (0x1); | |
1027 | gpmc_write_reg(GPMC_ECC_CONFIG, val); | |
1028 | return 0; | |
1029 | } | |
f611b020 | 1030 | EXPORT_SYMBOL_GPL(gpmc_enable_hwecc); |
948d38e7 SG |
1031 | |
1032 | /** | |
1033 | * gpmc_calculate_ecc - generate non-inverted ecc bytes | |
1034 | * @cs: chip select number | |
1035 | * @dat: data pointer over which ecc is computed | |
1036 | * @ecc_code: ecc code buffer | |
1037 | * | |
1038 | * Using non-inverted ECC is considered ugly since writing a blank | |
1039 | * page (padding) will clear the ECC bytes. This is not a problem as long | |
1040 | * no one is trying to write data on the seemingly unused page. Reading | |
1041 | * an erased page will produce an ECC mismatch between generated and read | |
1042 | * ECC bytes that has to be dealt with separately. | |
1043 | */ | |
1044 | int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code) | |
1045 | { | |
1046 | unsigned int val = 0x0; | |
1047 | ||
1048 | if (gpmc_ecc_used != cs) | |
1049 | return -EINVAL; | |
1050 | ||
1051 | /* read ecc result */ | |
1052 | val = gpmc_read_reg(GPMC_ECC1_RESULT); | |
1053 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
1054 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
1055 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
1056 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
1057 | ||
1058 | gpmc_ecc_used = -EINVAL; | |
1059 | return 0; | |
1060 | } | |
f611b020 | 1061 | EXPORT_SYMBOL_GPL(gpmc_calculate_ecc); |
8d602cf5 ID |
1062 | |
1063 | #ifdef CONFIG_ARCH_OMAP3 | |
1064 | ||
1065 | /** | |
1066 | * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality | |
1067 | * @cs: chip select number | |
1068 | * @nsectors: how many 512-byte sectors to process | |
1069 | * @nerrors: how many errors to correct per sector (4 or 8) | |
1070 | * | |
1071 | * This function must be executed before any call to gpmc_enable_hwecc_bch. | |
1072 | */ | |
1073 | int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors) | |
1074 | { | |
1075 | /* check if ecc module is in use */ | |
1076 | if (gpmc_ecc_used != -EINVAL) | |
1077 | return -EINVAL; | |
1078 | ||
1079 | /* support only OMAP3 class */ | |
1080 | if (!cpu_is_omap34xx()) { | |
1081 | printk(KERN_ERR "BCH ecc is not supported on this CPU\n"); | |
1082 | return -EINVAL; | |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. | |
1087 | * Other chips may be added if confirmed to work. | |
1088 | */ | |
1089 | if ((nerrors == 4) && | |
1090 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { | |
1091 | printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n"); | |
1092 | return -EINVAL; | |
1093 | } | |
1094 | ||
1095 | /* sanity check */ | |
1096 | if (nsectors > 8) { | |
1097 | printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n", | |
1098 | nsectors); | |
1099 | return -EINVAL; | |
1100 | } | |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch); | |
1105 | ||
1106 | /** | |
1107 | * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality | |
1108 | * @cs: chip select number | |
1109 | * @mode: read/write mode | |
1110 | * @dev_width: device bus width(1 for x16, 0 for x8) | |
1111 | * @nsectors: how many 512-byte sectors to process | |
1112 | * @nerrors: how many errors to correct per sector (4 or 8) | |
1113 | */ | |
1114 | int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors, | |
1115 | int nerrors) | |
1116 | { | |
1117 | unsigned int val; | |
1118 | ||
1119 | /* check if ecc module is in use */ | |
1120 | if (gpmc_ecc_used != -EINVAL) | |
1121 | return -EINVAL; | |
1122 | ||
1123 | gpmc_ecc_used = cs; | |
1124 | ||
1125 | /* clear ecc and enable bits */ | |
1126 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x1); | |
1127 | ||
1128 | /* | |
1129 | * When using BCH, sector size is hardcoded to 512 bytes. | |
1130 | * Here we are using wrapping mode 6 both for reading and writing, with: | |
1131 | * size0 = 0 (no additional protected byte in spare area) | |
1132 | * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
1133 | */ | |
1134 | gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12)); | |
1135 | ||
1136 | /* BCH configuration */ | |
1137 | val = ((1 << 16) | /* enable BCH */ | |
1138 | (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */ | |
1139 | (0x06 << 8) | /* wrap mode = 6 */ | |
1140 | (dev_width << 7) | /* bus width */ | |
1141 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1142 | (cs << 1) | /* ECC CS */ | |
1143 | (0x1)); /* enable ECC */ | |
1144 | ||
1145 | gpmc_write_reg(GPMC_ECC_CONFIG, val); | |
1146 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | |
1147 | return 0; | |
1148 | } | |
1149 | EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch); | |
1150 | ||
1151 | /** | |
1152 | * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes | |
1153 | * @cs: chip select number | |
1154 | * @dat: The pointer to data on which ecc is computed | |
1155 | * @ecc: The ecc output buffer | |
1156 | */ | |
1157 | int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc) | |
1158 | { | |
1159 | int i; | |
1160 | unsigned long nsectors, reg, val1, val2; | |
1161 | ||
1162 | if (gpmc_ecc_used != cs) | |
1163 | return -EINVAL; | |
1164 | ||
1165 | nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1; | |
1166 | ||
1167 | for (i = 0; i < nsectors; i++) { | |
1168 | ||
1169 | reg = GPMC_ECC_BCH_RESULT_0 + 16*i; | |
1170 | ||
1171 | /* Read hw-computed remainder */ | |
1172 | val1 = gpmc_read_reg(reg + 0); | |
1173 | val2 = gpmc_read_reg(reg + 4); | |
1174 | ||
1175 | /* | |
1176 | * Add constant polynomial to remainder, in order to get an ecc | |
1177 | * sequence of 0xFFs for a buffer filled with 0xFFs; and | |
1178 | * left-justify the resulting polynomial. | |
1179 | */ | |
1180 | *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF); | |
1181 | *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF); | |
1182 | *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF)); | |
1183 | *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF); | |
1184 | *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF); | |
1185 | *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF); | |
1186 | *ecc++ = 0x7f ^ ((val1 & 0xF) << 4); | |
1187 | } | |
1188 | ||
1189 | gpmc_ecc_used = -EINVAL; | |
1190 | return 0; | |
1191 | } | |
1192 | EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4); | |
1193 | ||
1194 | /** | |
1195 | * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes | |
1196 | * @cs: chip select number | |
1197 | * @dat: The pointer to data on which ecc is computed | |
1198 | * @ecc: The ecc output buffer | |
1199 | */ | |
1200 | int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc) | |
1201 | { | |
1202 | int i; | |
1203 | unsigned long nsectors, reg, val1, val2, val3, val4; | |
1204 | ||
1205 | if (gpmc_ecc_used != cs) | |
1206 | return -EINVAL; | |
1207 | ||
1208 | nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1; | |
1209 | ||
1210 | for (i = 0; i < nsectors; i++) { | |
1211 | ||
1212 | reg = GPMC_ECC_BCH_RESULT_0 + 16*i; | |
1213 | ||
1214 | /* Read hw-computed remainder */ | |
1215 | val1 = gpmc_read_reg(reg + 0); | |
1216 | val2 = gpmc_read_reg(reg + 4); | |
1217 | val3 = gpmc_read_reg(reg + 8); | |
1218 | val4 = gpmc_read_reg(reg + 12); | |
1219 | ||
1220 | /* | |
1221 | * Add constant polynomial to remainder, in order to get an ecc | |
1222 | * sequence of 0xFFs for a buffer filled with 0xFFs. | |
1223 | */ | |
1224 | *ecc++ = 0xef ^ (val4 & 0xFF); | |
1225 | *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); | |
1226 | *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); | |
1227 | *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); | |
1228 | *ecc++ = 0xed ^ (val3 & 0xFF); | |
1229 | *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); | |
1230 | *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); | |
1231 | *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); | |
1232 | *ecc++ = 0x97 ^ (val2 & 0xFF); | |
1233 | *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); | |
1234 | *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); | |
1235 | *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); | |
1236 | *ecc++ = 0xb5 ^ (val1 & 0xFF); | |
1237 | } | |
1238 | ||
1239 | gpmc_ecc_used = -EINVAL; | |
1240 | return 0; | |
1241 | } | |
1242 | EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8); | |
1243 | ||
1244 | #endif /* CONFIG_ARCH_OMAP3 */ |