[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.c

/*
 * GPMC support functions
 *
 * Copyright (C) 2005-2006 Nokia Corporation
 *
 * Author: Juha Yrjola
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>

#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/gpmc.h>

#undef DEBUG

#ifdef CONFIG_ARCH_OMAP2420
#define GPMC_BASE		0x6800a000
#endif

#ifdef CONFIG_ARCH_OMAP2430
#define GPMC_BASE		0x6E000000
#endif

#define GPMC_REVISION		0x00
#define GPMC_SYSCONFIG		0x10
#define GPMC_SYSSTATUS		0x14
#define GPMC_IRQSTATUS		0x18
#define GPMC_IRQENABLE		0x1c
#define GPMC_TIMEOUT_CONTROL	0x40
#define GPMC_ERR_ADDRESS	0x44
#define GPMC_ERR_TYPE		0x48
#define GPMC_CONFIG		0x50
#define GPMC_STATUS		0x54
#define GPMC_PREFETCH_CONFIG1	0x1e0
#define GPMC_PREFETCH_CONFIG2	0x1e4
#define GPMC_PREFETCH_CONTROL	0x1e8
#define GPMC_PREFETCH_STATUS	0x1f0
#define GPMC_ECC_CONFIG		0x1f4
#define GPMC_ECC_CONTROL	0x1f8
#define GPMC_ECC_SIZE_CONFIG	0x1fc

#define GPMC_CS0		0x60
#define GPMC_CS_SIZE		0x30

#define GPMC_CS_NUM		8
#define GPMC_MEM_START		0x00000000
#define GPMC_MEM_END		0x3FFFFFFF
#define BOOT_ROM_SPACE		0x100000	/* 1MB */

#define GPMC_CHUNK_SHIFT	24		/* 16 MB */
#define GPMC_SECTION_SHIFT	28		/* 128 MB */

static struct resource	gpmc_mem_root;
static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned		gpmc_cs_map;

static void __iomem *gpmc_base =
	(void __iomem *) IO_ADDRESS(GPMC_BASE);
static void __iomem *gpmc_cs_base =
	(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;

static struct clk *gpmc_l3_clk;

static void gpmc_write_reg(int idx, u32 val)
{
	__raw_writel(val, gpmc_base + idx);
}

static u32 gpmc_read_reg(int idx)
{
	return __raw_readl(gpmc_base + idx);
}

void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
	void __iomem *reg_addr;

	reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
	__raw_writel(val, reg_addr);
}

u32 gpmc_cs_read_reg(int cs, int idx)
{
	return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
}

/* TODO: Add support for gpmc_fck to clock framework and use it */
unsigned long gpmc_get_fclk_period(void)
{
	/* In picoseconds */
	return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
}

unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
	unsigned long tick_ps;

	/* Calculate in picosecs to yield more exact results */
	tick_ps = gpmc_get_fclk_period();

	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}

#ifdef DEBUG
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time, const char *name)
#else
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
			       int time)
#endif
{
	u32 l;
	int ticks, mask, nr_bits;

	if (time == 0)
		ticks = 0;
	else
		ticks = gpmc_ns_to_ticks(time);
	nr_bits = end_bit - st_bit + 1;
	if (ticks >= 1 << nr_bits) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
				cs, name, time, ticks, 1 << nr_bits);
#endif
		return -1;
	}

	mask = (1 << nr_bits) - 1;
	l = gpmc_cs_read_reg(cs, reg);
#ifdef DEBUG
	printk(KERN_INFO
		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
			(l >> st_bit) & mask, time);
#endif
	l &= ~(mask << st_bit);
	l |= ticks << st_bit;
	gpmc_cs_write_reg(cs, reg, l);

	return 0;
}

#ifdef DEBUG
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
			t->field, #field) < 0)			\
		return -1
#else
#define GPMC_SET_ONE(reg, st, end, field) \
	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
		return -1
#endif

int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
{
	int div;
	u32 l;

	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	div = l / gpmc_get_fclk_period();
	if (div > 4)
		return -1;
	if (div <= 0)
		div = 1;

	return div;
}

int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
	int div;
	u32 l;

	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	if (div < 0)
		return -1;

	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);

	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);

	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);

	/* caller is expected to have initialized CONFIG1 to cover
	 * at least sync vs async
	 */
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
#ifdef DEBUG
		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
				cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif
		l &= ~0x03;
		l |= (div - 1);
		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	}

	return 0;
}

static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
{
	u32 l;
	u32 mask;

	mask = (1 << GPMC_SECTION_SHIFT) - size;
	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~0x3f;
	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	l &= ~(0x0f << 8);
	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	l |= 1 << 6;		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_disable_mem(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	l &= ~(1 << 6);		/* CSVALID */
	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}

static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
{
	u32 l;
	u32 mask;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	mask = (l >> 8) & 0x0f;
	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
}

static int gpmc_cs_mem_enabled(int cs)
{
	u32 l;

	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	return l & (1 << 6);
}

int gpmc_cs_set_reserved(int cs, int reserved)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	gpmc_cs_map &= ~(1 << cs);
	gpmc_cs_map |= (reserved ? 1 : 0) << cs;

	return 0;
}

int gpmc_cs_reserved(int cs)
{
	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	return gpmc_cs_map & (1 << cs);
}

static unsigned long gpmc_mem_align(unsigned long size)
{
	int order;

	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	order = GPMC_CHUNK_SHIFT - 1;
	do {
		size >>= 1;
		order++;
	} while (size);
	size = 1 << order;
	return size;
}

static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
{
	struct resource	*res = &gpmc_cs_mem[cs];
	int r;

	size = gpmc_mem_align(size);
	spin_lock(&gpmc_mem_lock);
	res->start = base;
	res->end = base + size - 1;
	r = request_resource(&gpmc_mem_root, res);
	spin_unlock(&gpmc_mem_lock);

	return r;
}

int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
	struct resource *res = &gpmc_cs_mem[cs];
	int r = -1;

	if (cs > GPMC_CS_NUM)
		return -ENODEV;

	size = gpmc_mem_align(size);
	if (size > (1 << GPMC_SECTION_SHIFT))
		return -ENOMEM;

	spin_lock(&gpmc_mem_lock);
	if (gpmc_cs_reserved(cs)) {
		r = -EBUSY;
		goto out;
	}
	if (gpmc_cs_mem_enabled(cs))
		r = adjust_resource(res, res->start & ~(size - 1), size);
	if (r < 0)
		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
				      size, NULL, NULL);
	if (r < 0)
		goto out;

	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
	*base = res->start;
	gpmc_cs_set_reserved(cs, 1);
out:
	spin_unlock(&gpmc_mem_lock);
	return r;
}

void gpmc_cs_free(int cs)
{
	spin_lock(&gpmc_mem_lock);
	if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
		BUG();
		spin_unlock(&gpmc_mem_lock);
		return;
	}
	gpmc_cs_disable_mem(cs);
	release_resource(&gpmc_cs_mem[cs]);
	gpmc_cs_set_reserved(cs, 0);
	spin_unlock(&gpmc_mem_lock);
}

void __init gpmc_mem_init(void)
{
	int cs;
	unsigned long boot_rom_space = 0;

	/* never allocate the first page, to facilitate bug detection;
	 * even if we didn't boot from ROM.
	 */
	boot_rom_space = BOOT_ROM_SPACE;
	/* In apollon the CS0 is mapped as 0x0000 0000 */
	if (machine_is_omap_apollon())
		boot_rom_space = 0;
	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	gpmc_mem_root.end = GPMC_MEM_END;

	/* Reserve all regions that has been set up by bootloader */
	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
		u32 base, size;

		if (!gpmc_cs_mem_enabled(cs))
			continue;
		gpmc_cs_get_memconf(cs, &base, &size);
		if (gpmc_cs_insert_mem(cs, base, size) < 0)
			BUG();
	}
}

void __init gpmc_init(void)
{
	u32 l;

	gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
	BUG_ON(IS_ERR(gpmc_l3_clk));

	l = gpmc_read_reg(GPMC_REVISION);
	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	/* Set smart idle mode and automatic L3 clock gating */
	l = gpmc_read_reg(GPMC_SYSCONFIG);
	l &= 0x03 << 3;
	l |= (0x02 << 3) | (1 << 0);
	gpmc_write_reg(GPMC_SYSCONFIG, l);

	gpmc_mem_init();
}
Commit	Line	Data
4bbbc1ad JY	1	/*
	2	* GPMC support functions
	3	*
	4	* Copyright (C) 2005-2006 Nokia Corporation
	5	*
	6	* Author: Juha Yrjola
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
f37e4580 ID	16	#include <linux/ioport.h>
f37e4580 ID	17	#include <linux/spinlock.h>
4bbbc1ad JY	18
4bbbc1ad JY	19	#include <asm/io.h>
7f245162	20	#include <asm/mach-types.h>
4bbbc1ad JY	21	#include <asm/arch/gpmc.h>
	22
	23	#undef DEBUG
	24
72d0f1c3	25	#ifdef CONFIG_ARCH_OMAP2420
4bbbc1ad	26	#define GPMC_BASE 0x6800a000
72d0f1c3 SMK	27	#endif
	28
	29	#ifdef CONFIG_ARCH_OMAP2430
	30	#define GPMC_BASE 0x6E000000
	31	#endif
	32
4bbbc1ad JY	33	#define GPMC_REVISION 0x00
	34	#define GPMC_SYSCONFIG 0x10
	35	#define GPMC_SYSSTATUS 0x14
	36	#define GPMC_IRQSTATUS 0x18
	37	#define GPMC_IRQENABLE 0x1c
	38	#define GPMC_TIMEOUT_CONTROL 0x40
	39	#define GPMC_ERR_ADDRESS 0x44
	40	#define GPMC_ERR_TYPE 0x48
	41	#define GPMC_CONFIG 0x50
	42	#define GPMC_STATUS 0x54
	43	#define GPMC_PREFETCH_CONFIG1 0x1e0
	44	#define GPMC_PREFETCH_CONFIG2 0x1e4
	45	#define GPMC_PREFETCH_CONTROL 0x1e8
	46	#define GPMC_PREFETCH_STATUS 0x1f0
	47	#define GPMC_ECC_CONFIG 0x1f4
	48	#define GPMC_ECC_CONTROL 0x1f8
	49	#define GPMC_ECC_SIZE_CONFIG 0x1fc
	50
	51	#define GPMC_CS0 0x60
	52	#define GPMC_CS_SIZE 0x30
	53
f37e4580 ID	54	#define GPMC_CS_NUM 8
	55	#define GPMC_MEM_START 0x00000000
	56	#define GPMC_MEM_END 0x3FFFFFFF
	57	#define BOOT_ROM_SPACE 0x100000 /* 1MB */
	58
	59	#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
	60	#define GPMC_SECTION_SHIFT 28 /* 128 MB */
	61
	62	static struct resource gpmc_mem_root;
	63	static struct resource gpmc_cs_mem[GPMC_CS_NUM];
87b247c4	64	static DEFINE_SPINLOCK(gpmc_mem_lock);
f37e4580 ID	65	static unsigned gpmc_cs_map;
f37e4580 ID	66
4bbbc1ad JY	67	static void __iomem *gpmc_base =
	68	(void __iomem *) IO_ADDRESS(GPMC_BASE);
	69	static void __iomem *gpmc_cs_base =
	70	(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
	71
	72	static struct clk *gpmc_l3_clk;
	73
	74	static void gpmc_write_reg(int idx, u32 val)
	75	{
	76	__raw_writel(val, gpmc_base + idx);
	77	}
	78
	79	static u32 gpmc_read_reg(int idx)
	80	{
	81	return __raw_readl(gpmc_base + idx);
	82	}
	83
	84	void gpmc_cs_write_reg(int cs, int idx, u32 val)
	85	{
	86	void __iomem *reg_addr;
	87
	88	reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
	89	__raw_writel(val, reg_addr);
	90	}
	91
	92	u32 gpmc_cs_read_reg(int cs, int idx)
	93	{
	94	return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
	95	}
	96
	97	/* TODO: Add support for gpmc_fck to clock framework and use it */
1c22cc13	98	unsigned long gpmc_get_fclk_period(void)
4bbbc1ad JY	99	{
	100	/* In picoseconds */
	101	return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
	102	}
	103
	104	unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
	105	{
	106	unsigned long tick_ps;
	107
	108	/* Calculate in picosecs to yield more exact results */
	109	tick_ps = gpmc_get_fclk_period();
	110
	111	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
	112	}
	113
	114	#ifdef DEBUG
	115	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468	116	int time, const char *name)
4bbbc1ad JY	117	#else
	118	static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
	119	int time)
	120	#endif
	121	{
	122	u32 l;
	123	int ticks, mask, nr_bits;
	124
	125	if (time == 0)
	126	ticks = 0;
	127	else
	128	ticks = gpmc_ns_to_ticks(time);
	129	nr_bits = end_bit - st_bit + 1;
1c22cc13 DB	130	if (ticks >= 1 << nr_bits) {
	131	#ifdef DEBUG
	132	printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
	133	cs, name, time, ticks, 1 << nr_bits);
	134	#endif
4bbbc1ad	135	return -1;
1c22cc13	136	}
4bbbc1ad JY	137
	138	mask = (1 << nr_bits) - 1;
	139	l = gpmc_cs_read_reg(cs, reg);
	140	#ifdef DEBUG
1c22cc13 DB	141	printk(KERN_INFO
1c22cc13 DB	142	"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
2aab6468	143	cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
1c22cc13	144	(l >> st_bit) & mask, time);
4bbbc1ad JY	145	#endif
	146	l &= ~(mask << st_bit);
	147	l \|= ticks << st_bit;
	148	gpmc_cs_write_reg(cs, reg, l);
	149
	150	return 0;
	151	}
	152
	153	#ifdef DEBUG
	154	#define GPMC_SET_ONE(reg, st, end, field) \
	155	if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
	156	t->field, #field) < 0) \
	157	return -1
	158	#else
	159	#define GPMC_SET_ONE(reg, st, end, field) \
	160	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
	161	return -1
	162	#endif
	163
	164	int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
	165	{
	166	int div;
	167	u32 l;
	168
	169	l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
	170	div = l / gpmc_get_fclk_period();
	171	if (div > 4)
	172	return -1;
1c22cc13	173	if (div <= 0)
4bbbc1ad JY	174	div = 1;
	175
	176	return div;
	177	}
	178
	179	int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
	180	{
	181	int div;
	182	u32 l;
	183
	184	div = gpmc_cs_calc_divider(cs, t->sync_clk);
	185	if (div < 0)
	186	return -1;
	187
	188	GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
	189	GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
	190	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
	191
	192	GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
	193	GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
	194	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
	195
	196	GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
	197	GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
	198	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
	199	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
	200
	201	GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
	202	GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
	203	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
	204
	205	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
	206
1c22cc13 DB	207	/* caller is expected to have initialized CONFIG1 to cover
	208	* at least sync vs async
	209	*/
	210	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
	211	if (l & (GPMC_CONFIG1_READTYPE_SYNC \| GPMC_CONFIG1_WRITETYPE_SYNC)) {
4bbbc1ad	212	#ifdef DEBUG
1c22cc13 DB	213	printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
1c22cc13 DB	214	cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad	215	#endif
1c22cc13 DB	216	l &= ~0x03;
	217	l \|= (div - 1);
	218	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
	219	}
4bbbc1ad JY	220
	221	return 0;
	222	}
	223
f37e4580 ID	224	static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
	225	{
	226	u32 l;
	227	u32 mask;
	228
	229	mask = (1 << GPMC_SECTION_SHIFT) - size;
	230	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	231	l &= ~0x3f;
	232	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
	233	l &= ~(0x0f << 8);
	234	l \|= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
	235	l \|= 1 << 6; /* CSVALID */
	236	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	237	}
	238
	239	static void gpmc_cs_disable_mem(int cs)
	240	{
	241	u32 l;
	242
	243	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	244	l &= ~(1 << 6); /* CSVALID */
	245	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
	246	}
	247
	248	static void gpmc_cs_get_memconf(int cs, u32 base, u32 size)
	249	{
	250	u32 l;
	251	u32 mask;
	252
	253	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	254	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
	255	mask = (l >> 8) & 0x0f;
	256	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
	257	}
	258
	259	static int gpmc_cs_mem_enabled(int cs)
	260	{
	261	u32 l;
	262
	263	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
	264	return l & (1 << 6);
	265	}
	266
c40fae95	267	int gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad	268	{
c40fae95 TL	269	if (cs > GPMC_CS_NUM)
	270	return -ENODEV;
	271
f37e4580 ID	272	gpmc_cs_map &= ~(1 << cs);
f37e4580 ID	273	gpmc_cs_map \|= (reserved ? 1 : 0) << cs;
c40fae95 TL	274
c40fae95 TL	275	return 0;
f37e4580 ID	276	}
f37e4580 ID	277
c40fae95	278	int gpmc_cs_reserved(int cs)
f37e4580	279	{
c40fae95 TL	280	if (cs > GPMC_CS_NUM)
	281	return -ENODEV;
	282
f37e4580 ID	283	return gpmc_cs_map & (1 << cs);
	284	}
	285
	286	static unsigned long gpmc_mem_align(unsigned long size)
	287	{
	288	int order;
	289
	290	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
	291	order = GPMC_CHUNK_SHIFT - 1;
	292	do {
	293	size >>= 1;
	294	order++;
	295	} while (size);
	296	size = 1 << order;
	297	return size;
	298	}
	299
	300	static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
	301	{
	302	struct resource *res = &gpmc_cs_mem[cs];
	303	int r;
	304
	305	size = gpmc_mem_align(size);
	306	spin_lock(&gpmc_mem_lock);
	307	res->start = base;
	308	res->end = base + size - 1;
	309	r = request_resource(&gpmc_mem_root, res);
	310	spin_unlock(&gpmc_mem_lock);
	311
	312	return r;
	313	}
	314
	315	int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
	316	{
	317	struct resource *res = &gpmc_cs_mem[cs];
	318	int r = -1;
	319
	320	if (cs > GPMC_CS_NUM)
	321	return -ENODEV;
	322
	323	size = gpmc_mem_align(size);
	324	if (size > (1 << GPMC_SECTION_SHIFT))
	325	return -ENOMEM;
	326
	327	spin_lock(&gpmc_mem_lock);
	328	if (gpmc_cs_reserved(cs)) {
	329	r = -EBUSY;
	330	goto out;
	331	}
	332	if (gpmc_cs_mem_enabled(cs))
	333	r = adjust_resource(res, res->start & ~(size - 1), size);
	334	if (r < 0)
	335	r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
	336	size, NULL, NULL);
	337	if (r < 0)
	338	goto out;
	339
	340	gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
	341	*base = res->start;
	342	gpmc_cs_set_reserved(cs, 1);
	343	out:
	344	spin_unlock(&gpmc_mem_lock);
	345	return r;
	346	}
347
348	void gpmc_cs_free(int cs)
349	{
350	spin_lock(&gpmc_mem_lock);
351	if (cs >= GPMC_CS_NUM \|\| !gpmc_cs_reserved(cs)) {
352	printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
353	BUG();
354	spin_unlock(&gpmc_mem_lock);
355	return;
356	}
357	gpmc_cs_disable_mem(cs);
358	release_resource(&gpmc_cs_mem[cs]);
359	gpmc_cs_set_reserved(cs, 0);
360	spin_unlock(&gpmc_mem_lock);
361	}
362
363	void __init gpmc_mem_init(void)
364	{
365	int cs;
366	unsigned long boot_rom_space = 0;
367
7f245162 KP	368	/* never allocate the first page, to facilitate bug detection;
	369	* even if we didn't boot from ROM.
	370	*/
	371	boot_rom_space = BOOT_ROM_SPACE;
	372	/* In apollon the CS0 is mapped as 0x0000 0000 */
	373	if (machine_is_omap_apollon())
	374	boot_rom_space = 0;
f37e4580 ID	375	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
	376	gpmc_mem_root.end = GPMC_MEM_END;
	377
	378	/* Reserve all regions that has been set up by bootloader */
	379	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
	380	u32 base, size;
	381
	382	if (!gpmc_cs_mem_enabled(cs))
	383	continue;
	384	gpmc_cs_get_memconf(cs, &base, &size);
	385	if (gpmc_cs_insert_mem(cs, base, size) < 0)
	386	BUG();
	387	}
4bbbc1ad JY	388	}
	389
	390	void __init gpmc_init(void)
	391	{
	392	u32 l;
	393
	394	gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
	395	BUG_ON(IS_ERR(gpmc_l3_clk));
	396
	397	l = gpmc_read_reg(GPMC_REVISION);
	398	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	399	/* Set smart idle mode and automatic L3 clock gating */
	400	l = gpmc_read_reg(GPMC_SYSCONFIG);
	401	l &= 0x03 << 3;
	402	l \|= (0x02 << 3) \| (1 << 0);
	403	gpmc_write_reg(GPMC_SYSCONFIG, l);
f37e4580 ID	404
f37e4580 ID	405	gpmc_mem_init();
4bbbc1ad	406	}