Commit | Line | Data |
---|---|---|
4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
db97eb7d | 17 | #include <linux/irq.h> |
4bbbc1ad JY |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
f37e4580 ID |
22 | #include <linux/ioport.h> |
23 | #include <linux/spinlock.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fd1dc87d | 25 | #include <linux/module.h> |
db97eb7d | 26 | #include <linux/interrupt.h> |
da496873 | 27 | #include <linux/platform_device.h> |
4bbbc1ad | 28 | |
bc3668ea AM |
29 | #include <linux/platform_data/mtd-nand-omap2.h> |
30 | ||
7f245162 | 31 | #include <asm/mach-types.h> |
ce491cf8 | 32 | #include <plat/gpmc.h> |
4bbbc1ad | 33 | |
7d7e1eba | 34 | #include <plat/cpu.h> |
dbc04161 | 35 | #include <plat/gpmc.h> |
ce491cf8 | 36 | #include <plat/sdrc.h> |
4be48fd5 | 37 | #include <plat/omap_device.h> |
72d0f1c3 | 38 | |
dbc04161 | 39 | #include "soc.h" |
7d7e1eba TL |
40 | #include "common.h" |
41 | ||
4be48fd5 AM |
42 | #define DEVICE_NAME "omap-gpmc" |
43 | ||
fd1dc87d | 44 | /* GPMC register offsets */ |
4bbbc1ad JY |
45 | #define GPMC_REVISION 0x00 |
46 | #define GPMC_SYSCONFIG 0x10 | |
47 | #define GPMC_SYSSTATUS 0x14 | |
48 | #define GPMC_IRQSTATUS 0x18 | |
49 | #define GPMC_IRQENABLE 0x1c | |
50 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
51 | #define GPMC_ERR_ADDRESS 0x44 | |
52 | #define GPMC_ERR_TYPE 0x48 | |
53 | #define GPMC_CONFIG 0x50 | |
54 | #define GPMC_STATUS 0x54 | |
55 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
56 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 57 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
58 | #define GPMC_PREFETCH_STATUS 0x1f0 |
59 | #define GPMC_ECC_CONFIG 0x1f4 | |
60 | #define GPMC_ECC_CONTROL 0x1f8 | |
61 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 62 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 63 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
2fdf0c98 AM |
64 | #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ |
65 | #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ | |
66 | #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ | |
4bbbc1ad | 67 | |
2c65e744 YY |
68 | /* GPMC ECC control settings */ |
69 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
70 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
71 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
72 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
73 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
74 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
75 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
76 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
77 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
78 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
79 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
80 | ||
948d38e7 | 81 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad | 82 | #define GPMC_CS_SIZE 0x30 |
2fdf0c98 | 83 | #define GPMC_BCH_SIZE 0x10 |
4bbbc1ad | 84 | |
f37e4580 ID |
85 | #define GPMC_MEM_START 0x00000000 |
86 | #define GPMC_MEM_END 0x3FFFFFFF | |
87 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | |
88 | ||
89 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
90 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
91 | ||
59e9c5ae | 92 | #define CS_NUM_SHIFT 24 |
93 | #define ENABLE_PREFETCH (0x1 << 7) | |
94 | #define DMA_MPU_MODE 2 | |
95 | ||
da496873 AM |
96 | #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) |
97 | #define GPMC_REVISION_MINOR(l) (l & 0xf) | |
98 | ||
99 | #define GPMC_HAS_WR_ACCESS 0x1 | |
100 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | |
101 | ||
6b6c32fc AM |
102 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
103 | */ | |
104 | #define GPMC_NR_IRQ 2 | |
105 | ||
106 | struct gpmc_client_irq { | |
107 | unsigned irq; | |
108 | u32 bitmask; | |
109 | }; | |
110 | ||
a2d3e7ba RN |
111 | /* Structure to save gpmc cs context */ |
112 | struct gpmc_cs_config { | |
113 | u32 config1; | |
114 | u32 config2; | |
115 | u32 config3; | |
116 | u32 config4; | |
117 | u32 config5; | |
118 | u32 config6; | |
119 | u32 config7; | |
120 | int is_valid; | |
121 | }; | |
122 | ||
123 | /* | |
124 | * Structure to save/restore gpmc context | |
125 | * to support core off on OMAP3 | |
126 | */ | |
127 | struct omap3_gpmc_regs { | |
128 | u32 sysconfig; | |
129 | u32 irqenable; | |
130 | u32 timeout_ctrl; | |
131 | u32 config; | |
132 | u32 prefetch_config1; | |
133 | u32 prefetch_config2; | |
134 | u32 prefetch_control; | |
135 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
136 | }; | |
137 | ||
6b6c32fc AM |
138 | static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; |
139 | static struct irq_chip gpmc_irq_chip; | |
140 | static unsigned gpmc_irq_start; | |
141 | ||
f37e4580 ID |
142 | static struct resource gpmc_mem_root; |
143 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 144 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
948d38e7 | 145 | static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ |
da496873 AM |
146 | static struct device *gpmc_dev; |
147 | static int gpmc_irq; | |
148 | static resource_size_t phys_base, mem_size; | |
149 | static unsigned gpmc_capability; | |
fd1dc87d | 150 | static void __iomem *gpmc_base; |
4bbbc1ad | 151 | |
fd1dc87d | 152 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 153 | |
db97eb7d SG |
154 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
155 | ||
4bbbc1ad JY |
156 | static void gpmc_write_reg(int idx, u32 val) |
157 | { | |
158 | __raw_writel(val, gpmc_base + idx); | |
159 | } | |
160 | ||
161 | static u32 gpmc_read_reg(int idx) | |
162 | { | |
163 | return __raw_readl(gpmc_base + idx); | |
164 | } | |
165 | ||
166 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
167 | { | |
168 | void __iomem *reg_addr; | |
169 | ||
948d38e7 | 170 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
4bbbc1ad JY |
171 | __raw_writel(val, reg_addr); |
172 | } | |
173 | ||
174 | u32 gpmc_cs_read_reg(int cs, int idx) | |
175 | { | |
fd1dc87d PW |
176 | void __iomem *reg_addr; |
177 | ||
948d38e7 | 178 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
fd1dc87d | 179 | return __raw_readl(reg_addr); |
4bbbc1ad JY |
180 | } |
181 | ||
fd1dc87d | 182 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
1c22cc13 | 183 | unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 184 | { |
fd1dc87d PW |
185 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
186 | ||
187 | if (rate == 0) { | |
188 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | rate /= 1000; | |
193 | rate = 1000000000 / rate; /* In picoseconds */ | |
194 | ||
195 | return rate; | |
4bbbc1ad JY |
196 | } |
197 | ||
198 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |
199 | { | |
200 | unsigned long tick_ps; | |
201 | ||
202 | /* Calculate in picosecs to yield more exact results */ | |
203 | tick_ps = gpmc_get_fclk_period(); | |
204 | ||
205 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
206 | } | |
207 | ||
a3551f5b AH |
208 | unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
209 | { | |
210 | unsigned long tick_ps; | |
211 | ||
212 | /* Calculate in picosecs to yield more exact results */ | |
213 | tick_ps = gpmc_get_fclk_period(); | |
214 | ||
215 | return (time_ps + tick_ps - 1) / tick_ps; | |
216 | } | |
217 | ||
fd1dc87d PW |
218 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
219 | { | |
220 | return ticks * gpmc_get_fclk_period() / 1000; | |
221 | } | |
222 | ||
23300597 KS |
223 | unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) |
224 | { | |
225 | unsigned long ticks = gpmc_ns_to_ticks(time_ns); | |
226 | ||
227 | return ticks * gpmc_get_fclk_period() / 1000; | |
228 | } | |
229 | ||
4bbbc1ad JY |
230 | #ifdef DEBUG |
231 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
2aab6468 | 232 | int time, const char *name) |
4bbbc1ad JY |
233 | #else |
234 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
235 | int time) | |
236 | #endif | |
237 | { | |
238 | u32 l; | |
239 | int ticks, mask, nr_bits; | |
240 | ||
241 | if (time == 0) | |
242 | ticks = 0; | |
243 | else | |
244 | ticks = gpmc_ns_to_ticks(time); | |
245 | nr_bits = end_bit - st_bit + 1; | |
1c22cc13 DB |
246 | if (ticks >= 1 << nr_bits) { |
247 | #ifdef DEBUG | |
248 | printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", | |
249 | cs, name, time, ticks, 1 << nr_bits); | |
250 | #endif | |
4bbbc1ad | 251 | return -1; |
1c22cc13 | 252 | } |
4bbbc1ad JY |
253 | |
254 | mask = (1 << nr_bits) - 1; | |
255 | l = gpmc_cs_read_reg(cs, reg); | |
256 | #ifdef DEBUG | |
1c22cc13 DB |
257 | printk(KERN_INFO |
258 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 259 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 260 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
261 | #endif |
262 | l &= ~(mask << st_bit); | |
263 | l |= ticks << st_bit; | |
264 | gpmc_cs_write_reg(cs, reg, l); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | #ifdef DEBUG | |
270 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
271 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
272 | t->field, #field) < 0) \ | |
273 | return -1 | |
274 | #else | |
275 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
276 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
277 | return -1 | |
278 | #endif | |
279 | ||
1b47ca1a | 280 | int gpmc_calc_divider(unsigned int sync_clk) |
4bbbc1ad JY |
281 | { |
282 | int div; | |
283 | u32 l; | |
284 | ||
a3551f5b | 285 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
4bbbc1ad JY |
286 | div = l / gpmc_get_fclk_period(); |
287 | if (div > 4) | |
288 | return -1; | |
1c22cc13 | 289 | if (div <= 0) |
4bbbc1ad JY |
290 | div = 1; |
291 | ||
292 | return div; | |
293 | } | |
294 | ||
295 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
296 | { | |
297 | int div; | |
298 | u32 l; | |
299 | ||
1b47ca1a | 300 | div = gpmc_calc_divider(t->sync_clk); |
4bbbc1ad | 301 | if (div < 0) |
a032d33b | 302 | return div; |
4bbbc1ad JY |
303 | |
304 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
305 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
306 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
307 | ||
308 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
309 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
310 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
311 | ||
312 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
313 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
314 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
315 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
316 | ||
317 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
318 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
319 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
320 | ||
321 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
322 | ||
da496873 | 323 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) |
cc26b3b0 | 324 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); |
da496873 | 325 | if (gpmc_capability & GPMC_HAS_WR_ACCESS) |
cc26b3b0 | 326 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); |
cc26b3b0 | 327 | |
1c22cc13 DB |
328 | /* caller is expected to have initialized CONFIG1 to cover |
329 | * at least sync vs async | |
330 | */ | |
331 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
332 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 333 | #ifdef DEBUG |
1c22cc13 DB |
334 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
335 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 336 | #endif |
1c22cc13 DB |
337 | l &= ~0x03; |
338 | l |= (div - 1); | |
339 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
340 | } | |
4bbbc1ad JY |
341 | |
342 | return 0; | |
343 | } | |
344 | ||
f37e4580 ID |
345 | static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
346 | { | |
347 | u32 l; | |
348 | u32 mask; | |
349 | ||
350 | mask = (1 << GPMC_SECTION_SHIFT) - size; | |
351 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
352 | l &= ~0x3f; | |
353 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
354 | l &= ~(0x0f << 8); | |
355 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 356 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
357 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
358 | } | |
359 | ||
360 | static void gpmc_cs_disable_mem(int cs) | |
361 | { | |
362 | u32 l; | |
363 | ||
364 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 365 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
366 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
367 | } | |
368 | ||
369 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
370 | { | |
371 | u32 l; | |
372 | u32 mask; | |
373 | ||
374 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
375 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
376 | mask = (l >> 8) & 0x0f; | |
377 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
378 | } | |
379 | ||
380 | static int gpmc_cs_mem_enabled(int cs) | |
381 | { | |
382 | u32 l; | |
383 | ||
384 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 385 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
386 | } |
387 | ||
c40fae95 | 388 | int gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 389 | { |
c40fae95 TL |
390 | if (cs > GPMC_CS_NUM) |
391 | return -ENODEV; | |
392 | ||
f37e4580 ID |
393 | gpmc_cs_map &= ~(1 << cs); |
394 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
c40fae95 TL |
395 | |
396 | return 0; | |
f37e4580 ID |
397 | } |
398 | ||
c40fae95 | 399 | int gpmc_cs_reserved(int cs) |
f37e4580 | 400 | { |
c40fae95 TL |
401 | if (cs > GPMC_CS_NUM) |
402 | return -ENODEV; | |
403 | ||
f37e4580 ID |
404 | return gpmc_cs_map & (1 << cs); |
405 | } | |
406 | ||
407 | static unsigned long gpmc_mem_align(unsigned long size) | |
408 | { | |
409 | int order; | |
410 | ||
411 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
412 | order = GPMC_CHUNK_SHIFT - 1; | |
413 | do { | |
414 | size >>= 1; | |
415 | order++; | |
416 | } while (size); | |
417 | size = 1 << order; | |
418 | return size; | |
419 | } | |
420 | ||
421 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
422 | { | |
423 | struct resource *res = &gpmc_cs_mem[cs]; | |
424 | int r; | |
425 | ||
426 | size = gpmc_mem_align(size); | |
427 | spin_lock(&gpmc_mem_lock); | |
428 | res->start = base; | |
429 | res->end = base + size - 1; | |
430 | r = request_resource(&gpmc_mem_root, res); | |
431 | spin_unlock(&gpmc_mem_lock); | |
432 | ||
433 | return r; | |
434 | } | |
435 | ||
da496873 AM |
436 | static int gpmc_cs_delete_mem(int cs) |
437 | { | |
438 | struct resource *res = &gpmc_cs_mem[cs]; | |
439 | int r; | |
440 | ||
441 | spin_lock(&gpmc_mem_lock); | |
442 | r = release_resource(&gpmc_cs_mem[cs]); | |
443 | res->start = 0; | |
444 | res->end = 0; | |
445 | spin_unlock(&gpmc_mem_lock); | |
446 | ||
447 | return r; | |
448 | } | |
449 | ||
f37e4580 ID |
450 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
451 | { | |
452 | struct resource *res = &gpmc_cs_mem[cs]; | |
453 | int r = -1; | |
454 | ||
455 | if (cs > GPMC_CS_NUM) | |
456 | return -ENODEV; | |
457 | ||
458 | size = gpmc_mem_align(size); | |
459 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
460 | return -ENOMEM; | |
461 | ||
462 | spin_lock(&gpmc_mem_lock); | |
463 | if (gpmc_cs_reserved(cs)) { | |
464 | r = -EBUSY; | |
465 | goto out; | |
466 | } | |
467 | if (gpmc_cs_mem_enabled(cs)) | |
468 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
469 | if (r < 0) | |
470 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
471 | size, NULL, NULL); | |
472 | if (r < 0) | |
473 | goto out; | |
474 | ||
6d135242 | 475 | gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
f37e4580 ID |
476 | *base = res->start; |
477 | gpmc_cs_set_reserved(cs, 1); | |
478 | out: | |
479 | spin_unlock(&gpmc_mem_lock); | |
480 | return r; | |
481 | } | |
fd1dc87d | 482 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
483 | |
484 | void gpmc_cs_free(int cs) | |
485 | { | |
486 | spin_lock(&gpmc_mem_lock); | |
e7fdc605 | 487 | if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
488 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
489 | BUG(); | |
490 | spin_unlock(&gpmc_mem_lock); | |
491 | return; | |
492 | } | |
493 | gpmc_cs_disable_mem(cs); | |
494 | release_resource(&gpmc_cs_mem[cs]); | |
495 | gpmc_cs_set_reserved(cs, 0); | |
496 | spin_unlock(&gpmc_mem_lock); | |
497 | } | |
fd1dc87d | 498 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 499 | |
948d38e7 SG |
500 | /** |
501 | * gpmc_cs_configure - write request to configure gpmc | |
502 | * @cs: chip select number | |
503 | * @cmd: command type | |
504 | * @wval: value to write | |
505 | * @return status of the operation | |
506 | */ | |
507 | int gpmc_cs_configure(int cs, int cmd, int wval) | |
508 | { | |
509 | int err = 0; | |
510 | u32 regval = 0; | |
511 | ||
512 | switch (cmd) { | |
db97eb7d SG |
513 | case GPMC_ENABLE_IRQ: |
514 | gpmc_write_reg(GPMC_IRQENABLE, wval); | |
515 | break; | |
516 | ||
948d38e7 SG |
517 | case GPMC_SET_IRQ_STATUS: |
518 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
519 | break; | |
520 | ||
521 | case GPMC_CONFIG_WP: | |
522 | regval = gpmc_read_reg(GPMC_CONFIG); | |
523 | if (wval) | |
524 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
525 | else | |
526 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
527 | gpmc_write_reg(GPMC_CONFIG, regval); | |
528 | break; | |
529 | ||
530 | case GPMC_CONFIG_RDY_BSY: | |
531 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
532 | if (wval) | |
533 | regval |= WR_RD_PIN_MONITORING; | |
534 | else | |
535 | regval &= ~WR_RD_PIN_MONITORING; | |
536 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
537 | break; | |
538 | ||
539 | case GPMC_CONFIG_DEV_SIZE: | |
540 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
8ef5d844 YY |
541 | |
542 | /* clear 2 target bits */ | |
543 | regval &= ~GPMC_CONFIG1_DEVICESIZE(3); | |
544 | ||
545 | /* set the proper value */ | |
948d38e7 | 546 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); |
8ef5d844 | 547 | |
948d38e7 SG |
548 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); |
549 | break; | |
550 | ||
551 | case GPMC_CONFIG_DEV_TYPE: | |
552 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
553 | regval |= GPMC_CONFIG1_DEVICETYPE(wval); | |
554 | if (wval == GPMC_DEVICETYPE_NOR) | |
555 | regval |= GPMC_CONFIG1_MUXADDDATA; | |
556 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
557 | break; | |
558 | ||
559 | default: | |
560 | printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); | |
561 | err = -EINVAL; | |
562 | } | |
563 | ||
564 | return err; | |
565 | } | |
566 | EXPORT_SYMBOL(gpmc_cs_configure); | |
567 | ||
52bd138d AM |
568 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
569 | { | |
2fdf0c98 AM |
570 | int i; |
571 | ||
52bd138d AM |
572 | reg->gpmc_status = gpmc_base + GPMC_STATUS; |
573 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | |
574 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
575 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
576 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
577 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
578 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
579 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
580 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
581 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
582 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
583 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
584 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
585 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
586 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
2fdf0c98 AM |
587 | |
588 | for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { | |
589 | reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + | |
590 | GPMC_BCH_SIZE * i; | |
591 | reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + | |
592 | GPMC_BCH_SIZE * i; | |
593 | reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + | |
594 | GPMC_BCH_SIZE * i; | |
595 | reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + | |
596 | GPMC_BCH_SIZE * i; | |
597 | } | |
52bd138d AM |
598 | } |
599 | ||
6b6c32fc AM |
600 | int gpmc_get_client_irq(unsigned irq_config) |
601 | { | |
602 | int i; | |
603 | ||
604 | if (hweight32(irq_config) > 1) | |
605 | return 0; | |
606 | ||
607 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
608 | if (gpmc_client_irq[i].bitmask & irq_config) | |
609 | return gpmc_client_irq[i].irq; | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
614 | static int gpmc_irq_endis(unsigned irq, bool endis) | |
615 | { | |
616 | int i; | |
617 | u32 regval; | |
618 | ||
619 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
620 | if (irq == gpmc_client_irq[i].irq) { | |
621 | regval = gpmc_read_reg(GPMC_IRQENABLE); | |
622 | if (endis) | |
623 | regval |= gpmc_client_irq[i].bitmask; | |
624 | else | |
625 | regval &= ~gpmc_client_irq[i].bitmask; | |
626 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
627 | break; | |
628 | } | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | static void gpmc_irq_disable(struct irq_data *p) | |
634 | { | |
635 | gpmc_irq_endis(p->irq, false); | |
636 | } | |
637 | ||
638 | static void gpmc_irq_enable(struct irq_data *p) | |
639 | { | |
640 | gpmc_irq_endis(p->irq, true); | |
641 | } | |
642 | ||
643 | static void gpmc_irq_noop(struct irq_data *data) { } | |
644 | ||
645 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | |
646 | ||
da496873 | 647 | static int gpmc_setup_irq(void) |
6b6c32fc AM |
648 | { |
649 | int i; | |
650 | u32 regval; | |
651 | ||
652 | if (!gpmc_irq) | |
653 | return -EINVAL; | |
654 | ||
655 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | |
656 | if (IS_ERR_VALUE(gpmc_irq_start)) { | |
657 | pr_err("irq_alloc_descs failed\n"); | |
658 | return gpmc_irq_start; | |
659 | } | |
660 | ||
661 | gpmc_irq_chip.name = "gpmc"; | |
662 | gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; | |
663 | gpmc_irq_chip.irq_enable = gpmc_irq_enable; | |
664 | gpmc_irq_chip.irq_disable = gpmc_irq_disable; | |
665 | gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; | |
666 | gpmc_irq_chip.irq_ack = gpmc_irq_noop; | |
667 | gpmc_irq_chip.irq_mask = gpmc_irq_noop; | |
668 | gpmc_irq_chip.irq_unmask = gpmc_irq_noop; | |
669 | ||
670 | gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; | |
671 | gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; | |
672 | ||
673 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
674 | gpmc_client_irq[i].irq = gpmc_irq_start + i; | |
675 | irq_set_chip_and_handler(gpmc_client_irq[i].irq, | |
676 | &gpmc_irq_chip, handle_simple_irq); | |
677 | set_irq_flags(gpmc_client_irq[i].irq, | |
678 | IRQF_VALID | IRQF_NOAUTOEN); | |
679 | } | |
680 | ||
681 | /* Disable interrupts */ | |
682 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
683 | ||
684 | /* clear interrupts */ | |
685 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
686 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
687 | ||
688 | return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); | |
689 | } | |
690 | ||
61687c61 | 691 | static __devexit int gpmc_free_irq(void) |
da496873 AM |
692 | { |
693 | int i; | |
694 | ||
695 | if (gpmc_irq) | |
696 | free_irq(gpmc_irq, NULL); | |
697 | ||
698 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
699 | irq_set_handler(gpmc_client_irq[i].irq, NULL); | |
700 | irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); | |
701 | irq_modify_status(gpmc_client_irq[i].irq, 0, 0); | |
702 | } | |
703 | ||
704 | irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static void __devexit gpmc_mem_exit(void) | |
710 | { | |
711 | int cs; | |
712 | ||
713 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
714 | if (!gpmc_cs_mem_enabled(cs)) | |
715 | continue; | |
716 | gpmc_cs_delete_mem(cs); | |
717 | } | |
718 | ||
719 | } | |
720 | ||
721 | static void __devinit gpmc_mem_init(void) | |
f37e4580 ID |
722 | { |
723 | int cs; | |
724 | unsigned long boot_rom_space = 0; | |
725 | ||
7f245162 KP |
726 | /* never allocate the first page, to facilitate bug detection; |
727 | * even if we didn't boot from ROM. | |
728 | */ | |
729 | boot_rom_space = BOOT_ROM_SPACE; | |
730 | /* In apollon the CS0 is mapped as 0x0000 0000 */ | |
731 | if (machine_is_omap_apollon()) | |
732 | boot_rom_space = 0; | |
f37e4580 ID |
733 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; |
734 | gpmc_mem_root.end = GPMC_MEM_END; | |
735 | ||
736 | /* Reserve all regions that has been set up by bootloader */ | |
737 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
738 | u32 base, size; | |
739 | ||
740 | if (!gpmc_cs_mem_enabled(cs)) | |
741 | continue; | |
742 | gpmc_cs_get_memconf(cs, &base, &size); | |
743 | if (gpmc_cs_insert_mem(cs, base, size) < 0) | |
744 | BUG(); | |
745 | } | |
4bbbc1ad JY |
746 | } |
747 | ||
da496873 | 748 | static __devinit int gpmc_probe(struct platform_device *pdev) |
4bbbc1ad | 749 | { |
6b6c32fc | 750 | u32 l; |
da496873 | 751 | struct resource *res; |
4bbbc1ad | 752 | |
da496873 AM |
753 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
754 | if (res == NULL) | |
755 | return -ENOENT; | |
8d08436d | 756 | |
da496873 AM |
757 | phys_base = res->start; |
758 | mem_size = resource_size(res); | |
fd1dc87d | 759 | |
da496873 | 760 | gpmc_base = devm_request_and_ioremap(&pdev->dev, res); |
fd1dc87d | 761 | if (!gpmc_base) { |
da496873 AM |
762 | dev_err(&pdev->dev, "error: request memory / ioremap\n"); |
763 | return -EADDRNOTAVAIL; | |
764 | } | |
765 | ||
766 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
767 | if (res == NULL) | |
768 | dev_warn(&pdev->dev, "Failed to get resource: irq\n"); | |
769 | else | |
770 | gpmc_irq = res->start; | |
771 | ||
772 | gpmc_l3_clk = clk_get(&pdev->dev, "fck"); | |
773 | if (IS_ERR(gpmc_l3_clk)) { | |
774 | dev_err(&pdev->dev, "error: clk_get\n"); | |
775 | gpmc_irq = 0; | |
776 | return PTR_ERR(gpmc_l3_clk); | |
fd1dc87d PW |
777 | } |
778 | ||
4d7cb45e | 779 | clk_prepare_enable(gpmc_l3_clk); |
1daa8c1d | 780 | |
da496873 AM |
781 | gpmc_dev = &pdev->dev; |
782 | ||
4bbbc1ad | 783 | l = gpmc_read_reg(GPMC_REVISION); |
da496873 AM |
784 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
785 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | |
786 | dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), | |
787 | GPMC_REVISION_MINOR(l)); | |
788 | ||
f37e4580 | 789 | gpmc_mem_init(); |
db97eb7d | 790 | |
da496873 AM |
791 | if (IS_ERR_VALUE(gpmc_setup_irq())) |
792 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
61687c61 | 797 | static __devexit int gpmc_remove(struct platform_device *pdev) |
da496873 AM |
798 | { |
799 | gpmc_free_irq(); | |
800 | gpmc_mem_exit(); | |
801 | gpmc_dev = NULL; | |
802 | return 0; | |
803 | } | |
804 | ||
805 | static struct platform_driver gpmc_driver = { | |
806 | .probe = gpmc_probe, | |
807 | .remove = __devexit_p(gpmc_remove), | |
808 | .driver = { | |
809 | .name = DEVICE_NAME, | |
810 | .owner = THIS_MODULE, | |
811 | }, | |
812 | }; | |
813 | ||
814 | static __init int gpmc_init(void) | |
815 | { | |
816 | return platform_driver_register(&gpmc_driver); | |
817 | } | |
818 | ||
819 | static __exit void gpmc_exit(void) | |
820 | { | |
821 | platform_driver_unregister(&gpmc_driver); | |
822 | ||
db97eb7d | 823 | } |
da496873 | 824 | |
db97eb7d | 825 | postcore_initcall(gpmc_init); |
da496873 | 826 | module_exit(gpmc_exit); |
db97eb7d | 827 | |
4be48fd5 AM |
828 | static int __init omap_gpmc_init(void) |
829 | { | |
830 | struct omap_hwmod *oh; | |
831 | struct platform_device *pdev; | |
832 | char *oh_name = "gpmc"; | |
833 | ||
834 | oh = omap_hwmod_lookup(oh_name); | |
835 | if (!oh) { | |
836 | pr_err("Could not look up %s\n", oh_name); | |
837 | return -ENODEV; | |
838 | } | |
839 | ||
840 | pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0); | |
841 | WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); | |
842 | ||
843 | return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; | |
844 | } | |
845 | postcore_initcall(omap_gpmc_init); | |
846 | ||
db97eb7d SG |
847 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) |
848 | { | |
6b6c32fc AM |
849 | int i; |
850 | u32 regval; | |
851 | ||
852 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
853 | ||
854 | if (!regval) | |
855 | return IRQ_NONE; | |
856 | ||
857 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
858 | if (regval & gpmc_client_irq[i].bitmask) | |
859 | generic_handle_irq(gpmc_client_irq[i].irq); | |
db97eb7d | 860 | |
6b6c32fc | 861 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
db97eb7d SG |
862 | |
863 | return IRQ_HANDLED; | |
4bbbc1ad | 864 | } |
a2d3e7ba RN |
865 | |
866 | #ifdef CONFIG_ARCH_OMAP3 | |
867 | static struct omap3_gpmc_regs gpmc_context; | |
868 | ||
b2fa3b7c | 869 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
870 | { |
871 | int i; | |
b2fa3b7c | 872 | |
a2d3e7ba RN |
873 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
874 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
875 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
876 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
877 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
878 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
879 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
880 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
881 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | |
882 | if (gpmc_context.cs_context[i].is_valid) { | |
883 | gpmc_context.cs_context[i].config1 = | |
884 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
885 | gpmc_context.cs_context[i].config2 = | |
886 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
887 | gpmc_context.cs_context[i].config3 = | |
888 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
889 | gpmc_context.cs_context[i].config4 = | |
890 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
891 | gpmc_context.cs_context[i].config5 = | |
892 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
893 | gpmc_context.cs_context[i].config6 = | |
894 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
895 | gpmc_context.cs_context[i].config7 = | |
896 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
897 | } | |
898 | } | |
899 | } | |
900 | ||
b2fa3b7c | 901 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
902 | { |
903 | int i; | |
b2fa3b7c | 904 | |
a2d3e7ba RN |
905 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
906 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
907 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
908 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
909 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
910 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
911 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
912 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
913 | if (gpmc_context.cs_context[i].is_valid) { | |
914 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
915 | gpmc_context.cs_context[i].config1); | |
916 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
917 | gpmc_context.cs_context[i].config2); | |
918 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
919 | gpmc_context.cs_context[i].config3); | |
920 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
921 | gpmc_context.cs_context[i].config4); | |
922 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
923 | gpmc_context.cs_context[i].config5); | |
924 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
925 | gpmc_context.cs_context[i].config6); | |
926 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
927 | gpmc_context.cs_context[i].config7); | |
928 | } | |
929 | } | |
930 | } | |
931 | #endif /* CONFIG_ARCH_OMAP3 */ |