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ARM: OMAP: Split plat/cpu.h into local soc.h for mach-omap1 and mach-omap2
[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.c
CommitLineData
4bbbc1ad
JY		 1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
44169075
SS		 8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
4bbbc1ad
JY		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
fd1dc87d
PW		 15#undef DEBUG
16
db97eb7d 17#include <linux/irq.h>
4bbbc1ad
JY		 18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/err.h>
21#include <linux/clk.h>
f37e4580
ID		 22#include <linux/ioport.h>
23#include <linux/spinlock.h>
fced80c7 24#include <linux/io.h>
fd1dc87d 25#include <linux/module.h>
db97eb7d 26#include <linux/interrupt.h>
da496873 27#include <linux/platform_device.h>
4bbbc1ad 28
bc3668ea
AM		 29#include <linux/platform_data/mtd-nand-omap2.h>
30
7f245162 31#include <asm/mach-types.h>
4bbbc1ad 32
dbc04161 33#include "soc.h"
7d7e1eba 34#include "common.h"
25c7d49e 35#include "omap_device.h"
3ef5d007 36#include "gpmc.h"
7d7e1eba 37
4be48fd5
AM		 38#define DEVICE_NAME "omap-gpmc"
39
fd1dc87d 40/* GPMC register offsets */
4bbbc1ad
JY		 41#define GPMC_REVISION 0x00
42#define GPMC_SYSCONFIG 0x10
43#define GPMC_SYSSTATUS 0x14
44#define GPMC_IRQSTATUS 0x18
45#define GPMC_IRQENABLE 0x1c
46#define GPMC_TIMEOUT_CONTROL 0x40
47#define GPMC_ERR_ADDRESS 0x44
48#define GPMC_ERR_TYPE 0x48
49#define GPMC_CONFIG 0x50
50#define GPMC_STATUS 0x54
51#define GPMC_PREFETCH_CONFIG1 0x1e0
52#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b 53#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad
JY		 54#define GPMC_PREFETCH_STATUS 0x1f0
55#define GPMC_ECC_CONFIG 0x1f4
56#define GPMC_ECC_CONTROL 0x1f8
57#define GPMC_ECC_SIZE_CONFIG 0x1fc
948d38e7 58#define GPMC_ECC1_RESULT 0x200
8d602cf5 59#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
2fdf0c98
AM		 60#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
61#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
62#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
4bbbc1ad 63
2c65e744
YY		 64/* GPMC ECC control settings */
65#define GPMC_ECC_CTRL_ECCCLEAR 0x100
66#define GPMC_ECC_CTRL_ECCDISABLE 0x000
67#define GPMC_ECC_CTRL_ECCREG1 0x001
68#define GPMC_ECC_CTRL_ECCREG2 0x002
69#define GPMC_ECC_CTRL_ECCREG3 0x003
70#define GPMC_ECC_CTRL_ECCREG4 0x004
71#define GPMC_ECC_CTRL_ECCREG5 0x005
72#define GPMC_ECC_CTRL_ECCREG6 0x006
73#define GPMC_ECC_CTRL_ECCREG7 0x007
74#define GPMC_ECC_CTRL_ECCREG8 0x008
75#define GPMC_ECC_CTRL_ECCREG9 0x009
76
948d38e7 77#define GPMC_CS0_OFFSET 0x60
4bbbc1ad 78#define GPMC_CS_SIZE 0x30
2fdf0c98 79#define GPMC_BCH_SIZE 0x10
4bbbc1ad 80
f37e4580
ID		 81#define GPMC_MEM_START 0x00000000
82#define GPMC_MEM_END 0x3FFFFFFF
83#define BOOT_ROM_SPACE 0x100000 /* 1MB */
84
85#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
86#define GPMC_SECTION_SHIFT 28 /* 128 MB */
87
59e9c5ae 88#define CS_NUM_SHIFT 24
89#define ENABLE_PREFETCH (0x1 << 7)
90#define DMA_MPU_MODE 2
91
da496873
AM		 92#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
93#define GPMC_REVISION_MINOR(l) (l & 0xf)
94
95#define GPMC_HAS_WR_ACCESS 0x1
96#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
97
6b6c32fc
AM		 98/* XXX: Only NAND irq has been considered,currently these are the only ones used
99 */
100#define GPMC_NR_IRQ 2
101
102struct gpmc_client_irq {
103 unsigned irq;
104 u32 bitmask;
105};
106
a2d3e7ba
RN		 107/* Structure to save gpmc cs context */
108struct gpmc_cs_config {
109 u32 config1;
110 u32 config2;
111 u32 config3;
112 u32 config4;
113 u32 config5;
114 u32 config6;
115 u32 config7;
116 int is_valid;
117};
118
119/*
120 * Structure to save/restore gpmc context
121 * to support core off on OMAP3
122 */
123struct omap3_gpmc_regs {
124 u32 sysconfig;
125 u32 irqenable;
126 u32 timeout_ctrl;
127 u32 config;
128 u32 prefetch_config1;
129 u32 prefetch_config2;
130 u32 prefetch_control;
131 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
132};
133
6b6c32fc
AM		 134static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
135static struct irq_chip gpmc_irq_chip;
136static unsigned gpmc_irq_start;
137
f37e4580
ID		 138static struct resource gpmc_mem_root;
139static struct resource gpmc_cs_mem[GPMC_CS_NUM];
87b247c4 140static DEFINE_SPINLOCK(gpmc_mem_lock);
948d38e7 141static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
da496873
AM		 142static struct device *gpmc_dev;
143static int gpmc_irq;
144static resource_size_t phys_base, mem_size;
145static unsigned gpmc_capability;
fd1dc87d 146static void __iomem *gpmc_base;
4bbbc1ad 147
fd1dc87d 148static struct clk *gpmc_l3_clk;
4bbbc1ad 149
db97eb7d
SG		 150static irqreturn_t gpmc_handle_irq(int irq, void *dev);
151
4bbbc1ad
JY		 152static void gpmc_write_reg(int idx, u32 val)
153{
154 __raw_writel(val, gpmc_base + idx);
155}
156
157static u32 gpmc_read_reg(int idx)
158{
159 return __raw_readl(gpmc_base + idx);
160}
161
162void gpmc_cs_write_reg(int cs, int idx, u32 val)
163{
164 void __iomem *reg_addr;
165
948d38e7 166 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
4bbbc1ad
JY		 167 __raw_writel(val, reg_addr);
168}
169
170u32 gpmc_cs_read_reg(int cs, int idx)
171{
fd1dc87d
PW		 172 void __iomem *reg_addr;
173
948d38e7 174 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
fd1dc87d 175 return __raw_readl(reg_addr);
4bbbc1ad
JY		 176}
177
fd1dc87d 178/* TODO: Add support for gpmc_fck to clock framework and use it */
1c22cc13 179unsigned long gpmc_get_fclk_period(void)
4bbbc1ad 180{
fd1dc87d
PW		 181 unsigned long rate = clk_get_rate(gpmc_l3_clk);
182
183 if (rate == 0) {
184 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
185 return 0;
186 }
187
188 rate /= 1000;
189 rate = 1000000000 / rate; /* In picoseconds */
190
191 return rate;
4bbbc1ad
JY		 192}
193
194unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
195{
196 unsigned long tick_ps;
197
198 /* Calculate in picosecs to yield more exact results */
199 tick_ps = gpmc_get_fclk_period();
200
201 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
202}
203
a3551f5b
AH		 204unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
205{
206 unsigned long tick_ps;
207
208 /* Calculate in picosecs to yield more exact results */
209 tick_ps = gpmc_get_fclk_period();
210
211 return (time_ps + tick_ps - 1) / tick_ps;
212}
213
fd1dc87d
PW		 214unsigned int gpmc_ticks_to_ns(unsigned int ticks)
215{
216 return ticks * gpmc_get_fclk_period() / 1000;
217}
218
23300597
KS		 219unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
220{
221 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
222
223 return ticks * gpmc_get_fclk_period() / 1000;
224}
225
4bbbc1ad
JY		 226#ifdef DEBUG
227static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
2aab6468 228 int time, const char *name)
4bbbc1ad
JY		 229#else
230static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
231 int time)
232#endif
233{
234 u32 l;
235 int ticks, mask, nr_bits;
236
237 if (time == 0)
238 ticks = 0;
239 else
240 ticks = gpmc_ns_to_ticks(time);
241 nr_bits = end_bit - st_bit + 1;
1c22cc13
DB		 242 if (ticks >= 1 << nr_bits) {
243#ifdef DEBUG
244 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
245 cs, name, time, ticks, 1 << nr_bits);
246#endif
4bbbc1ad 247 return -1;
1c22cc13 248 }
4bbbc1ad
JY		 249
250 mask = (1 << nr_bits) - 1;
251 l = gpmc_cs_read_reg(cs, reg);
252#ifdef DEBUG
1c22cc13
DB		 253 printk(KERN_INFO
254 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
2aab6468 255 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
1c22cc13 256 (l >> st_bit) & mask, time);
4bbbc1ad
JY		 257#endif
258 l &= ~(mask << st_bit);
259 l |= ticks << st_bit;
260 gpmc_cs_write_reg(cs, reg, l);
261
262 return 0;
263}
264
265#ifdef DEBUG
266#define GPMC_SET_ONE(reg, st, end, field) \
267 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
268 t->field, #field) < 0) \
269 return -1
270#else
271#define GPMC_SET_ONE(reg, st, end, field) \
272 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
273 return -1
274#endif
275
1b47ca1a 276int gpmc_calc_divider(unsigned int sync_clk)
4bbbc1ad
JY		 277{
278 int div;
279 u32 l;
280
a3551f5b 281 l = sync_clk + (gpmc_get_fclk_period() - 1);
4bbbc1ad
JY		 282 div = l / gpmc_get_fclk_period();
283 if (div > 4)
284 return -1;
1c22cc13 285 if (div <= 0)
4bbbc1ad
JY		 286 div = 1;
287
288 return div;
289}
290
291int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
292{
293 int div;
294 u32 l;
295
1b47ca1a 296 div = gpmc_calc_divider(t->sync_clk);
4bbbc1ad 297 if (div < 0)
a032d33b 298 return div;
4bbbc1ad
JY		 299
300 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
301 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
302 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
303
304 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
305 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
306 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
307
308 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
309 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
310 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
311 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
312
313 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
314 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
315 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
316
317 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
318
da496873 319 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
cc26b3b0 320 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
da496873 321 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
cc26b3b0 322 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
cc26b3b0 323
1c22cc13
DB		 324 /* caller is expected to have initialized CONFIG1 to cover
325 * at least sync vs async
326 */
327 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
328 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
4bbbc1ad 329#ifdef DEBUG
1c22cc13
DB		 330 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
331 cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad 332#endif
1c22cc13
DB		 333 l &= ~0x03;
334 l |= (div - 1);
335 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
336 }
4bbbc1ad
JY		 337
338 return 0;
339}
340
f37e4580
ID		 341static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
342{
343 u32 l;
344 u32 mask;
345
346 mask = (1 << GPMC_SECTION_SHIFT) - size;
347 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
348 l &= ~0x3f;
349 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
350 l &= ~(0x0f << 8);
351 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
a2d3e7ba 352 l |= GPMC_CONFIG7_CSVALID;
f37e4580
ID		 353 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
354}
355
356static void gpmc_cs_disable_mem(int cs)
357{
358 u32 l;
359
360 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 361 l &= ~GPMC_CONFIG7_CSVALID;
f37e4580
ID		 362 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
363}
364
365static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
366{
367 u32 l;
368 u32 mask;
369
370 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
371 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
372 mask = (l >> 8) & 0x0f;
373 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
374}
375
376static int gpmc_cs_mem_enabled(int cs)
377{
378 u32 l;
379
380 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 381 return l & GPMC_CONFIG7_CSVALID;
f37e4580
ID		 382}
383
c40fae95 384int gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad 385{
c40fae95
TL		 386 if (cs > GPMC_CS_NUM)
387 return -ENODEV;
388
f37e4580
ID		 389 gpmc_cs_map &= ~(1 << cs);
390 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
c40fae95
TL		 391
392 return 0;
f37e4580
ID		 393}
394
c40fae95 395int gpmc_cs_reserved(int cs)
f37e4580 396{
c40fae95
TL		 397 if (cs > GPMC_CS_NUM)
398 return -ENODEV;
399
f37e4580
ID		 400 return gpmc_cs_map & (1 << cs);
401}
402
403static unsigned long gpmc_mem_align(unsigned long size)
404{
405 int order;
406
407 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
408 order = GPMC_CHUNK_SHIFT - 1;
409 do {
410 size >>= 1;
411 order++;
412 } while (size);
413 size = 1 << order;
414 return size;
415}
416
417static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
418{
419 struct resource *res = &gpmc_cs_mem[cs];
420 int r;
421
422 size = gpmc_mem_align(size);
423 spin_lock(&gpmc_mem_lock);
424 res->start = base;
425 res->end = base + size - 1;
426 r = request_resource(&gpmc_mem_root, res);
427 spin_unlock(&gpmc_mem_lock);
428
429 return r;
430}
431
da496873
AM		 432static int gpmc_cs_delete_mem(int cs)
433{
434 struct resource *res = &gpmc_cs_mem[cs];
435 int r;
436
437 spin_lock(&gpmc_mem_lock);
438 r = release_resource(&gpmc_cs_mem[cs]);
439 res->start = 0;
440 res->end = 0;
441 spin_unlock(&gpmc_mem_lock);
442
443 return r;
444}
445
f37e4580
ID		 446int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
447{
448 struct resource *res = &gpmc_cs_mem[cs];
449 int r = -1;
450
451 if (cs > GPMC_CS_NUM)
452 return -ENODEV;
453
454 size = gpmc_mem_align(size);
455 if (size > (1 << GPMC_SECTION_SHIFT))
456 return -ENOMEM;
457
458 spin_lock(&gpmc_mem_lock);
459 if (gpmc_cs_reserved(cs)) {
460 r = -EBUSY;
461 goto out;
462 }
463 if (gpmc_cs_mem_enabled(cs))
464 r = adjust_resource(res, res->start & ~(size - 1), size);
465 if (r < 0)
466 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
467 size, NULL, NULL);
468 if (r < 0)
469 goto out;
470
6d135242 471 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
f37e4580
ID		 472 *base = res->start;
473 gpmc_cs_set_reserved(cs, 1);
474out:
475 spin_unlock(&gpmc_mem_lock);
476 return r;
477}
fd1dc87d 478EXPORT_SYMBOL(gpmc_cs_request);
f37e4580
ID		 479
480void gpmc_cs_free(int cs)
481{
482 spin_lock(&gpmc_mem_lock);
e7fdc605 483 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
f37e4580
ID		 484 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
485 BUG();
486 spin_unlock(&gpmc_mem_lock);
487 return;
488 }
489 gpmc_cs_disable_mem(cs);
490 release_resource(&gpmc_cs_mem[cs]);
491 gpmc_cs_set_reserved(cs, 0);
492 spin_unlock(&gpmc_mem_lock);
493}
fd1dc87d 494EXPORT_SYMBOL(gpmc_cs_free);
f37e4580 495
948d38e7
SG		 496/**
497 * gpmc_cs_configure - write request to configure gpmc
498 * @cs: chip select number
499 * @cmd: command type
500 * @wval: value to write
501 * @return status of the operation
502 */
503int gpmc_cs_configure(int cs, int cmd, int wval)
504{
505 int err = 0;
506 u32 regval = 0;
507
508 switch (cmd) {
db97eb7d
SG		 509 case GPMC_ENABLE_IRQ:
510 gpmc_write_reg(GPMC_IRQENABLE, wval);
511 break;
512
948d38e7
SG		 513 case GPMC_SET_IRQ_STATUS:
514 gpmc_write_reg(GPMC_IRQSTATUS, wval);
515 break;
516
517 case GPMC_CONFIG_WP:
518 regval = gpmc_read_reg(GPMC_CONFIG);
519 if (wval)
520 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
521 else
522 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
523 gpmc_write_reg(GPMC_CONFIG, regval);
524 break;
525
526 case GPMC_CONFIG_RDY_BSY:
527 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
528 if (wval)
529 regval |= WR_RD_PIN_MONITORING;
530 else
531 regval &= ~WR_RD_PIN_MONITORING;
532 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
533 break;
534
535 case GPMC_CONFIG_DEV_SIZE:
536 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
8ef5d844
YY		 537
538 /* clear 2 target bits */
539 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
540
541 /* set the proper value */
948d38e7 542 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
8ef5d844 543
948d38e7
SG		 544 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
545 break;
546
547 case GPMC_CONFIG_DEV_TYPE:
548 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
549 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
550 if (wval == GPMC_DEVICETYPE_NOR)
551 regval |= GPMC_CONFIG1_MUXADDDATA;
552 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
553 break;
554
555 default:
556 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
557 err = -EINVAL;
558 }
559
560 return err;
561}
562EXPORT_SYMBOL(gpmc_cs_configure);
563
52bd138d
AM		 564void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
565{
2fdf0c98
AM		 566 int i;
567
52bd138d
AM		 568 reg->gpmc_status = gpmc_base + GPMC_STATUS;
569 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
570 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
571 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
572 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
573 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
574 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
575 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
576 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
577 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
578 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
579 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
580 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
581 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
582 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
2fdf0c98
AM		 583
584 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
585 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
586 GPMC_BCH_SIZE * i;
587 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
588 GPMC_BCH_SIZE * i;
589 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
590 GPMC_BCH_SIZE * i;
591 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
592 GPMC_BCH_SIZE * i;
593 }
52bd138d
AM		 594}
595
6b6c32fc
AM		 596int gpmc_get_client_irq(unsigned irq_config)
597{
598 int i;
599
600 if (hweight32(irq_config) > 1)
601 return 0;
602
603 for (i = 0; i < GPMC_NR_IRQ; i++)
604 if (gpmc_client_irq[i].bitmask & irq_config)
605 return gpmc_client_irq[i].irq;
606
607 return 0;
608}
609
610static int gpmc_irq_endis(unsigned irq, bool endis)
611{
612 int i;
613 u32 regval;
614
615 for (i = 0; i < GPMC_NR_IRQ; i++)
616 if (irq == gpmc_client_irq[i].irq) {
617 regval = gpmc_read_reg(GPMC_IRQENABLE);
618 if (endis)
619 regval |= gpmc_client_irq[i].bitmask;
620 else
621 regval &= ~gpmc_client_irq[i].bitmask;
622 gpmc_write_reg(GPMC_IRQENABLE, regval);
623 break;
624 }
625
626 return 0;
627}
628
629static void gpmc_irq_disable(struct irq_data *p)
630{
631 gpmc_irq_endis(p->irq, false);
632}
633
634static void gpmc_irq_enable(struct irq_data *p)
635{
636 gpmc_irq_endis(p->irq, true);
637}
638
639static void gpmc_irq_noop(struct irq_data *data) { }
640
641static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
642
da496873 643static int gpmc_setup_irq(void)
6b6c32fc
AM		 644{
645 int i;
646 u32 regval;
647
648 if (!gpmc_irq)
649 return -EINVAL;
650
651 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
652 if (IS_ERR_VALUE(gpmc_irq_start)) {
653 pr_err("irq_alloc_descs failed\n");
654 return gpmc_irq_start;
655 }
656
657 gpmc_irq_chip.name = "gpmc";
658 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
659 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
660 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
661 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
662 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
663 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
664 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
665
666 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
667 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
668
669 for (i = 0; i < GPMC_NR_IRQ; i++) {
670 gpmc_client_irq[i].irq = gpmc_irq_start + i;
671 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
672 &gpmc_irq_chip, handle_simple_irq);
673 set_irq_flags(gpmc_client_irq[i].irq,
674 IRQF_VALID | IRQF_NOAUTOEN);
675 }
676
677 /* Disable interrupts */
678 gpmc_write_reg(GPMC_IRQENABLE, 0);
679
680 /* clear interrupts */
681 regval = gpmc_read_reg(GPMC_IRQSTATUS);
682 gpmc_write_reg(GPMC_IRQSTATUS, regval);
683
684 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
685}
686
61687c61 687static __devexit int gpmc_free_irq(void)
da496873
AM		 688{
689 int i;
690
691 if (gpmc_irq)
692 free_irq(gpmc_irq, NULL);
693
694 for (i = 0; i < GPMC_NR_IRQ; i++) {
695 irq_set_handler(gpmc_client_irq[i].irq, NULL);
696 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
697 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
698 }
699
700 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
701
702 return 0;
703}
704
705static void __devexit gpmc_mem_exit(void)
706{
707 int cs;
708
709 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
710 if (!gpmc_cs_mem_enabled(cs))
711 continue;
712 gpmc_cs_delete_mem(cs);
713 }
714
715}
716
717static void __devinit gpmc_mem_init(void)
f37e4580
ID		 718{
719 int cs;
720 unsigned long boot_rom_space = 0;
721
7f245162
KP		 722 /* never allocate the first page, to facilitate bug detection;
723 * even if we didn't boot from ROM.
724 */
725 boot_rom_space = BOOT_ROM_SPACE;
726 /* In apollon the CS0 is mapped as 0x0000 0000 */
727 if (machine_is_omap_apollon())
728 boot_rom_space = 0;
f37e4580
ID		 729 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
730 gpmc_mem_root.end = GPMC_MEM_END;
731
732 /* Reserve all regions that has been set up by bootloader */
733 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
734 u32 base, size;
735
736 if (!gpmc_cs_mem_enabled(cs))
737 continue;
738 gpmc_cs_get_memconf(cs, &base, &size);
739 if (gpmc_cs_insert_mem(cs, base, size) < 0)
740 BUG();
741 }
4bbbc1ad
JY		 742}
743
da496873 744static __devinit int gpmc_probe(struct platform_device *pdev)
4bbbc1ad 745{
6b6c32fc 746 u32 l;
da496873 747 struct resource *res;
4bbbc1ad 748
da496873
AM		 749 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
750 if (res == NULL)
751 return -ENOENT;
8d08436d 752
da496873
AM		 753 phys_base = res->start;
754 mem_size = resource_size(res);
fd1dc87d 755
da496873 756 gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
fd1dc87d 757 if (!gpmc_base) {
da496873
AM		 758 dev_err(&pdev->dev, "error: request memory / ioremap\n");
759 return -EADDRNOTAVAIL;
760 }
761
762 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
763 if (res == NULL)
764 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
765 else
766 gpmc_irq = res->start;
767
768 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
769 if (IS_ERR(gpmc_l3_clk)) {
770 dev_err(&pdev->dev, "error: clk_get\n");
771 gpmc_irq = 0;
772 return PTR_ERR(gpmc_l3_clk);
fd1dc87d
PW		 773 }
774
4d7cb45e 775 clk_prepare_enable(gpmc_l3_clk);
1daa8c1d 776
da496873
AM		 777 gpmc_dev = &pdev->dev;
778
4bbbc1ad 779 l = gpmc_read_reg(GPMC_REVISION);
da496873
AM		 780 if (GPMC_REVISION_MAJOR(l) > 0x4)
781 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
782 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
783 GPMC_REVISION_MINOR(l));
784
f37e4580 785 gpmc_mem_init();
db97eb7d 786
da496873
AM		 787 if (IS_ERR_VALUE(gpmc_setup_irq()))
788 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
789
790 return 0;
791}
792
61687c61 793static __devexit int gpmc_remove(struct platform_device *pdev)
da496873
AM		 794{
795 gpmc_free_irq();
796 gpmc_mem_exit();
797 gpmc_dev = NULL;
798 return 0;
799}
800
801static struct platform_driver gpmc_driver = {
802 .probe = gpmc_probe,
803 .remove = __devexit_p(gpmc_remove),
804 .driver = {
805 .name = DEVICE_NAME,
806 .owner = THIS_MODULE,
807 },
808};
809
810static __init int gpmc_init(void)
811{
812 return platform_driver_register(&gpmc_driver);
813}
814
815static __exit void gpmc_exit(void)
816{
817 platform_driver_unregister(&gpmc_driver);
818
db97eb7d 819}
da496873 820
db97eb7d 821postcore_initcall(gpmc_init);
da496873 822module_exit(gpmc_exit);
db97eb7d 823
4be48fd5
AM		 824static int __init omap_gpmc_init(void)
825{
826 struct omap_hwmod *oh;
827 struct platform_device *pdev;
828 char *oh_name = "gpmc";
829
830 oh = omap_hwmod_lookup(oh_name);
831 if (!oh) {
832 pr_err("Could not look up %s\n", oh_name);
833 return -ENODEV;
834 }
835
836 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
837 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
838
839 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
840}
841postcore_initcall(omap_gpmc_init);
842
db97eb7d
SG		 843static irqreturn_t gpmc_handle_irq(int irq, void *dev)
844{
6b6c32fc
AM		 845 int i;
846 u32 regval;
847
848 regval = gpmc_read_reg(GPMC_IRQSTATUS);
849
850 if (!regval)
851 return IRQ_NONE;
852
853 for (i = 0; i < GPMC_NR_IRQ; i++)
854 if (regval & gpmc_client_irq[i].bitmask)
855 generic_handle_irq(gpmc_client_irq[i].irq);
db97eb7d 856
6b6c32fc 857 gpmc_write_reg(GPMC_IRQSTATUS, regval);
db97eb7d
SG		 858
859 return IRQ_HANDLED;
4bbbc1ad 860}
a2d3e7ba
RN		 861
862#ifdef CONFIG_ARCH_OMAP3
863static struct omap3_gpmc_regs gpmc_context;
864
b2fa3b7c 865void omap3_gpmc_save_context(void)
a2d3e7ba
RN		 866{
867 int i;
b2fa3b7c 868
a2d3e7ba
RN		 869 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
870 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
871 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
872 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
873 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
874 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
875 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
876 for (i = 0; i < GPMC_CS_NUM; i++) {
877 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
878 if (gpmc_context.cs_context[i].is_valid) {
879 gpmc_context.cs_context[i].config1 =
880 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
881 gpmc_context.cs_context[i].config2 =
882 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
883 gpmc_context.cs_context[i].config3 =
884 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
885 gpmc_context.cs_context[i].config4 =
886 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
887 gpmc_context.cs_context[i].config5 =
888 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
889 gpmc_context.cs_context[i].config6 =
890 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
891 gpmc_context.cs_context[i].config7 =
892 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
893 }
894 }
895}
896
b2fa3b7c 897void omap3_gpmc_restore_context(void)
a2d3e7ba
RN		 898{
899 int i;
b2fa3b7c 900
a2d3e7ba
RN		 901 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
902 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
903 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
904 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
905 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
906 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
907 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
908 for (i = 0; i < GPMC_CS_NUM; i++) {
909 if (gpmc_context.cs_context[i].is_valid) {
910 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
911 gpmc_context.cs_context[i].config1);
912 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
913 gpmc_context.cs_context[i].config2);
914 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
915 gpmc_context.cs_context[i].config3);
916 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
917 gpmc_context.cs_context[i].config4);
918 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
919 gpmc_context.cs_context[i].config5);
920 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
921 gpmc_context.cs_context[i].config6);
922 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
923 gpmc_context.cs_context[i].config7);
924 }
925 }
926}
927#endif /* CONFIG_ARCH_OMAP3 */
Linux kernel - Deliverables
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