ARM: OMAP2+: gpmc: handle additional timings
[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.h
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1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
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14#include <linux/platform_data/mtd-nand-omap2.h>
15
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16/* Maximum Number of Chip Selects */
17#define GPMC_CS_NUM 8
18
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19#define GPMC_CS_CONFIG1 0x00
20#define GPMC_CS_CONFIG2 0x04
21#define GPMC_CS_CONFIG3 0x08
22#define GPMC_CS_CONFIG4 0x0c
23#define GPMC_CS_CONFIG5 0x10
24#define GPMC_CS_CONFIG6 0x14
25#define GPMC_CS_CONFIG7 0x18
26#define GPMC_CS_NAND_COMMAND 0x1c
27#define GPMC_CS_NAND_ADDRESS 0x20
28#define GPMC_CS_NAND_DATA 0x24
29
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30/* Control Commands */
31#define GPMC_CONFIG_RDY_BSY 0x00000001
32#define GPMC_CONFIG_DEV_SIZE 0x00000002
33#define GPMC_CONFIG_DEV_TYPE 0x00000003
34#define GPMC_SET_IRQ_STATUS 0x00000004
35#define GPMC_CONFIG_WP 0x00000005
36
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37#define GPMC_ENABLE_IRQ 0x0000000d
38
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39/* ECC commands */
40#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
41#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
42#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
646e3ed1 43
4bbbc1ad 44#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
1c22cc13 45#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
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46#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
47#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
1c22cc13 48#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
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49#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
50#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
51#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
52#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
53#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
54#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
55#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
56#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
57#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
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61#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
65#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
66#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
a2d3e7ba 67#define GPMC_CONFIG7_CSVALID (1 << 6)
4bbbc1ad 68
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69#define GPMC_DEVICETYPE_NOR 0
70#define GPMC_DEVICETYPE_NAND 2
71#define GPMC_CONFIG_WRITEPROTECT 0x00000010
948d38e7 72#define WR_RD_PIN_MONITORING 0x00600000
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73#define GPMC_IRQ_FIFOEVENTENABLE 0x01
74#define GPMC_IRQ_COUNT_EVENT 0x02
948d38e7 75
317379a9 76
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77/* bool type time settings */
78struct gpmc_bool_timings {
79 bool cycle2cyclediffcsen;
80 bool cycle2cyclesamecsen;
81 bool we_extra_delay;
82 bool oe_extra_delay;
83 bool adv_extra_delay;
84 bool cs_extra_delay;
85 bool time_para_granularity;
86};
87
4bbbc1ad 88/*
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89 * Note that all values in this struct are in nanoseconds except sync_clk
90 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
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91 */
92struct gpmc_timings {
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93 /* Minimum clock period for synchronous mode (in picoseconds) */
94 u32 sync_clk;
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95
96 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
97 u16 cs_on; /* Assertion time */
98 u16 cs_rd_off; /* Read deassertion time */
99 u16 cs_wr_off; /* Write deassertion time */
100
101 /* ADV signal timings corresponding to GPMC_CONFIG3 */
102 u16 adv_on; /* Assertion time */
103 u16 adv_rd_off; /* Read deassertion time */
104 u16 adv_wr_off; /* Write deassertion time */
105
106 /* WE signals timings corresponding to GPMC_CONFIG4 */
107 u16 we_on; /* WE assertion time */
108 u16 we_off; /* WE deassertion time */
109
110 /* OE signals timings corresponding to GPMC_CONFIG4 */
111 u16 oe_on; /* OE assertion time */
112 u16 oe_off; /* OE deassertion time */
113
114 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
115 u16 page_burst_access; /* Multiple access word delay */
116 u16 access; /* Start-cycle to first data valid delay */
117 u16 rd_cycle; /* Total read cycle time */
118 u16 wr_cycle; /* Total write cycle time */
cc26b3b0 119
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120 u16 bus_turnaround;
121 u16 cycle2cycle_delay;
122
123 u16 wait_monitoring;
124 u16 clk_activation;
125
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126 /* The following are only on OMAP3430 */
127 u16 wr_access; /* WRACCESSTIME */
128 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
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129
130 struct gpmc_bool_timings bool_timings;
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131};
132
52bd138d 133extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
6b6c32fc 134extern int gpmc_get_client_irq(unsigned irq_config);
52bd138d 135
4bbbc1ad 136extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
a3551f5b 137extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
fd1dc87d 138extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
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139extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
140extern unsigned long gpmc_get_fclk_period(void);
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141
142extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
143extern u32 gpmc_cs_read_reg(int cs, int idx);
1b47ca1a 144extern int gpmc_calc_divider(unsigned int sync_clk);
4bbbc1ad 145extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
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146extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
147extern void gpmc_cs_free(int cs);
39b8e698 148extern int gpmc_cs_set_reserved(int cs, int reserved);
f4e4c324 149extern int gpmc_cs_reserved(int cs);
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150extern void omap3_gpmc_save_context(void);
151extern void omap3_gpmc_restore_context(void);
948d38e7 152extern int gpmc_cs_configure(int cs, int cmd, int wval);
8d602cf5 153
4bbbc1ad 154#endif
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