[deliverable/linux.git] / arch / arm / mach-omap2 / hsmmc.c

/*
 * linux/arch/arm/mach-omap2/hsmmc.c
 *
 * Copyright (C) 2007-2008 Texas Instruments
 * Copyright (C) 2008 Nokia Corporation
 * Author: Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>

#include "soc.h"
#include "omap_device.h"
#include "omap-pm.h"

#include "mux.h"
#include "mmc.h"
#include "hsmmc.h"
#include "control.h"

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)

static u16 control_pbias_offset;
static u16 control_devconf1_offset;

#define HSMMC_NAME_LEN	9

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

static int hsmmc_get_context_loss(struct device *dev)
{
	return omap_pm_get_dev_context_loss_count(dev);
}

#else
#define hsmmc_get_context_loss NULL
#endif

static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg, prog_io;
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	/*
	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
	 *
	 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	 * is most naturally TWL VSIM; those pins also use PBIAS.
	 *
	 * FIXME handle VMMC1A as needed ...
	 */
	if (power_on) {
		if (cpu_is_omap2430()) {
			reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
			if ((1 << vdd) >= MMC_VDD_30_31)
				reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
			else
				reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
		}

		if (mmc->slots[0].internal_clock) {
			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
		}

		reg = omap_ctrl_readl(control_pbias_offset);
		if (cpu_is_omap3630()) {
			/* Set MMC I/O to 52Mhz */
			prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
			prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
			omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
		} else {
			reg |= OMAP2_PBIASSPEEDCTRL0;
		}
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
				 int power_on, int vdd)
{
	u32 reg;

	/* 100ms delay required for PBIAS configuration */
	msleep(100);

	if (power_on) {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
		if ((1 << vdd) <= MMC_VDD_165_195)
			reg &= ~OMAP2_PBIASLITEVMODE0;
		else
			reg |= OMAP2_PBIASLITEVMODE0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
			OMAP2_PBIASLITEVMODE0);
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
{
	u32 reg;

	reg = omap_ctrl_readl(control_devconf1_offset);
	if (mmc->slots[0].internal_clock)
		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
	else
		reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
	omap_ctrl_writel(reg, control_devconf1_offset);
}

static void hsmmc2_before_set_reg(struct device *dev, int slot,
				   int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	if (power_on)
		hsmmc2_select_input_clk_src(mmc);
}

static int am35x_hsmmc2_set_power(struct device *dev, int slot,
				  int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (power_on)
		hsmmc2_select_input_clk_src(mmc);

	return 0;
}

static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
							int vdd)
{
	return 0;
}

static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
			int controller_nr)
{
	if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
		(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
		omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
					OMAP_PIN_INPUT_PULLUP);
	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
		(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
		omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
					OMAP_PIN_INPUT_PULLUP);
	if (cpu_is_omap34xx()) {
		if (controller_nr == 0) {
			omap_mux_init_signal("sdmmc1_clk",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc1_cmd",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc1_dat0",
				OMAP_PIN_INPUT_PULLUP);
			if (mmc_controller->slots[0].caps &
				(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
				omap_mux_init_signal("sdmmc1_dat1",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat2",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat3",
					OMAP_PIN_INPUT_PULLUP);
			}
			if (mmc_controller->slots[0].caps &
						MMC_CAP_8_BIT_DATA) {
				omap_mux_init_signal("sdmmc1_dat4",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat5",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat6",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat7",
					OMAP_PIN_INPUT_PULLUP);
			}
		}
		if (controller_nr == 1) {
			/* MMC2 */
			omap_mux_init_signal("sdmmc2_clk",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc2_cmd",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc2_dat0",
				OMAP_PIN_INPUT_PULLUP);

			/*
			 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
			 * need to be muxed in the board-*.c files
			 */
			if (mmc_controller->slots[0].caps &
				(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
				omap_mux_init_signal("sdmmc2_dat1",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat2",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat3",
					OMAP_PIN_INPUT_PULLUP);
			}
			if (mmc_controller->slots[0].caps &
							MMC_CAP_8_BIT_DATA) {
				omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
					OMAP_PIN_INPUT_PULLUP);
			}
		}

		/*
		 * For MMC3 the pins need to be muxed in the board-*.c files
		 */
	}
}

static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
					struct omap_mmc_platform_data *mmc)
{
	char *hc_name;

	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
	if (!hc_name) {
		pr_err("Cannot allocate memory for controller slot name\n");
		kfree(hc_name);
		return -ENOMEM;
	}

	if (c->name)
		strncpy(hc_name, c->name, HSMMC_NAME_LEN);
	else
		snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
								c->mmc, 1);
	mmc->slots[0].name = hc_name;
	mmc->nr_slots = 1;
	mmc->slots[0].caps = c->caps;
	mmc->slots[0].pm_caps = c->pm_caps;
	mmc->slots[0].internal_clock = !c->ext_clock;
	mmc->max_freq = c->max_freq;
	mmc->reg_offset = 0;
	mmc->get_context_loss_count = hsmmc_get_context_loss;

	mmc->slots[0].switch_pin = c->gpio_cd;
	mmc->slots[0].gpio_wp = c->gpio_wp;

	mmc->slots[0].remux = c->remux;
	mmc->slots[0].init_card = c->init_card;

	if (c->cover_only)
		mmc->slots[0].cover = 1;

	if (c->nonremovable)
		mmc->slots[0].nonremovable = 1;

	if (c->power_saving)
		mmc->slots[0].power_saving = 1;

	if (c->no_off)
		mmc->slots[0].no_off = 1;

	if (c->no_off_init)
		mmc->slots[0].no_regulator_off_init = c->no_off_init;

	if (c->vcc_aux_disable_is_sleep)
		mmc->slots[0].vcc_aux_disable_is_sleep = 1;

	/*
	 * NOTE:  MMC slots should have a Vcc regulator set up.
	 * This may be from a TWL4030-family chip, another
	 * controllable regulator, or a fixed supply.
	 *
	 * temporary HACK: ocr_mask instead of fixed supply
	 */
	if (soc_is_am35xx())
		mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
					 MMC_VDD_26_27 |
					 MMC_VDD_27_28 |
					 MMC_VDD_29_30 |
					 MMC_VDD_30_31 |
					 MMC_VDD_31_32;
	else
		mmc->slots[0].ocr_mask = c->ocr_mask;

	if (!soc_is_am35xx())
		mmc->slots[0].features |= HSMMC_HAS_PBIAS;

	switch (c->mmc) {
	case 1:
		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
			/* on-chip level shifting via PBIAS0/PBIAS1 */
			mmc->slots[0].before_set_reg =
					omap_hsmmc1_before_set_reg;
			mmc->slots[0].after_set_reg =
					omap_hsmmc1_after_set_reg;
		}

		if (soc_is_am35xx())
			mmc->slots[0].set_power = nop_mmc_set_power;

		/* OMAP3630 HSMMC1 supports only 4-bit */
		if (cpu_is_omap3630() &&
				(c->caps & MMC_CAP_8_BIT_DATA)) {
			c->caps &= ~MMC_CAP_8_BIT_DATA;
			c->caps |= MMC_CAP_4_BIT_DATA;
			mmc->slots[0].caps = c->caps;
		}
		break;
	case 2:
		if (soc_is_am35xx())
			mmc->slots[0].set_power = am35x_hsmmc2_set_power;

		if (c->ext_clock)
			c->transceiver = 1;
		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
			c->caps &= ~MMC_CAP_8_BIT_DATA;
			c->caps |= MMC_CAP_4_BIT_DATA;
		}
		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
			/* off-chip level shifting, or none */
			mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
			mmc->slots[0].after_set_reg = NULL;
		}
		break;
	case 3:
	case 4:
	case 5:
		mmc->slots[0].before_set_reg = NULL;
		mmc->slots[0].after_set_reg = NULL;
		break;
	default:
		pr_err("MMC%d configuration not supported!\n", c->mmc);
		kfree(hc_name);
		return -ENODEV;
	}
	return 0;
}

static int omap_hsmmc_done;

void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
{
	struct platform_device *pdev;
	struct omap_mmc_platform_data *mmc_pdata;
	int res;

	if (omap_hsmmc_done != 1)
		return;

	omap_hsmmc_done++;

	for (; c->mmc; c++) {
		if (!c->deferred)
			continue;

		pdev = c->pdev;
		if (!pdev)
			continue;

		mmc_pdata = pdev->dev.platform_data;
		if (!mmc_pdata)
			continue;

		mmc_pdata->slots[0].switch_pin = c->gpio_cd;
		mmc_pdata->slots[0].gpio_wp = c->gpio_wp;

		res = omap_device_register(pdev);
		if (res)
			pr_err("Could not late init MMC %s\n",
			       c->name);
	}
}

#define MAX_OMAP_MMC_HWMOD_NAME_LEN		16

static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
					int ctrl_nr)
{
	struct omap_hwmod *oh;
	struct omap_hwmod *ohs[1];
	struct omap_device *od;
	struct platform_device *pdev;
	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
	struct omap_mmc_platform_data *mmc_data;
	struct omap_mmc_dev_attr *mmc_dev_attr;
	char *name;
	int res;

	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
	if (!mmc_data) {
		pr_err("Cannot allocate memory for mmc device!\n");
		return;
	}

	res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
	if (res < 0)
		goto free_mmc;

	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));

	name = "omap_hsmmc";
	res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
		     "mmc%d", ctrl_nr);
	WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
	     "String buffer overflow in MMC%d device setup\n", ctrl_nr);

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		goto free_name;
	}
	ohs[0] = oh;
	if (oh->dev_attr != NULL) {
		mmc_dev_attr = oh->dev_attr;
		mmc_data->controller_flags = mmc_dev_attr->flags;
		/*
		 * erratum 2.1.1.128 doesn't apply if board has
		 * a transceiver is attached
		 */
		if (hsmmcinfo->transceiver)
			mmc_data->controller_flags &=
				~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
	}

	pdev = platform_device_alloc(name, ctrl_nr - 1);
	if (!pdev) {
		pr_err("Could not allocate pdev for %s\n", name);
		goto free_name;
	}
	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);

	od = omap_device_alloc(pdev, ohs, 1);
	if (IS_ERR(od)) {
		pr_err("Could not allocate od for %s\n", name);
		goto put_pdev;
	}

	res = platform_device_add_data(pdev, mmc_data,
			      sizeof(struct omap_mmc_platform_data));
	if (res) {
		pr_err("Could not add pdata for %s\n", name);
		goto put_pdev;
	}

	hsmmcinfo->pdev = pdev;

	if (hsmmcinfo->deferred)
		goto free_mmc;

	res = omap_device_register(pdev);
	if (res) {
		pr_err("Could not register od for %s\n", name);
		goto free_od;
	}

	goto free_mmc;

free_od:
	omap_device_delete(od);

put_pdev:
	platform_device_put(pdev);

free_name:
	kfree(mmc_data->slots[0].name);

free_mmc:
	kfree(mmc_data);
}

void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	if (omap_hsmmc_done)
		return;

	omap_hsmmc_done = 1;

	if (cpu_is_omap2430()) {
		control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
		control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
	} else {
		control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
		control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
	}

	for (; controllers->mmc; controllers++)
		omap_hsmmc_init_one(controllers, controllers->mmc);

}

#endif
Commit	Line	Data
90c62bf0	1	/*
d02a900b	2	* linux/arch/arm/mach-omap2/hsmmc.c
90c62bf0 TL	3	*
	4	* Copyright (C) 2007-2008 Texas Instruments
	5	* Copyright (C) 2008 Nokia Corporation
	6	* Author: Texas Instruments
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
db0fefc5 AH	12	#include <linux/kernel.h>
	13	#include <linux/slab.h>
	14	#include <linux/string.h>
90c62bf0	15	#include <linux/delay.h>
5e4698fc	16	#include <linux/gpio.h>
4b25408f TL	17	#include <linux/platform_data/gpio-omap.h>
4b25408f TL	18
e4c060db	19	#include "soc.h"
25c7d49e	20	#include "omap_device.h"
1d5aef49	21	#include "omap-pm.h"
90c62bf0	22
d8d0a61c	23	#include "mux.h"
68f39e74	24	#include "mmc.h"
d02a900b	25	#include "hsmmc.h"
4814ced5	26	#include "control.h"
90c62bf0	27
db0fefc5	28	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
90c62bf0 TL	29
	30	static u16 control_pbias_offset;
	31	static u16 control_devconf1_offset;
	32
	33	#define HSMMC_NAME_LEN 9
	34
1887bde3 DK	35	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
1887bde3 DK	36
68ff0423	37	static int hsmmc_get_context_loss(struct device *dev)
1887bde3	38	{
e3df0fb4	39	return omap_pm_get_dev_context_loss_count(dev);
1887bde3 DK	40	}
	41
	42	#else
68ff0423	43	#define hsmmc_get_context_loss NULL
1887bde3 DK	44	#endif
1887bde3 DK	45
c83c8e6c	46	static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
db0fefc5	47	int power_on, int vdd)
90c62bf0	48	{
555d503f	49	u32 reg, prog_io;
90c62bf0 TL	50	struct omap_mmc_platform_data *mmc = dev->platform_data;
90c62bf0 TL	51
ce6f0016 AH	52	if (mmc->slots[0].remux)
	53	mmc->slots[0].remux(dev, slot, power_on);
	54
0329c377 DB	55	/*
0329c377 DB	56	* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
b583f26d	57	* card with Vcc regulator (from twl4030 or whatever). OMAP has both
0329c377 DB	58	* 1.8V and 3.0V modes, controlled by the PBIAS register.
	59	*
	60	* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	61	* is most naturally TWL VSIM; those pins also use PBIAS.
b583f26d DB	62	*
b583f26d DB	63	* FIXME handle VMMC1A as needed ...
0329c377	64	*/
90c62bf0 TL	65	if (power_on) {
	66	if (cpu_is_omap2430()) {
	67	reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
	68	if ((1 << vdd) >= MMC_VDD_30_31)
	69	reg \|= OMAP243X_MMC1_ACTIVE_OVERWRITE;
	70	else
	71	reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
	72	omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
	73	}
	74
	75	if (mmc->slots[0].internal_clock) {
	76	reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	77	reg \|= OMAP2_MMCSDIO1ADPCLKISEL;
	78	omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
	79	}
	80
	81	reg = omap_ctrl_readl(control_pbias_offset);
555d503f M	82	if (cpu_is_omap3630()) {
	83	/* Set MMC I/O to 52Mhz */
	84	prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	85	prog_io \|= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
	86	omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
	87	} else {
	88	reg \|= OMAP2_PBIASSPEEDCTRL0;
	89	}
90c62bf0 TL	90	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
90c62bf0 TL	91	omap_ctrl_writel(reg, control_pbias_offset);
db0fefc5 AH	92	} else {
	93	reg = omap_ctrl_readl(control_pbias_offset);
	94	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
	95	omap_ctrl_writel(reg, control_pbias_offset);
	96	}
	97	}
	98
c83c8e6c	99	static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
db0fefc5 AH	100	int power_on, int vdd)
	101	{
	102	u32 reg;
90c62bf0	103
db0fefc5 AH	104	/* 100ms delay required for PBIAS configuration */
db0fefc5 AH	105	msleep(100);
90c62bf0	106
db0fefc5	107	if (power_on) {
90c62bf0 TL	108	reg = omap_ctrl_readl(control_pbias_offset);
	109	reg \|= (OMAP2_PBIASLITEPWRDNZ0 \| OMAP2_PBIASSPEEDCTRL0);
	110	if ((1 << vdd) <= MMC_VDD_165_195)
	111	reg &= ~OMAP2_PBIASLITEVMODE0;
	112	else
	113	reg \|= OMAP2_PBIASLITEVMODE0;
	114	omap_ctrl_writel(reg, control_pbias_offset);
	115	} else {
90c62bf0 TL	116	reg = omap_ctrl_readl(control_pbias_offset);
	117	reg \|= (OMAP2_PBIASSPEEDCTRL0 \| OMAP2_PBIASLITEPWRDNZ0 \|
	118	OMAP2_PBIASLITEVMODE0);
	119	omap_ctrl_writel(reg, control_pbias_offset);
	120	}
90c62bf0 TL	121	}
90c62bf0 TL	122
e62245ba IG	123	static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
	124	{
	125	u32 reg;
	126
d82e5190 GI	127	reg = omap_ctrl_readl(control_devconf1_offset);
d82e5190 GI	128	if (mmc->slots[0].internal_clock)
e62245ba	129	reg \|= OMAP2_MMCSDIO2ADPCLKISEL;
d82e5190 GI	130	else
	131	reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
	132	omap_ctrl_writel(reg, control_devconf1_offset);
e62245ba IG	133	}
e62245ba IG	134
ffa1e4ed	135	static void hsmmc2_before_set_reg(struct device *dev, int slot,
db0fefc5	136	int power_on, int vdd)
90c62bf0	137	{
90c62bf0	138	struct omap_mmc_platform_data *mmc = dev->platform_data;
b583f26d	139
ce6f0016 AH	140	if (mmc->slots[0].remux)
	141	mmc->slots[0].remux(dev, slot, power_on);
	142
e62245ba IG	143	if (power_on)
	144	hsmmc2_select_input_clk_src(mmc);
	145	}
90c62bf0	146
e62245ba IG	147	static int am35x_hsmmc2_set_power(struct device *dev, int slot,
	148	int power_on, int vdd)
	149	{
	150	struct omap_mmc_platform_data *mmc = dev->platform_data;
	151
	152	if (power_on)
	153	hsmmc2_select_input_clk_src(mmc);
	154
	155	return 0;
9b7c18e0 AH	156	}
9b7c18e0 AH	157
03e7e170	158	static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
	159	int vdd)
	160	{
	161	return 0;
	162	}
	163
d8d0a61c KK	164	static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
	165	int controller_nr)
	166	{
a15164f1 TW	167	if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
a15164f1 TW	168	(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
d8d0a61c KK	169	omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
d8d0a61c KK	170	OMAP_PIN_INPUT_PULLUP);
a15164f1 TW	171	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
a15164f1 TW	172	(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
d8d0a61c KK	173	omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
	174	OMAP_PIN_INPUT_PULLUP);
	175	if (cpu_is_omap34xx()) {
	176	if (controller_nr == 0) {
	177	omap_mux_init_signal("sdmmc1_clk",
	178	OMAP_PIN_INPUT_PULLUP);
	179	omap_mux_init_signal("sdmmc1_cmd",
	180	OMAP_PIN_INPUT_PULLUP);
	181	omap_mux_init_signal("sdmmc1_dat0",
	182	OMAP_PIN_INPUT_PULLUP);
	183	if (mmc_controller->slots[0].caps &
	184	(MMC_CAP_4_BIT_DATA \| MMC_CAP_8_BIT_DATA)) {
	185	omap_mux_init_signal("sdmmc1_dat1",
	186	OMAP_PIN_INPUT_PULLUP);
	187	omap_mux_init_signal("sdmmc1_dat2",
	188	OMAP_PIN_INPUT_PULLUP);
	189	omap_mux_init_signal("sdmmc1_dat3",
	190	OMAP_PIN_INPUT_PULLUP);
	191	}
	192	if (mmc_controller->slots[0].caps &
	193	MMC_CAP_8_BIT_DATA) {
	194	omap_mux_init_signal("sdmmc1_dat4",
	195	OMAP_PIN_INPUT_PULLUP);
	196	omap_mux_init_signal("sdmmc1_dat5",
	197	OMAP_PIN_INPUT_PULLUP);
	198	omap_mux_init_signal("sdmmc1_dat6",
	199	OMAP_PIN_INPUT_PULLUP);
	200	omap_mux_init_signal("sdmmc1_dat7",
	201	OMAP_PIN_INPUT_PULLUP);
	202	}
	203	}
	204	if (controller_nr == 1) {
	205	/* MMC2 */
	206	omap_mux_init_signal("sdmmc2_clk",
	207	OMAP_PIN_INPUT_PULLUP);
	208	omap_mux_init_signal("sdmmc2_cmd",
	209	OMAP_PIN_INPUT_PULLUP);
	210	omap_mux_init_signal("sdmmc2_dat0",
	211	OMAP_PIN_INPUT_PULLUP);
	212
	213	/*
	214	* For 8 wire configurations, Lines DAT4, 5, 6 and 7
	215	* need to be muxed in the board-*.c files
	216	*/
	217	if (mmc_controller->slots[0].caps &
	218	(MMC_CAP_4_BIT_DATA \| MMC_CAP_8_BIT_DATA)) {
	219	omap_mux_init_signal("sdmmc2_dat1",
	220	OMAP_PIN_INPUT_PULLUP);
	221	omap_mux_init_signal("sdmmc2_dat2",
	222	OMAP_PIN_INPUT_PULLUP);
	223	omap_mux_init_signal("sdmmc2_dat3",
	224	OMAP_PIN_INPUT_PULLUP);
	225	}
	226	if (mmc_controller->slots[0].caps &
	227	MMC_CAP_8_BIT_DATA) {
	228	omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
	229	OMAP_PIN_INPUT_PULLUP);
	230	omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
	231	OMAP_PIN_INPUT_PULLUP);
	232	omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
	233	OMAP_PIN_INPUT_PULLUP);
	234	omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
	235	OMAP_PIN_INPUT_PULLUP);
	236	}
237	}
238
239	/*
240	* For MMC3 the pins need to be muxed in the board-*.c files
241	*/
242	}
243	}
244
d1589f09 TL	245	static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
d1589f09 TL	246	struct omap_mmc_platform_data *mmc)
4621d5f8 KK	247	{
	248	char *hc_name;
	249
	250	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
	251	if (!hc_name) {
	252	pr_err("Cannot allocate memory for controller slot name\n");
	253	kfree(hc_name);
	254	return -ENOMEM;
	255	}
	256
	257	if (c->name)
	258	strncpy(hc_name, c->name, HSMMC_NAME_LEN);
	259	else
	260	snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
	261	c->mmc, 1);
	262	mmc->slots[0].name = hc_name;
	263	mmc->nr_slots = 1;
	264	mmc->slots[0].caps = c->caps;
6fdc75de	265	mmc->slots[0].pm_caps = c->pm_caps;
4621d5f8	266	mmc->slots[0].internal_clock = !c->ext_clock;
d418ed87	267	mmc->max_freq = c->max_freq;
b30e321b	268	mmc->reg_offset = 0;
4621d5f8 KK	269	mmc->get_context_loss_count = hsmmc_get_context_loss;
	270
	271	mmc->slots[0].switch_pin = c->gpio_cd;
	272	mmc->slots[0].gpio_wp = c->gpio_wp;
	273
	274	mmc->slots[0].remux = c->remux;
	275	mmc->slots[0].init_card = c->init_card;
	276
	277	if (c->cover_only)
	278	mmc->slots[0].cover = 1;
	279
	280	if (c->nonremovable)
	281	mmc->slots[0].nonremovable = 1;
	282
	283	if (c->power_saving)
	284	mmc->slots[0].power_saving = 1;
	285
	286	if (c->no_off)
	287	mmc->slots[0].no_off = 1;
	288
b1c1df7a B	289	if (c->no_off_init)
	290	mmc->slots[0].no_regulator_off_init = c->no_off_init;
	291
4621d5f8 KK	292	if (c->vcc_aux_disable_is_sleep)
	293	mmc->slots[0].vcc_aux_disable_is_sleep = 1;
	294
	295	/*
	296	* NOTE: MMC slots should have a Vcc regulator set up.
	297	* This may be from a TWL4030-family chip, another
	298	* controllable regulator, or a fixed supply.
	299	*
	300	* temporary HACK: ocr_mask instead of fixed supply
	301	*/
68a88b98	302	if (soc_is_am35xx())
e89715a7 A	303	mmc->slots[0].ocr_mask = MMC_VDD_165_195 \|
	304	MMC_VDD_26_27 \|
	305	MMC_VDD_27_28 \|
	306	MMC_VDD_29_30 \|
	307	MMC_VDD_30_31 \|
	308	MMC_VDD_31_32;
	309	else
	310	mmc->slots[0].ocr_mask = c->ocr_mask;
4621d5f8	311
68a88b98	312	if (!soc_is_am35xx())
4621d5f8 KK	313	mmc->slots[0].features \|= HSMMC_HAS_PBIAS;
4621d5f8 KK	314
4621d5f8 KK	315	switch (c->mmc) {
	316	case 1:
	317	if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
	318	/* on-chip level shifting via PBIAS0/PBIAS1 */
b30e321b TL	319	mmc->slots[0].before_set_reg =
	320	omap_hsmmc1_before_set_reg;
	321	mmc->slots[0].after_set_reg =
	322	omap_hsmmc1_after_set_reg;
4621d5f8 KK	323	}
4621d5f8 KK	324
68a88b98	325	if (soc_is_am35xx())
e62245ba IG	326	mmc->slots[0].set_power = nop_mmc_set_power;
e62245ba IG	327
4621d5f8 KK	328	/* OMAP3630 HSMMC1 supports only 4-bit */
	329	if (cpu_is_omap3630() &&
	330	(c->caps & MMC_CAP_8_BIT_DATA)) {
	331	c->caps &= ~MMC_CAP_8_BIT_DATA;
	332	c->caps \|= MMC_CAP_4_BIT_DATA;
	333	mmc->slots[0].caps = c->caps;
	334	}
	335	break;
	336	case 2:
68a88b98	337	if (soc_is_am35xx())
e62245ba IG	338	mmc->slots[0].set_power = am35x_hsmmc2_set_power;
e62245ba IG	339
4621d5f8 KK	340	if (c->ext_clock)
	341	c->transceiver = 1;
	342	if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
	343	c->caps &= ~MMC_CAP_8_BIT_DATA;
	344	c->caps \|= MMC_CAP_4_BIT_DATA;
	345	}
4621d5f8 KK	346	if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
4621d5f8 KK	347	/* off-chip level shifting, or none */
ffa1e4ed	348	mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
4621d5f8 KK	349	mmc->slots[0].after_set_reg = NULL;
	350	}
	351	break;
ffa1e4ed	352	case 3:
4621d5f8 KK	353	case 4:
	354	case 5:
	355	mmc->slots[0].before_set_reg = NULL;
	356	mmc->slots[0].after_set_reg = NULL;
	357	break;
	358	default:
	359	pr_err("MMC%d configuration not supported!\n", c->mmc);
	360	kfree(hc_name);
	361	return -ENODEV;
	362	}
	363	return 0;
	364	}
	365
97899e55	366	static int omap_hsmmc_done;
3b972bf0 TL	367
	368	void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
	369	{
	370	struct platform_device *pdev;
	371	struct omap_mmc_platform_data *mmc_pdata;
	372	int res;
	373
	374	if (omap_hsmmc_done != 1)
	375	return;
	376
	377	omap_hsmmc_done++;
	378
	379	for (; c->mmc; c++) {
	380	if (!c->deferred)
	381	continue;
	382
	383	pdev = c->pdev;
	384	if (!pdev)
	385	continue;
	386
	387	mmc_pdata = pdev->dev.platform_data;
	388	if (!mmc_pdata)
	389	continue;
	390
	391	mmc_pdata->slots[0].switch_pin = c->gpio_cd;
	392	mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
	393
	394	res = omap_device_register(pdev);
	395	if (res)
	396	pr_err("Could not late init MMC %s\n",
	397	c->name);
	398	}
	399	}
	400
4621d5f8 KK	401	#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
4621d5f8 KK	402
6028505c	403	static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
3b972bf0	404	int ctrl_nr)
4621d5f8 KK	405	{
4621d5f8 KK	406	struct omap_hwmod *oh;
3b972bf0 TL	407	struct omap_hwmod *ohs[1];
3b972bf0 TL	408	struct omap_device *od;
3528c58e	409	struct platform_device *pdev;
4621d5f8 KK	410	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
	411	struct omap_mmc_platform_data *mmc_data;
	412	struct omap_mmc_dev_attr *mmc_dev_attr;
	413	char *name;
3b972bf0	414	int res;
4621d5f8 KK	415
	416	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
	417	if (!mmc_data) {
	418	pr_err("Cannot allocate memory for mmc device!\n");
3b972bf0	419	return;
4621d5f8 KK	420	}
4621d5f8 KK	421
3b972bf0 TL	422	res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
	423	if (res < 0)
	424	goto free_mmc;
	425
4621d5f8 KK	426	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
4621d5f8 KK	427
0005ae73	428	name = "omap_hsmmc";
3b972bf0	429	res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
4621d5f8	430	"mmc%d", ctrl_nr);
3b972bf0	431	WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
4621d5f8	432	"String buffer overflow in MMC%d device setup\n", ctrl_nr);
3b972bf0	433
4621d5f8 KK	434	oh = omap_hwmod_lookup(oh_name);
	435	if (!oh) {
	436	pr_err("Could not look up %s\n", oh_name);
3b972bf0	437	goto free_name;
4621d5f8	438	}
3b972bf0	439	ohs[0] = oh;
4621d5f8 KK	440	if (oh->dev_attr != NULL) {
	441	mmc_dev_attr = oh->dev_attr;
	442	mmc_data->controller_flags = mmc_dev_attr->flags;
26c547fd GI	443	/*
	444	* erratum 2.1.1.128 doesn't apply if board has
	445	* a transceiver is attached
	446	*/
	447	if (hsmmcinfo->transceiver)
	448	mmc_data->controller_flags &=
	449	~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
4621d5f8 KK	450	}
4621d5f8 KK	451
3b972bf0 TL	452	pdev = platform_device_alloc(name, ctrl_nr - 1);
	453	if (!pdev) {
	454	pr_err("Could not allocate pdev for %s\n", name);
	455	goto free_name;
4621d5f8	456	}
3b972bf0 TL	457	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
3b972bf0 TL	458
c1d1cd59	459	od = omap_device_alloc(pdev, ohs, 1);
64de3a00	460	if (IS_ERR(od)) {
3b972bf0 TL	461	pr_err("Could not allocate od for %s\n", name);
	462	goto put_pdev;
	463	}
	464
	465	res = platform_device_add_data(pdev, mmc_data,
	466	sizeof(struct omap_mmc_platform_data));
	467	if (res) {
	468	pr_err("Could not add pdata for %s\n", name);
	469	goto put_pdev;
	470	}
	471
	472	hsmmcinfo->pdev = pdev;
	473
	474	if (hsmmcinfo->deferred)
	475	goto free_mmc;
	476
	477	res = omap_device_register(pdev);
	478	if (res) {
	479	pr_err("Could not register od for %s\n", name);
	480	goto free_od;
	481	}
	482
	483	goto free_mmc;
	484
	485	free_od:
	486	omap_device_delete(od);
	487
	488	put_pdev:
	489	platform_device_put(pdev);
	490
	491	free_name:
	492	kfree(mmc_data->slots[0].name);
4621d5f8	493
3b972bf0	494	free_mmc:
4621d5f8 KK	495	kfree(mmc_data);
4621d5f8 KK	496	}
90c62bf0	497
d1589f09	498	void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
90c62bf0	499	{
97899e55 TL	500	if (omap_hsmmc_done)
	501	return;
	502
	503	omap_hsmmc_done = 1;
	504
b30e321b TL	505	if (cpu_is_omap2430()) {
	506	control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
	507	control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
90c62bf0	508	} else {
b30e321b TL	509	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
b30e321b TL	510	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
90c62bf0 TL	511	}
90c62bf0 TL	512
4621d5f8	513	for (; controllers->mmc; controllers++)
3b972bf0	514	omap_hsmmc_init_one(controllers, controllers->mmc);
01971f65	515
90c62bf0 TL	516	}
	517
	518	#endif