Commit | Line | Data |
---|---|---|
90c62bf0 | 1 | /* |
d02a900b | 2 | * linux/arch/arm/mach-omap2/hsmmc.c |
90c62bf0 TL |
3 | * |
4 | * Copyright (C) 2007-2008 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Author: Texas Instruments | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
db0fefc5 AH |
12 | #include <linux/kernel.h> |
13 | #include <linux/slab.h> | |
14 | #include <linux/string.h> | |
90c62bf0 | 15 | #include <linux/delay.h> |
5e4698fc | 16 | #include <linux/gpio.h> |
4b25408f TL |
17 | #include <linux/platform_data/gpio-omap.h> |
18 | ||
e4c060db | 19 | #include "soc.h" |
25c7d49e | 20 | #include "omap_device.h" |
1d5aef49 | 21 | #include "omap-pm.h" |
90c62bf0 | 22 | |
d8d0a61c | 23 | #include "mux.h" |
68f39e74 | 24 | #include "mmc.h" |
d02a900b | 25 | #include "hsmmc.h" |
4814ced5 | 26 | #include "control.h" |
90c62bf0 | 27 | |
db0fefc5 | 28 | #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) |
90c62bf0 TL |
29 | |
30 | static u16 control_pbias_offset; | |
31 | static u16 control_devconf1_offset; | |
c83c8e6c | 32 | static u16 control_mmc1; |
90c62bf0 TL |
33 | |
34 | #define HSMMC_NAME_LEN 9 | |
35 | ||
1887bde3 DK |
36 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
37 | ||
68ff0423 | 38 | static int hsmmc_get_context_loss(struct device *dev) |
1887bde3 | 39 | { |
e3df0fb4 | 40 | return omap_pm_get_dev_context_loss_count(dev); |
1887bde3 DK |
41 | } |
42 | ||
43 | #else | |
68ff0423 | 44 | #define hsmmc_get_context_loss NULL |
1887bde3 DK |
45 | #endif |
46 | ||
c83c8e6c | 47 | static void omap_hsmmc1_before_set_reg(struct device *dev, int slot, |
db0fefc5 | 48 | int power_on, int vdd) |
90c62bf0 | 49 | { |
555d503f | 50 | u32 reg, prog_io; |
90c62bf0 TL |
51 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
52 | ||
ce6f0016 AH |
53 | if (mmc->slots[0].remux) |
54 | mmc->slots[0].remux(dev, slot, power_on); | |
55 | ||
0329c377 DB |
56 | /* |
57 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | |
b583f26d | 58 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both |
0329c377 DB |
59 | * 1.8V and 3.0V modes, controlled by the PBIAS register. |
60 | * | |
61 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | |
62 | * is most naturally TWL VSIM; those pins also use PBIAS. | |
b583f26d DB |
63 | * |
64 | * FIXME handle VMMC1A as needed ... | |
0329c377 | 65 | */ |
90c62bf0 TL |
66 | if (power_on) { |
67 | if (cpu_is_omap2430()) { | |
68 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | |
69 | if ((1 << vdd) >= MMC_VDD_30_31) | |
70 | reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
71 | else | |
72 | reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
73 | omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); | |
74 | } | |
75 | ||
76 | if (mmc->slots[0].internal_clock) { | |
77 | reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
78 | reg |= OMAP2_MMCSDIO1ADPCLKISEL; | |
79 | omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); | |
80 | } | |
81 | ||
82 | reg = omap_ctrl_readl(control_pbias_offset); | |
555d503f M |
83 | if (cpu_is_omap3630()) { |
84 | /* Set MMC I/O to 52Mhz */ | |
85 | prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | |
86 | prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; | |
87 | omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); | |
88 | } else { | |
89 | reg |= OMAP2_PBIASSPEEDCTRL0; | |
90 | } | |
90c62bf0 TL |
91 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; |
92 | omap_ctrl_writel(reg, control_pbias_offset); | |
db0fefc5 AH |
93 | } else { |
94 | reg = omap_ctrl_readl(control_pbias_offset); | |
95 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | |
96 | omap_ctrl_writel(reg, control_pbias_offset); | |
97 | } | |
98 | } | |
99 | ||
c83c8e6c | 100 | static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, |
db0fefc5 AH |
101 | int power_on, int vdd) |
102 | { | |
103 | u32 reg; | |
90c62bf0 | 104 | |
db0fefc5 AH |
105 | /* 100ms delay required for PBIAS configuration */ |
106 | msleep(100); | |
90c62bf0 | 107 | |
db0fefc5 | 108 | if (power_on) { |
90c62bf0 TL |
109 | reg = omap_ctrl_readl(control_pbias_offset); |
110 | reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); | |
111 | if ((1 << vdd) <= MMC_VDD_165_195) | |
112 | reg &= ~OMAP2_PBIASLITEVMODE0; | |
113 | else | |
114 | reg |= OMAP2_PBIASLITEVMODE0; | |
115 | omap_ctrl_writel(reg, control_pbias_offset); | |
116 | } else { | |
90c62bf0 TL |
117 | reg = omap_ctrl_readl(control_pbias_offset); |
118 | reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | | |
119 | OMAP2_PBIASLITEVMODE0); | |
120 | omap_ctrl_writel(reg, control_pbias_offset); | |
121 | } | |
90c62bf0 TL |
122 | } |
123 | ||
c83c8e6c | 124 | static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, |
125 | int power_on, int vdd) | |
126 | { | |
127 | u32 reg; | |
128 | ||
129 | /* | |
130 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | |
131 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both | |
132 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | |
c83c8e6c | 133 | */ |
dcf5ef3f SS |
134 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
135 | reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | |
ff2beb1d B |
136 | OMAP4_MMC1_PWRDNZ_MASK | |
137 | OMAP4_MMC1_PBIASLITE_VMODE_MASK); | |
dcf5ef3f | 138 | omap4_ctrl_pad_writel(reg, control_pbias_offset); |
c83c8e6c | 139 | } |
140 | ||
141 | static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, | |
142 | int power_on, int vdd) | |
143 | { | |
144 | u32 reg; | |
1fcecf28 | 145 | unsigned long timeout; |
c83c8e6c | 146 | |
147 | if (power_on) { | |
dcf5ef3f SS |
148 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
149 | reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; | |
c83c8e6c | 150 | if ((1 << vdd) <= MMC_VDD_165_195) |
dcf5ef3f | 151 | reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; |
c83c8e6c | 152 | else |
dcf5ef3f SS |
153 | reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; |
154 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | |
3696d303 | 155 | OMAP4_MMC1_PWRDNZ_MASK); |
dcf5ef3f | 156 | omap4_ctrl_pad_writel(reg, control_pbias_offset); |
1fcecf28 B |
157 | |
158 | timeout = jiffies + msecs_to_jiffies(5); | |
159 | do { | |
160 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | |
161 | if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK)) | |
162 | break; | |
163 | usleep_range(100, 200); | |
164 | } while (!time_after(jiffies, timeout)); | |
165 | ||
dcf5ef3f | 166 | if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { |
c83c8e6c | 167 | pr_err("Pbias Voltage is not same as LDO\n"); |
168 | /* Caution : On VMODE_ERROR Power Down MMC IO */ | |
3696d303 | 169 | reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); |
dcf5ef3f | 170 | omap4_ctrl_pad_writel(reg, control_pbias_offset); |
c83c8e6c | 171 | } |
c83c8e6c | 172 | } |
173 | } | |
174 | ||
e62245ba IG |
175 | static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) |
176 | { | |
177 | u32 reg; | |
178 | ||
d82e5190 GI |
179 | reg = omap_ctrl_readl(control_devconf1_offset); |
180 | if (mmc->slots[0].internal_clock) | |
e62245ba | 181 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; |
d82e5190 GI |
182 | else |
183 | reg &= ~OMAP2_MMCSDIO2ADPCLKISEL; | |
184 | omap_ctrl_writel(reg, control_devconf1_offset); | |
e62245ba IG |
185 | } |
186 | ||
ffa1e4ed | 187 | static void hsmmc2_before_set_reg(struct device *dev, int slot, |
db0fefc5 | 188 | int power_on, int vdd) |
90c62bf0 | 189 | { |
90c62bf0 | 190 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
b583f26d | 191 | |
ce6f0016 AH |
192 | if (mmc->slots[0].remux) |
193 | mmc->slots[0].remux(dev, slot, power_on); | |
194 | ||
e62245ba IG |
195 | if (power_on) |
196 | hsmmc2_select_input_clk_src(mmc); | |
197 | } | |
90c62bf0 | 198 | |
e62245ba IG |
199 | static int am35x_hsmmc2_set_power(struct device *dev, int slot, |
200 | int power_on, int vdd) | |
201 | { | |
202 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
203 | ||
204 | if (power_on) | |
205 | hsmmc2_select_input_clk_src(mmc); | |
206 | ||
207 | return 0; | |
9b7c18e0 AH |
208 | } |
209 | ||
03e7e170 | 210 | static int nop_mmc_set_power(struct device *dev, int slot, int power_on, |
211 | int vdd) | |
212 | { | |
213 | return 0; | |
214 | } | |
215 | ||
d8d0a61c KK |
216 | static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, |
217 | int controller_nr) | |
218 | { | |
a15164f1 TW |
219 | if (gpio_is_valid(mmc_controller->slots[0].switch_pin) && |
220 | (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) | |
d8d0a61c KK |
221 | omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, |
222 | OMAP_PIN_INPUT_PULLUP); | |
a15164f1 TW |
223 | if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) && |
224 | (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) | |
d8d0a61c KK |
225 | omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, |
226 | OMAP_PIN_INPUT_PULLUP); | |
227 | if (cpu_is_omap34xx()) { | |
228 | if (controller_nr == 0) { | |
229 | omap_mux_init_signal("sdmmc1_clk", | |
230 | OMAP_PIN_INPUT_PULLUP); | |
231 | omap_mux_init_signal("sdmmc1_cmd", | |
232 | OMAP_PIN_INPUT_PULLUP); | |
233 | omap_mux_init_signal("sdmmc1_dat0", | |
234 | OMAP_PIN_INPUT_PULLUP); | |
235 | if (mmc_controller->slots[0].caps & | |
236 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
237 | omap_mux_init_signal("sdmmc1_dat1", | |
238 | OMAP_PIN_INPUT_PULLUP); | |
239 | omap_mux_init_signal("sdmmc1_dat2", | |
240 | OMAP_PIN_INPUT_PULLUP); | |
241 | omap_mux_init_signal("sdmmc1_dat3", | |
242 | OMAP_PIN_INPUT_PULLUP); | |
243 | } | |
244 | if (mmc_controller->slots[0].caps & | |
245 | MMC_CAP_8_BIT_DATA) { | |
246 | omap_mux_init_signal("sdmmc1_dat4", | |
247 | OMAP_PIN_INPUT_PULLUP); | |
248 | omap_mux_init_signal("sdmmc1_dat5", | |
249 | OMAP_PIN_INPUT_PULLUP); | |
250 | omap_mux_init_signal("sdmmc1_dat6", | |
251 | OMAP_PIN_INPUT_PULLUP); | |
252 | omap_mux_init_signal("sdmmc1_dat7", | |
253 | OMAP_PIN_INPUT_PULLUP); | |
254 | } | |
255 | } | |
256 | if (controller_nr == 1) { | |
257 | /* MMC2 */ | |
258 | omap_mux_init_signal("sdmmc2_clk", | |
259 | OMAP_PIN_INPUT_PULLUP); | |
260 | omap_mux_init_signal("sdmmc2_cmd", | |
261 | OMAP_PIN_INPUT_PULLUP); | |
262 | omap_mux_init_signal("sdmmc2_dat0", | |
263 | OMAP_PIN_INPUT_PULLUP); | |
264 | ||
265 | /* | |
266 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 | |
267 | * need to be muxed in the board-*.c files | |
268 | */ | |
269 | if (mmc_controller->slots[0].caps & | |
270 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
271 | omap_mux_init_signal("sdmmc2_dat1", | |
272 | OMAP_PIN_INPUT_PULLUP); | |
273 | omap_mux_init_signal("sdmmc2_dat2", | |
274 | OMAP_PIN_INPUT_PULLUP); | |
275 | omap_mux_init_signal("sdmmc2_dat3", | |
276 | OMAP_PIN_INPUT_PULLUP); | |
277 | } | |
278 | if (mmc_controller->slots[0].caps & | |
279 | MMC_CAP_8_BIT_DATA) { | |
280 | omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", | |
281 | OMAP_PIN_INPUT_PULLUP); | |
282 | omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", | |
283 | OMAP_PIN_INPUT_PULLUP); | |
284 | omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", | |
285 | OMAP_PIN_INPUT_PULLUP); | |
286 | omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", | |
287 | OMAP_PIN_INPUT_PULLUP); | |
288 | } | |
289 | } | |
290 | ||
291 | /* | |
292 | * For MMC3 the pins need to be muxed in the board-*.c files | |
293 | */ | |
294 | } | |
295 | } | |
296 | ||
d1589f09 TL |
297 | static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, |
298 | struct omap_mmc_platform_data *mmc) | |
4621d5f8 KK |
299 | { |
300 | char *hc_name; | |
301 | ||
302 | hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); | |
303 | if (!hc_name) { | |
304 | pr_err("Cannot allocate memory for controller slot name\n"); | |
305 | kfree(hc_name); | |
306 | return -ENOMEM; | |
307 | } | |
308 | ||
309 | if (c->name) | |
310 | strncpy(hc_name, c->name, HSMMC_NAME_LEN); | |
311 | else | |
312 | snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", | |
313 | c->mmc, 1); | |
314 | mmc->slots[0].name = hc_name; | |
315 | mmc->nr_slots = 1; | |
316 | mmc->slots[0].caps = c->caps; | |
6fdc75de | 317 | mmc->slots[0].pm_caps = c->pm_caps; |
4621d5f8 | 318 | mmc->slots[0].internal_clock = !c->ext_clock; |
d418ed87 | 319 | mmc->max_freq = c->max_freq; |
4621d5f8 KK |
320 | if (cpu_is_omap44xx()) |
321 | mmc->reg_offset = OMAP4_MMC_REG_OFFSET; | |
322 | else | |
323 | mmc->reg_offset = 0; | |
324 | ||
325 | mmc->get_context_loss_count = hsmmc_get_context_loss; | |
326 | ||
327 | mmc->slots[0].switch_pin = c->gpio_cd; | |
328 | mmc->slots[0].gpio_wp = c->gpio_wp; | |
329 | ||
330 | mmc->slots[0].remux = c->remux; | |
331 | mmc->slots[0].init_card = c->init_card; | |
332 | ||
333 | if (c->cover_only) | |
334 | mmc->slots[0].cover = 1; | |
335 | ||
336 | if (c->nonremovable) | |
337 | mmc->slots[0].nonremovable = 1; | |
338 | ||
339 | if (c->power_saving) | |
340 | mmc->slots[0].power_saving = 1; | |
341 | ||
342 | if (c->no_off) | |
343 | mmc->slots[0].no_off = 1; | |
344 | ||
b1c1df7a B |
345 | if (c->no_off_init) |
346 | mmc->slots[0].no_regulator_off_init = c->no_off_init; | |
347 | ||
4621d5f8 KK |
348 | if (c->vcc_aux_disable_is_sleep) |
349 | mmc->slots[0].vcc_aux_disable_is_sleep = 1; | |
350 | ||
351 | /* | |
352 | * NOTE: MMC slots should have a Vcc regulator set up. | |
353 | * This may be from a TWL4030-family chip, another | |
354 | * controllable regulator, or a fixed supply. | |
355 | * | |
356 | * temporary HACK: ocr_mask instead of fixed supply | |
357 | */ | |
68a88b98 | 358 | if (soc_is_am35xx()) |
e89715a7 A |
359 | mmc->slots[0].ocr_mask = MMC_VDD_165_195 | |
360 | MMC_VDD_26_27 | | |
361 | MMC_VDD_27_28 | | |
362 | MMC_VDD_29_30 | | |
363 | MMC_VDD_30_31 | | |
364 | MMC_VDD_31_32; | |
365 | else | |
366 | mmc->slots[0].ocr_mask = c->ocr_mask; | |
4621d5f8 | 367 | |
68a88b98 | 368 | if (!soc_is_am35xx()) |
4621d5f8 KK |
369 | mmc->slots[0].features |= HSMMC_HAS_PBIAS; |
370 | ||
371 | if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) | |
372 | mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; | |
373 | ||
374 | switch (c->mmc) { | |
375 | case 1: | |
376 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { | |
377 | /* on-chip level shifting via PBIAS0/PBIAS1 */ | |
378 | if (cpu_is_omap44xx()) { | |
379 | mmc->slots[0].before_set_reg = | |
380 | omap4_hsmmc1_before_set_reg; | |
381 | mmc->slots[0].after_set_reg = | |
382 | omap4_hsmmc1_after_set_reg; | |
383 | } else { | |
384 | mmc->slots[0].before_set_reg = | |
385 | omap_hsmmc1_before_set_reg; | |
386 | mmc->slots[0].after_set_reg = | |
387 | omap_hsmmc1_after_set_reg; | |
388 | } | |
389 | } | |
390 | ||
68a88b98 | 391 | if (soc_is_am35xx()) |
e62245ba IG |
392 | mmc->slots[0].set_power = nop_mmc_set_power; |
393 | ||
4621d5f8 KK |
394 | /* OMAP3630 HSMMC1 supports only 4-bit */ |
395 | if (cpu_is_omap3630() && | |
396 | (c->caps & MMC_CAP_8_BIT_DATA)) { | |
397 | c->caps &= ~MMC_CAP_8_BIT_DATA; | |
398 | c->caps |= MMC_CAP_4_BIT_DATA; | |
399 | mmc->slots[0].caps = c->caps; | |
400 | } | |
401 | break; | |
402 | case 2: | |
68a88b98 | 403 | if (soc_is_am35xx()) |
e62245ba IG |
404 | mmc->slots[0].set_power = am35x_hsmmc2_set_power; |
405 | ||
4621d5f8 KK |
406 | if (c->ext_clock) |
407 | c->transceiver = 1; | |
408 | if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { | |
409 | c->caps &= ~MMC_CAP_8_BIT_DATA; | |
410 | c->caps |= MMC_CAP_4_BIT_DATA; | |
411 | } | |
4621d5f8 KK |
412 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { |
413 | /* off-chip level shifting, or none */ | |
ffa1e4ed | 414 | mmc->slots[0].before_set_reg = hsmmc2_before_set_reg; |
4621d5f8 KK |
415 | mmc->slots[0].after_set_reg = NULL; |
416 | } | |
417 | break; | |
ffa1e4ed | 418 | case 3: |
4621d5f8 KK |
419 | case 4: |
420 | case 5: | |
421 | mmc->slots[0].before_set_reg = NULL; | |
422 | mmc->slots[0].after_set_reg = NULL; | |
423 | break; | |
424 | default: | |
425 | pr_err("MMC%d configuration not supported!\n", c->mmc); | |
426 | kfree(hc_name); | |
427 | return -ENODEV; | |
428 | } | |
429 | return 0; | |
430 | } | |
431 | ||
97899e55 | 432 | static int omap_hsmmc_done; |
3b972bf0 TL |
433 | |
434 | void omap_hsmmc_late_init(struct omap2_hsmmc_info *c) | |
435 | { | |
436 | struct platform_device *pdev; | |
437 | struct omap_mmc_platform_data *mmc_pdata; | |
438 | int res; | |
439 | ||
440 | if (omap_hsmmc_done != 1) | |
441 | return; | |
442 | ||
443 | omap_hsmmc_done++; | |
444 | ||
445 | for (; c->mmc; c++) { | |
446 | if (!c->deferred) | |
447 | continue; | |
448 | ||
449 | pdev = c->pdev; | |
450 | if (!pdev) | |
451 | continue; | |
452 | ||
453 | mmc_pdata = pdev->dev.platform_data; | |
454 | if (!mmc_pdata) | |
455 | continue; | |
456 | ||
457 | mmc_pdata->slots[0].switch_pin = c->gpio_cd; | |
458 | mmc_pdata->slots[0].gpio_wp = c->gpio_wp; | |
459 | ||
460 | res = omap_device_register(pdev); | |
461 | if (res) | |
462 | pr_err("Could not late init MMC %s\n", | |
463 | c->name); | |
464 | } | |
465 | } | |
466 | ||
4621d5f8 KK |
467 | #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 |
468 | ||
6028505c | 469 | static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, |
3b972bf0 | 470 | int ctrl_nr) |
4621d5f8 KK |
471 | { |
472 | struct omap_hwmod *oh; | |
3b972bf0 TL |
473 | struct omap_hwmod *ohs[1]; |
474 | struct omap_device *od; | |
3528c58e | 475 | struct platform_device *pdev; |
4621d5f8 KK |
476 | char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; |
477 | struct omap_mmc_platform_data *mmc_data; | |
478 | struct omap_mmc_dev_attr *mmc_dev_attr; | |
479 | char *name; | |
3b972bf0 | 480 | int res; |
4621d5f8 KK |
481 | |
482 | mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); | |
483 | if (!mmc_data) { | |
484 | pr_err("Cannot allocate memory for mmc device!\n"); | |
3b972bf0 | 485 | return; |
4621d5f8 KK |
486 | } |
487 | ||
3b972bf0 TL |
488 | res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data); |
489 | if (res < 0) | |
490 | goto free_mmc; | |
491 | ||
4621d5f8 KK |
492 | omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); |
493 | ||
0005ae73 | 494 | name = "omap_hsmmc"; |
3b972bf0 | 495 | res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, |
4621d5f8 | 496 | "mmc%d", ctrl_nr); |
3b972bf0 | 497 | WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN, |
4621d5f8 | 498 | "String buffer overflow in MMC%d device setup\n", ctrl_nr); |
3b972bf0 | 499 | |
4621d5f8 KK |
500 | oh = omap_hwmod_lookup(oh_name); |
501 | if (!oh) { | |
502 | pr_err("Could not look up %s\n", oh_name); | |
3b972bf0 | 503 | goto free_name; |
4621d5f8 | 504 | } |
3b972bf0 | 505 | ohs[0] = oh; |
4621d5f8 KK |
506 | if (oh->dev_attr != NULL) { |
507 | mmc_dev_attr = oh->dev_attr; | |
508 | mmc_data->controller_flags = mmc_dev_attr->flags; | |
26c547fd GI |
509 | /* |
510 | * erratum 2.1.1.128 doesn't apply if board has | |
511 | * a transceiver is attached | |
512 | */ | |
513 | if (hsmmcinfo->transceiver) | |
514 | mmc_data->controller_flags &= | |
515 | ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ; | |
4621d5f8 KK |
516 | } |
517 | ||
3b972bf0 TL |
518 | pdev = platform_device_alloc(name, ctrl_nr - 1); |
519 | if (!pdev) { | |
520 | pr_err("Could not allocate pdev for %s\n", name); | |
521 | goto free_name; | |
4621d5f8 | 522 | } |
3b972bf0 TL |
523 | dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); |
524 | ||
c1d1cd59 | 525 | od = omap_device_alloc(pdev, ohs, 1); |
64de3a00 | 526 | if (IS_ERR(od)) { |
3b972bf0 TL |
527 | pr_err("Could not allocate od for %s\n", name); |
528 | goto put_pdev; | |
529 | } | |
530 | ||
531 | res = platform_device_add_data(pdev, mmc_data, | |
532 | sizeof(struct omap_mmc_platform_data)); | |
533 | if (res) { | |
534 | pr_err("Could not add pdata for %s\n", name); | |
535 | goto put_pdev; | |
536 | } | |
537 | ||
538 | hsmmcinfo->pdev = pdev; | |
539 | ||
540 | if (hsmmcinfo->deferred) | |
541 | goto free_mmc; | |
542 | ||
543 | res = omap_device_register(pdev); | |
544 | if (res) { | |
545 | pr_err("Could not register od for %s\n", name); | |
546 | goto free_od; | |
547 | } | |
548 | ||
549 | goto free_mmc; | |
550 | ||
551 | free_od: | |
552 | omap_device_delete(od); | |
553 | ||
554 | put_pdev: | |
555 | platform_device_put(pdev); | |
556 | ||
557 | free_name: | |
558 | kfree(mmc_data->slots[0].name); | |
4621d5f8 | 559 | |
3b972bf0 | 560 | free_mmc: |
4621d5f8 KK |
561 | kfree(mmc_data); |
562 | } | |
90c62bf0 | 563 | |
d1589f09 | 564 | void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) |
90c62bf0 | 565 | { |
c83c8e6c | 566 | u32 reg; |
90c62bf0 | 567 | |
97899e55 TL |
568 | if (omap_hsmmc_done) |
569 | return; | |
570 | ||
571 | omap_hsmmc_done = 1; | |
572 | ||
c83c8e6c | 573 | if (!cpu_is_omap44xx()) { |
574 | if (cpu_is_omap2430()) { | |
575 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | |
576 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | |
577 | } else { | |
578 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | |
579 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | |
580 | } | |
90c62bf0 | 581 | } else { |
dcf5ef3f SS |
582 | control_pbias_offset = |
583 | OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; | |
584 | control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; | |
585 | reg = omap4_ctrl_pad_readl(control_mmc1); | |
586 | reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | | |
587 | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); | |
588 | reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | | |
589 | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); | |
c862dd70 | 590 | reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | |
dcf5ef3f SS |
591 | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | |
592 | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); | |
593 | omap4_ctrl_pad_writel(reg, control_mmc1); | |
90c62bf0 TL |
594 | } |
595 | ||
4621d5f8 | 596 | for (; controllers->mmc; controllers++) |
3b972bf0 | 597 | omap_hsmmc_init_one(controllers, controllers->mmc); |
01971f65 | 598 | |
90c62bf0 TL |
599 | } |
600 | ||
601 | #endif |