Commit | Line | Data |
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90c62bf0 | 1 | /* |
d02a900b | 2 | * linux/arch/arm/mach-omap2/hsmmc.c |
90c62bf0 TL |
3 | * |
4 | * Copyright (C) 2007-2008 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Author: Texas Instruments | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
db0fefc5 AH |
12 | #include <linux/kernel.h> |
13 | #include <linux/slab.h> | |
14 | #include <linux/string.h> | |
90c62bf0 | 15 | #include <linux/delay.h> |
90c62bf0 | 16 | #include <mach/hardware.h> |
ce491cf8 TL |
17 | #include <plat/control.h> |
18 | #include <plat/mmc.h> | |
90c62bf0 | 19 | |
d02a900b | 20 | #include "hsmmc.h" |
90c62bf0 | 21 | |
db0fefc5 | 22 | #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) |
90c62bf0 TL |
23 | |
24 | static u16 control_pbias_offset; | |
25 | static u16 control_devconf1_offset; | |
26 | ||
27 | #define HSMMC_NAME_LEN 9 | |
28 | ||
68ff0423 | 29 | static struct hsmmc_controller { |
b583f26d DB |
30 | char name[HSMMC_NAME_LEN + 1]; |
31 | } hsmmc[OMAP34XX_NR_MMC]; | |
90c62bf0 | 32 | |
1887bde3 DK |
33 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
34 | ||
68ff0423 | 35 | static int hsmmc_get_context_loss(struct device *dev) |
1887bde3 DK |
36 | { |
37 | /* FIXME: PM DPS not implemented yet */ | |
38 | return 0; | |
39 | } | |
40 | ||
41 | #else | |
68ff0423 | 42 | #define hsmmc_get_context_loss NULL |
1887bde3 DK |
43 | #endif |
44 | ||
db0fefc5 AH |
45 | static void hsmmc1_before_set_reg(struct device *dev, int slot, |
46 | int power_on, int vdd) | |
90c62bf0 | 47 | { |
555d503f | 48 | u32 reg, prog_io; |
90c62bf0 TL |
49 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
50 | ||
0329c377 DB |
51 | /* |
52 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | |
b583f26d | 53 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both |
0329c377 DB |
54 | * 1.8V and 3.0V modes, controlled by the PBIAS register. |
55 | * | |
56 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | |
57 | * is most naturally TWL VSIM; those pins also use PBIAS. | |
b583f26d DB |
58 | * |
59 | * FIXME handle VMMC1A as needed ... | |
0329c377 | 60 | */ |
90c62bf0 TL |
61 | if (power_on) { |
62 | if (cpu_is_omap2430()) { | |
63 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | |
64 | if ((1 << vdd) >= MMC_VDD_30_31) | |
65 | reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
66 | else | |
67 | reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
68 | omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); | |
69 | } | |
70 | ||
71 | if (mmc->slots[0].internal_clock) { | |
72 | reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
73 | reg |= OMAP2_MMCSDIO1ADPCLKISEL; | |
74 | omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); | |
75 | } | |
76 | ||
77 | reg = omap_ctrl_readl(control_pbias_offset); | |
555d503f M |
78 | if (cpu_is_omap3630()) { |
79 | /* Set MMC I/O to 52Mhz */ | |
80 | prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | |
81 | prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; | |
82 | omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); | |
83 | } else { | |
84 | reg |= OMAP2_PBIASSPEEDCTRL0; | |
85 | } | |
90c62bf0 TL |
86 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; |
87 | omap_ctrl_writel(reg, control_pbias_offset); | |
db0fefc5 AH |
88 | } else { |
89 | reg = omap_ctrl_readl(control_pbias_offset); | |
90 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | |
91 | omap_ctrl_writel(reg, control_pbias_offset); | |
92 | } | |
93 | } | |
94 | ||
95 | static void hsmmc1_after_set_reg(struct device *dev, int slot, | |
96 | int power_on, int vdd) | |
97 | { | |
98 | u32 reg; | |
90c62bf0 | 99 | |
db0fefc5 AH |
100 | /* 100ms delay required for PBIAS configuration */ |
101 | msleep(100); | |
90c62bf0 | 102 | |
db0fefc5 | 103 | if (power_on) { |
90c62bf0 TL |
104 | reg = omap_ctrl_readl(control_pbias_offset); |
105 | reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); | |
106 | if ((1 << vdd) <= MMC_VDD_165_195) | |
107 | reg &= ~OMAP2_PBIASLITEVMODE0; | |
108 | else | |
109 | reg |= OMAP2_PBIASLITEVMODE0; | |
110 | omap_ctrl_writel(reg, control_pbias_offset); | |
111 | } else { | |
90c62bf0 TL |
112 | reg = omap_ctrl_readl(control_pbias_offset); |
113 | reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | | |
114 | OMAP2_PBIASLITEVMODE0); | |
115 | omap_ctrl_writel(reg, control_pbias_offset); | |
116 | } | |
90c62bf0 TL |
117 | } |
118 | ||
db0fefc5 AH |
119 | static void hsmmc23_before_set_reg(struct device *dev, int slot, |
120 | int power_on, int vdd) | |
90c62bf0 | 121 | { |
90c62bf0 | 122 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
b583f26d | 123 | |
90c62bf0 | 124 | if (power_on) { |
db0fefc5 | 125 | /* Only MMC2 supports a CLKIN */ |
90c62bf0 TL |
126 | if (mmc->slots[0].internal_clock) { |
127 | u32 reg; | |
128 | ||
129 | reg = omap_ctrl_readl(control_devconf1_offset); | |
130 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; | |
131 | omap_ctrl_writel(reg, control_devconf1_offset); | |
132 | } | |
9b7c18e0 | 133 | } |
9b7c18e0 AH |
134 | } |
135 | ||
90c62bf0 TL |
136 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; |
137 | ||
68ff0423 | 138 | void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) |
90c62bf0 | 139 | { |
68ff0423 | 140 | struct omap2_hsmmc_info *c; |
90c62bf0 | 141 | int nr_hsmmc = ARRAY_SIZE(hsmmc_data); |
a6c7fdd2 | 142 | int i; |
90c62bf0 TL |
143 | |
144 | if (cpu_is_omap2430()) { | |
145 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | |
146 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | |
90c62bf0 TL |
147 | } else { |
148 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | |
149 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | |
150 | } | |
151 | ||
152 | for (c = controllers; c->mmc; c++) { | |
68ff0423 | 153 | struct hsmmc_controller *hc = hsmmc + c->mmc - 1; |
90c62bf0 TL |
154 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; |
155 | ||
156 | if (!c->mmc || c->mmc > nr_hsmmc) { | |
157 | pr_debug("MMC%d: no such controller\n", c->mmc); | |
158 | continue; | |
159 | } | |
160 | if (mmc) { | |
161 | pr_debug("MMC%d: already configured\n", c->mmc); | |
162 | continue; | |
163 | } | |
164 | ||
68ff0423 AH |
165 | mmc = kzalloc(sizeof(struct omap_mmc_platform_data), |
166 | GFP_KERNEL); | |
90c62bf0 TL |
167 | if (!mmc) { |
168 | pr_err("Cannot allocate memory for mmc device!\n"); | |
a6c7fdd2 | 169 | goto done; |
90c62bf0 TL |
170 | } |
171 | ||
e51151a5 | 172 | if (c->name) |
68ff0423 | 173 | strncpy(hc->name, c->name, HSMMC_NAME_LEN); |
e51151a5 | 174 | else |
68ff0423 | 175 | snprintf(hc->name, ARRAY_SIZE(hc->name), |
e51151a5 | 176 | "mmc%islot%i", c->mmc, 1); |
68ff0423 | 177 | mmc->slots[0].name = hc->name; |
90c62bf0 | 178 | mmc->nr_slots = 1; |
90c62bf0 TL |
179 | mmc->slots[0].wires = c->wires; |
180 | mmc->slots[0].internal_clock = !c->ext_clock; | |
181 | mmc->dma_mask = 0xffffffff; | |
90c62bf0 | 182 | |
68ff0423 | 183 | mmc->get_context_loss_count = hsmmc_get_context_loss; |
1887bde3 | 184 | |
db0fefc5 AH |
185 | mmc->slots[0].switch_pin = c->gpio_cd; |
186 | mmc->slots[0].gpio_wp = c->gpio_wp; | |
90c62bf0 | 187 | |
db0fefc5 AH |
188 | if (c->cover_only) |
189 | mmc->slots[0].cover = 1; | |
90c62bf0 | 190 | |
23d99bb9 AH |
191 | if (c->nonremovable) |
192 | mmc->slots[0].nonremovable = 1; | |
193 | ||
dd498eff DK |
194 | if (c->power_saving) |
195 | mmc->slots[0].power_saving = 1; | |
196 | ||
b583f26d DB |
197 | /* NOTE: MMC slots should have a Vcc regulator set up. |
198 | * This may be from a TWL4030-family chip, another | |
199 | * controllable regulator, or a fixed supply. | |
200 | * | |
201 | * temporary HACK: ocr_mask instead of fixed supply | |
90c62bf0 | 202 | */ |
b583f26d | 203 | mmc->slots[0].ocr_mask = c->ocr_mask; |
90c62bf0 TL |
204 | |
205 | switch (c->mmc) { | |
206 | case 1: | |
b583f26d | 207 | /* on-chip level shifting via PBIAS0/PBIAS1 */ |
db0fefc5 AH |
208 | mmc->slots[0].before_set_reg = hsmmc1_before_set_reg; |
209 | mmc->slots[0].after_set_reg = hsmmc1_after_set_reg; | |
41fd03d6 M |
210 | |
211 | /* Omap3630 HSMMC1 supports only 4-bit */ | |
212 | if (cpu_is_omap3630() && c->wires > 4) { | |
213 | c->wires = 4; | |
214 | mmc->slots[0].wires = c->wires; | |
215 | } | |
90c62bf0 TL |
216 | break; |
217 | case 2: | |
b583f26d DB |
218 | if (c->ext_clock) |
219 | c->transceiver = 1; | |
220 | if (c->transceiver && c->wires > 4) | |
221 | c->wires = 4; | |
222 | /* FALLTHROUGH */ | |
07d83cc9 | 223 | case 3: |
b583f26d | 224 | /* off-chip level shifting, or none */ |
db0fefc5 AH |
225 | mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; |
226 | mmc->slots[0].after_set_reg = NULL; | |
07d83cc9 | 227 | break; |
90c62bf0 TL |
228 | default: |
229 | pr_err("MMC%d configuration not supported!\n", c->mmc); | |
07d83cc9 | 230 | kfree(mmc); |
90c62bf0 TL |
231 | continue; |
232 | } | |
233 | hsmmc_data[c->mmc - 1] = mmc; | |
234 | } | |
235 | ||
236 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); | |
01971f65 DB |
237 | |
238 | /* pass the device nodes back to board setup code */ | |
239 | for (c = controllers; c->mmc; c++) { | |
240 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | |
241 | ||
242 | if (!c->mmc || c->mmc > nr_hsmmc) | |
243 | continue; | |
244 | c->dev = mmc->dev; | |
245 | } | |
a6c7fdd2 AK |
246 | |
247 | done: | |
248 | for (i = 0; i < nr_hsmmc; i++) | |
249 | kfree(hsmmc_data[i]); | |
90c62bf0 TL |
250 | } |
251 | ||
252 | #endif |