[deliverable/linux.git] / arch / arm / mach-omap2 / hsmmc.c

/*
 * linux/arch/arm/mach-omap2/hsmmc.c
 *
 * Copyright (C) 2007-2008 Texas Instruments
 * Copyright (C) 2008 Nokia Corporation
 * Author: Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <plat/mmc.h>
#include <plat/omap-pm.h>
#include <plat/mux.h>
#include <plat/omap_device.h>

#include "mux.h"
#include "hsmmc.h"
#include "control.h"

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)

static u16 control_pbias_offset;
static u16 control_devconf1_offset;
static u16 control_mmc1;

#define HSMMC_NAME_LEN	9

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

static int hsmmc_get_context_loss(struct device *dev)
{
	return omap_pm_get_dev_context_loss_count(dev);
}

#else
#define hsmmc_get_context_loss NULL
#endif

static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg, prog_io;
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	/*
	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
	 *
	 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	 * is most naturally TWL VSIM; those pins also use PBIAS.
	 *
	 * FIXME handle VMMC1A as needed ...
	 */
	if (power_on) {
		if (cpu_is_omap2430()) {
			reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
			if ((1 << vdd) >= MMC_VDD_30_31)
				reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
			else
				reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
		}

		if (mmc->slots[0].internal_clock) {
			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
		}

		reg = omap_ctrl_readl(control_pbias_offset);
		if (cpu_is_omap3630()) {
			/* Set MMC I/O to 52Mhz */
			prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
			prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
			omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
		} else {
			reg |= OMAP2_PBIASSPEEDCTRL0;
		}
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
				 int power_on, int vdd)
{
	u32 reg;

	/* 100ms delay required for PBIAS configuration */
	msleep(100);

	if (power_on) {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
		if ((1 << vdd) <= MMC_VDD_165_195)
			reg &= ~OMAP2_PBIASLITEVMODE0;
		else
			reg |= OMAP2_PBIASLITEVMODE0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
			OMAP2_PBIASLITEVMODE0);
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg;

	/*
	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
	 */
	reg = omap4_ctrl_pad_readl(control_pbias_offset);
	reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
		OMAP4_MMC1_PWRDNZ_MASK |
		OMAP4_MMC1_PBIASLITE_VMODE_MASK);
	omap4_ctrl_pad_writel(reg, control_pbias_offset);
}

static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
				 int power_on, int vdd)
{
	u32 reg;
	unsigned long timeout;

	if (power_on) {
		reg = omap4_ctrl_pad_readl(control_pbias_offset);
		reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
		if ((1 << vdd) <= MMC_VDD_165_195)
			reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
		else
			reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
		reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
			OMAP4_MMC1_PWRDNZ_MASK);
		omap4_ctrl_pad_writel(reg, control_pbias_offset);

		timeout = jiffies + msecs_to_jiffies(5);
		do {
			reg = omap4_ctrl_pad_readl(control_pbias_offset);
			if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
				break;
			usleep_range(100, 200);
		} while (!time_after(jiffies, timeout));

		if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
			pr_err("Pbias Voltage is not same as LDO\n");
			/* Caution : On VMODE_ERROR Power Down MMC IO */
			reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
			omap4_ctrl_pad_writel(reg, control_pbias_offset);
		}
	}
}

static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
{
	u32 reg;

	if (mmc->slots[0].internal_clock) {
		reg = omap_ctrl_readl(control_devconf1_offset);
		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
		omap_ctrl_writel(reg, control_devconf1_offset);
	}
}

static void hsmmc23_before_set_reg(struct device *dev, int slot,
				   int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	if (power_on)
		hsmmc2_select_input_clk_src(mmc);
}

static int am35x_hsmmc2_set_power(struct device *dev, int slot,
				  int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (power_on)
		hsmmc2_select_input_clk_src(mmc);

	return 0;
}

static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
							int vdd)
{
	return 0;
}

static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
			int controller_nr)
{
	if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
		(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
		omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
					OMAP_PIN_INPUT_PULLUP);
	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
		(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
		omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
					OMAP_PIN_INPUT_PULLUP);
	if (cpu_is_omap34xx()) {
		if (controller_nr == 0) {
			omap_mux_init_signal("sdmmc1_clk",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc1_cmd",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc1_dat0",
				OMAP_PIN_INPUT_PULLUP);
			if (mmc_controller->slots[0].caps &
				(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
				omap_mux_init_signal("sdmmc1_dat1",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat2",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat3",
					OMAP_PIN_INPUT_PULLUP);
			}
			if (mmc_controller->slots[0].caps &
						MMC_CAP_8_BIT_DATA) {
				omap_mux_init_signal("sdmmc1_dat4",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat5",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat6",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat7",
					OMAP_PIN_INPUT_PULLUP);
			}
		}
		if (controller_nr == 1) {
			/* MMC2 */
			omap_mux_init_signal("sdmmc2_clk",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc2_cmd",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc2_dat0",
				OMAP_PIN_INPUT_PULLUP);

			/*
			 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
			 * need to be muxed in the board-*.c files
			 */
			if (mmc_controller->slots[0].caps &
				(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
				omap_mux_init_signal("sdmmc2_dat1",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat2",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat3",
					OMAP_PIN_INPUT_PULLUP);
			}
			if (mmc_controller->slots[0].caps &
							MMC_CAP_8_BIT_DATA) {
				omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
					OMAP_PIN_INPUT_PULLUP);
			}
		}

		/*
		 * For MMC3 the pins need to be muxed in the board-*.c files
		 */
	}
}

static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
					struct omap_mmc_platform_data *mmc)
{
	char *hc_name;

	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
	if (!hc_name) {
		pr_err("Cannot allocate memory for controller slot name\n");
		kfree(hc_name);
		return -ENOMEM;
	}

	if (c->name)
		strncpy(hc_name, c->name, HSMMC_NAME_LEN);
	else
		snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
								c->mmc, 1);
	mmc->slots[0].name = hc_name;
	mmc->nr_slots = 1;
	mmc->slots[0].caps = c->caps;
	mmc->slots[0].pm_caps = c->pm_caps;
	mmc->slots[0].internal_clock = !c->ext_clock;
	mmc->dma_mask = 0xffffffff;
	if (cpu_is_omap44xx())
		mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
	else
		mmc->reg_offset = 0;

	mmc->get_context_loss_count = hsmmc_get_context_loss;

	mmc->slots[0].switch_pin = c->gpio_cd;
	mmc->slots[0].gpio_wp = c->gpio_wp;

	mmc->slots[0].remux = c->remux;
	mmc->slots[0].init_card = c->init_card;

	if (c->cover_only)
		mmc->slots[0].cover = 1;

	if (c->nonremovable)
		mmc->slots[0].nonremovable = 1;

	if (c->power_saving)
		mmc->slots[0].power_saving = 1;

	if (c->no_off)
		mmc->slots[0].no_off = 1;

	if (c->no_off_init)
		mmc->slots[0].no_regulator_off_init = c->no_off_init;

	if (c->vcc_aux_disable_is_sleep)
		mmc->slots[0].vcc_aux_disable_is_sleep = 1;

	/*
	 * NOTE:  MMC slots should have a Vcc regulator set up.
	 * This may be from a TWL4030-family chip, another
	 * controllable regulator, or a fixed supply.
	 *
	 * temporary HACK: ocr_mask instead of fixed supply
	 */
	mmc->slots[0].ocr_mask = c->ocr_mask;

	if (!cpu_is_omap3517() && !cpu_is_omap3505())
		mmc->slots[0].features |= HSMMC_HAS_PBIAS;

	if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
		mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;

	switch (c->mmc) {
	case 1:
		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
			/* on-chip level shifting via PBIAS0/PBIAS1 */
			if (cpu_is_omap44xx()) {
				mmc->slots[0].before_set_reg =
						omap4_hsmmc1_before_set_reg;
				mmc->slots[0].after_set_reg =
						omap4_hsmmc1_after_set_reg;
			} else {
				mmc->slots[0].before_set_reg =
						omap_hsmmc1_before_set_reg;
				mmc->slots[0].after_set_reg =
						omap_hsmmc1_after_set_reg;
			}
		}

		if (cpu_is_omap3517() || cpu_is_omap3505())
			mmc->slots[0].set_power = nop_mmc_set_power;

		/* OMAP3630 HSMMC1 supports only 4-bit */
		if (cpu_is_omap3630() &&
				(c->caps & MMC_CAP_8_BIT_DATA)) {
			c->caps &= ~MMC_CAP_8_BIT_DATA;
			c->caps |= MMC_CAP_4_BIT_DATA;
			mmc->slots[0].caps = c->caps;
		}
		break;
	case 2:
		if (cpu_is_omap3517() || cpu_is_omap3505())
			mmc->slots[0].set_power = am35x_hsmmc2_set_power;

		if (c->ext_clock)
			c->transceiver = 1;
		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
			c->caps &= ~MMC_CAP_8_BIT_DATA;
			c->caps |= MMC_CAP_4_BIT_DATA;
		}
		/* FALLTHROUGH */
	case 3:
		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
			/* off-chip level shifting, or none */
			mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
			mmc->slots[0].after_set_reg = NULL;
		}
		break;
	case 4:
	case 5:
		mmc->slots[0].before_set_reg = NULL;
		mmc->slots[0].after_set_reg = NULL;
		break;
	default:
		pr_err("MMC%d configuration not supported!\n", c->mmc);
		kfree(hc_name);
		return -ENODEV;
	}
	return 0;
}

#define MAX_OMAP_MMC_HWMOD_NAME_LEN		16

void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
{
	struct omap_hwmod *oh;
	struct platform_device *pdev;
	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
	struct omap_mmc_platform_data *mmc_data;
	struct omap_mmc_dev_attr *mmc_dev_attr;
	char *name;
	int l;

	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
	if (!mmc_data) {
		pr_err("Cannot allocate memory for mmc device!\n");
		goto done;
	}

	if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
		pr_err("%s fails!\n", __func__);
		goto done;
	}
	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));

	name = "omap_hsmmc";

	l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
		     "mmc%d", ctrl_nr);
	WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
	     "String buffer overflow in MMC%d device setup\n", ctrl_nr);
	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		kfree(mmc_data->slots[0].name);
		goto done;
	}

	if (oh->dev_attr != NULL) {
		mmc_dev_attr = oh->dev_attr;
		mmc_data->controller_flags = mmc_dev_attr->flags;
	}

	pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
		sizeof(struct omap_mmc_platform_data), NULL, 0, false);
	if (IS_ERR(pdev)) {
		WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
		kfree(mmc_data->slots[0].name);
		goto done;
	}
	/*
	 * return device handle to board setup code
	 * required to populate for regulator framework structure
	 */
	hsmmcinfo->dev = &pdev->dev;

done:
	kfree(mmc_data);
}

void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	u32 reg;

	if (!cpu_is_omap44xx()) {
		if (cpu_is_omap2430()) {
			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
		} else {
			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
		}
	} else {
		control_pbias_offset =
			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
		reg = omap4_ctrl_pad_readl(control_mmc1);
		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
		reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		omap4_ctrl_pad_writel(reg, control_mmc1);
	}

	for (; controllers->mmc; controllers++)
		omap_init_hsmmc(controllers, controllers->mmc);

}

#endif
Commit	Line	Data
90c62bf0	1	/*
d02a900b	2	* linux/arch/arm/mach-omap2/hsmmc.c
90c62bf0 TL	3	*
	4	* Copyright (C) 2007-2008 Texas Instruments
	5	* Copyright (C) 2008 Nokia Corporation
	6	* Author: Texas Instruments
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
db0fefc5 AH	12	#include <linux/kernel.h>
	13	#include <linux/slab.h>
	14	#include <linux/string.h>
90c62bf0	15	#include <linux/delay.h>
5e4698fc	16	#include <linux/gpio.h>
90c62bf0	17	#include <mach/hardware.h>
ce491cf8	18	#include <plat/mmc.h>
e3df0fb4	19	#include <plat/omap-pm.h>
d8d0a61c	20	#include <plat/mux.h>
4621d5f8	21	#include <plat/omap_device.h>
90c62bf0	22
d8d0a61c	23	#include "mux.h"
d02a900b	24	#include "hsmmc.h"
4814ced5	25	#include "control.h"
90c62bf0	26
db0fefc5	27	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
90c62bf0 TL	28
	29	static u16 control_pbias_offset;
	30	static u16 control_devconf1_offset;
c83c8e6c	31	static u16 control_mmc1;
90c62bf0 TL	32
	33	#define HSMMC_NAME_LEN 9
	34
1887bde3 DK	35	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
1887bde3 DK	36
68ff0423	37	static int hsmmc_get_context_loss(struct device *dev)
1887bde3	38	{
e3df0fb4	39	return omap_pm_get_dev_context_loss_count(dev);
1887bde3 DK	40	}
	41
	42	#else
68ff0423	43	#define hsmmc_get_context_loss NULL
1887bde3 DK	44	#endif
1887bde3 DK	45
c83c8e6c	46	static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
db0fefc5	47	int power_on, int vdd)
90c62bf0	48	{
555d503f	49	u32 reg, prog_io;
90c62bf0 TL	50	struct omap_mmc_platform_data *mmc = dev->platform_data;
90c62bf0 TL	51
ce6f0016 AH	52	if (mmc->slots[0].remux)
	53	mmc->slots[0].remux(dev, slot, power_on);
	54
0329c377 DB	55	/*
0329c377 DB	56	* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
b583f26d	57	* card with Vcc regulator (from twl4030 or whatever). OMAP has both
0329c377 DB	58	* 1.8V and 3.0V modes, controlled by the PBIAS register.
	59	*
	60	* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	61	* is most naturally TWL VSIM; those pins also use PBIAS.
b583f26d DB	62	*
b583f26d DB	63	* FIXME handle VMMC1A as needed ...
0329c377	64	*/
90c62bf0 TL	65	if (power_on) {
	66	if (cpu_is_omap2430()) {
	67	reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
	68	if ((1 << vdd) >= MMC_VDD_30_31)
	69	reg \|= OMAP243X_MMC1_ACTIVE_OVERWRITE;
	70	else
	71	reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
	72	omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
	73	}
	74
	75	if (mmc->slots[0].internal_clock) {
	76	reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	77	reg \|= OMAP2_MMCSDIO1ADPCLKISEL;
	78	omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
	79	}
	80
	81	reg = omap_ctrl_readl(control_pbias_offset);
555d503f M	82	if (cpu_is_omap3630()) {
	83	/* Set MMC I/O to 52Mhz */
	84	prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	85	prog_io \|= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
	86	omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
	87	} else {
	88	reg \|= OMAP2_PBIASSPEEDCTRL0;
	89	}
90c62bf0 TL	90	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
90c62bf0 TL	91	omap_ctrl_writel(reg, control_pbias_offset);
db0fefc5 AH	92	} else {
	93	reg = omap_ctrl_readl(control_pbias_offset);
	94	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
	95	omap_ctrl_writel(reg, control_pbias_offset);
	96	}
	97	}
	98
c83c8e6c	99	static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
db0fefc5 AH	100	int power_on, int vdd)
	101	{
	102	u32 reg;
90c62bf0	103
db0fefc5 AH	104	/* 100ms delay required for PBIAS configuration */
db0fefc5 AH	105	msleep(100);
90c62bf0	106
db0fefc5	107	if (power_on) {
90c62bf0 TL	108	reg = omap_ctrl_readl(control_pbias_offset);
	109	reg \|= (OMAP2_PBIASLITEPWRDNZ0 \| OMAP2_PBIASSPEEDCTRL0);
	110	if ((1 << vdd) <= MMC_VDD_165_195)
	111	reg &= ~OMAP2_PBIASLITEVMODE0;
	112	else
	113	reg \|= OMAP2_PBIASLITEVMODE0;
	114	omap_ctrl_writel(reg, control_pbias_offset);
	115	} else {
90c62bf0 TL	116	reg = omap_ctrl_readl(control_pbias_offset);
	117	reg \|= (OMAP2_PBIASSPEEDCTRL0 \| OMAP2_PBIASLITEPWRDNZ0 \|
	118	OMAP2_PBIASLITEVMODE0);
	119	omap_ctrl_writel(reg, control_pbias_offset);
	120	}
90c62bf0 TL	121	}
90c62bf0 TL	122
c83c8e6c	123	static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
	124	int power_on, int vdd)
	125	{
	126	u32 reg;
	127
	128	/*
	129	* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	130	* card with Vcc regulator (from twl4030 or whatever). OMAP has both
	131	* 1.8V and 3.0V modes, controlled by the PBIAS register.
c83c8e6c	132	*/
dcf5ef3f SS	133	reg = omap4_ctrl_pad_readl(control_pbias_offset);
dcf5ef3f SS	134	reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK \|
ff2beb1d B	135	OMAP4_MMC1_PWRDNZ_MASK \|
ff2beb1d B	136	OMAP4_MMC1_PBIASLITE_VMODE_MASK);
dcf5ef3f	137	omap4_ctrl_pad_writel(reg, control_pbias_offset);
c83c8e6c	138	}
	139
	140	static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
	141	int power_on, int vdd)
	142	{
	143	u32 reg;
1fcecf28	144	unsigned long timeout;
c83c8e6c	145
c83c8e6c	146	if (power_on) {
dcf5ef3f SS	147	reg = omap4_ctrl_pad_readl(control_pbias_offset);
dcf5ef3f SS	148	reg \|= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
c83c8e6c	149	if ((1 << vdd) <= MMC_VDD_165_195)
dcf5ef3f	150	reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
c83c8e6c	151	else
dcf5ef3f SS	152	reg \|= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
dcf5ef3f SS	153	reg \|= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK \|
3696d303	154	OMAP4_MMC1_PWRDNZ_MASK);
dcf5ef3f	155	omap4_ctrl_pad_writel(reg, control_pbias_offset);
1fcecf28 B	156
	157	timeout = jiffies + msecs_to_jiffies(5);
	158	do {
	159	reg = omap4_ctrl_pad_readl(control_pbias_offset);
	160	if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
	161	break;
	162	usleep_range(100, 200);
	163	} while (!time_after(jiffies, timeout));
	164
dcf5ef3f	165	if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
c83c8e6c	166	pr_err("Pbias Voltage is not same as LDO\n");
c83c8e6c	167	/* Caution : On VMODE_ERROR Power Down MMC IO */
3696d303	168	reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
dcf5ef3f	169	omap4_ctrl_pad_writel(reg, control_pbias_offset);
c83c8e6c	170	}
c83c8e6c	171	}
	172	}
	173
e62245ba IG	174	static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
	175	{
	176	u32 reg;
	177
	178	if (mmc->slots[0].internal_clock) {
	179	reg = omap_ctrl_readl(control_devconf1_offset);
	180	reg \|= OMAP2_MMCSDIO2ADPCLKISEL;
	181	omap_ctrl_writel(reg, control_devconf1_offset);
	182	}
	183	}
	184
db0fefc5 AH	185	static void hsmmc23_before_set_reg(struct device *dev, int slot,
db0fefc5 AH	186	int power_on, int vdd)
90c62bf0	187	{
90c62bf0	188	struct omap_mmc_platform_data *mmc = dev->platform_data;
b583f26d	189
ce6f0016 AH	190	if (mmc->slots[0].remux)
	191	mmc->slots[0].remux(dev, slot, power_on);
	192
e62245ba IG	193	if (power_on)
	194	hsmmc2_select_input_clk_src(mmc);
	195	}
90c62bf0	196
e62245ba IG	197	static int am35x_hsmmc2_set_power(struct device *dev, int slot,
	198	int power_on, int vdd)
	199	{
	200	struct omap_mmc_platform_data *mmc = dev->platform_data;
	201
	202	if (power_on)
	203	hsmmc2_select_input_clk_src(mmc);
	204
	205	return 0;
9b7c18e0 AH	206	}
9b7c18e0 AH	207
03e7e170	208	static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
	209	int vdd)
	210	{
	211	return 0;
	212	}
	213
d8d0a61c KK	214	static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
	215	int controller_nr)
	216	{
a15164f1 TW	217	if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
a15164f1 TW	218	(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
d8d0a61c KK	219	omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
d8d0a61c KK	220	OMAP_PIN_INPUT_PULLUP);
a15164f1 TW	221	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
a15164f1 TW	222	(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
d8d0a61c KK	223	omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
	224	OMAP_PIN_INPUT_PULLUP);
	225	if (cpu_is_omap34xx()) {
	226	if (controller_nr == 0) {
	227	omap_mux_init_signal("sdmmc1_clk",
	228	OMAP_PIN_INPUT_PULLUP);
	229	omap_mux_init_signal("sdmmc1_cmd",
	230	OMAP_PIN_INPUT_PULLUP);
	231	omap_mux_init_signal("sdmmc1_dat0",
	232	OMAP_PIN_INPUT_PULLUP);
	233	if (mmc_controller->slots[0].caps &
	234	(MMC_CAP_4_BIT_DATA \| MMC_CAP_8_BIT_DATA)) {
	235	omap_mux_init_signal("sdmmc1_dat1",
	236	OMAP_PIN_INPUT_PULLUP);
	237	omap_mux_init_signal("sdmmc1_dat2",
	238	OMAP_PIN_INPUT_PULLUP);
	239	omap_mux_init_signal("sdmmc1_dat3",
	240	OMAP_PIN_INPUT_PULLUP);
	241	}
	242	if (mmc_controller->slots[0].caps &
	243	MMC_CAP_8_BIT_DATA) {
	244	omap_mux_init_signal("sdmmc1_dat4",
	245	OMAP_PIN_INPUT_PULLUP);
	246	omap_mux_init_signal("sdmmc1_dat5",
	247	OMAP_PIN_INPUT_PULLUP);
	248	omap_mux_init_signal("sdmmc1_dat6",
	249	OMAP_PIN_INPUT_PULLUP);
	250	omap_mux_init_signal("sdmmc1_dat7",
	251	OMAP_PIN_INPUT_PULLUP);
	252	}
	253	}
	254	if (controller_nr == 1) {
	255	/* MMC2 */
	256	omap_mux_init_signal("sdmmc2_clk",
	257	OMAP_PIN_INPUT_PULLUP);
	258	omap_mux_init_signal("sdmmc2_cmd",
	259	OMAP_PIN_INPUT_PULLUP);
	260	omap_mux_init_signal("sdmmc2_dat0",
	261	OMAP_PIN_INPUT_PULLUP);
	262
	263	/*
	264	* For 8 wire configurations, Lines DAT4, 5, 6 and 7
	265	* need to be muxed in the board-*.c files
	266	*/
	267	if (mmc_controller->slots[0].caps &
	268	(MMC_CAP_4_BIT_DATA \| MMC_CAP_8_BIT_DATA)) {
	269	omap_mux_init_signal("sdmmc2_dat1",
	270	OMAP_PIN_INPUT_PULLUP);
	271	omap_mux_init_signal("sdmmc2_dat2",
	272	OMAP_PIN_INPUT_PULLUP);
	273	omap_mux_init_signal("sdmmc2_dat3",
	274	OMAP_PIN_INPUT_PULLUP);
	275	}
	276	if (mmc_controller->slots[0].caps &
	277	MMC_CAP_8_BIT_DATA) {
	278	omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
	279	OMAP_PIN_INPUT_PULLUP);
	280	omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
	281	OMAP_PIN_INPUT_PULLUP);
	282	omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
	283	OMAP_PIN_INPUT_PULLUP);
	284	omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
	285	OMAP_PIN_INPUT_PULLUP);
	286	}
287	}
288
289	/*
290	* For MMC3 the pins need to be muxed in the board-*.c files
291	*/
292	}
293	}
294
4621d5f8 KK	295	static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
	296	struct omap_mmc_platform_data *mmc)
	297	{
	298	char *hc_name;
	299
	300	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
	301	if (!hc_name) {
	302	pr_err("Cannot allocate memory for controller slot name\n");
	303	kfree(hc_name);
	304	return -ENOMEM;
	305	}
	306
	307	if (c->name)
	308	strncpy(hc_name, c->name, HSMMC_NAME_LEN);
	309	else
	310	snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
	311	c->mmc, 1);
	312	mmc->slots[0].name = hc_name;
	313	mmc->nr_slots = 1;
	314	mmc->slots[0].caps = c->caps;
6fdc75de	315	mmc->slots[0].pm_caps = c->pm_caps;
4621d5f8 KK	316	mmc->slots[0].internal_clock = !c->ext_clock;
	317	mmc->dma_mask = 0xffffffff;
	318	if (cpu_is_omap44xx())
	319	mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
	320	else
	321	mmc->reg_offset = 0;
	322
	323	mmc->get_context_loss_count = hsmmc_get_context_loss;
	324
	325	mmc->slots[0].switch_pin = c->gpio_cd;
	326	mmc->slots[0].gpio_wp = c->gpio_wp;
	327
	328	mmc->slots[0].remux = c->remux;
	329	mmc->slots[0].init_card = c->init_card;
	330
	331	if (c->cover_only)
	332	mmc->slots[0].cover = 1;
	333
	334	if (c->nonremovable)
	335	mmc->slots[0].nonremovable = 1;
	336
	337	if (c->power_saving)
	338	mmc->slots[0].power_saving = 1;
	339
	340	if (c->no_off)
	341	mmc->slots[0].no_off = 1;
	342
b1c1df7a B	343	if (c->no_off_init)
	344	mmc->slots[0].no_regulator_off_init = c->no_off_init;
	345
4621d5f8 KK	346	if (c->vcc_aux_disable_is_sleep)
	347	mmc->slots[0].vcc_aux_disable_is_sleep = 1;
	348
	349	/*
	350	* NOTE: MMC slots should have a Vcc regulator set up.
	351	* This may be from a TWL4030-family chip, another
	352	* controllable regulator, or a fixed supply.
	353	*
	354	* temporary HACK: ocr_mask instead of fixed supply
	355	*/
	356	mmc->slots[0].ocr_mask = c->ocr_mask;
	357
e62245ba	358	if (!cpu_is_omap3517() && !cpu_is_omap3505())
4621d5f8 KK	359	mmc->slots[0].features \|= HSMMC_HAS_PBIAS;
	360
	361	if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
	362	mmc->slots[0].features \|= HSMMC_HAS_UPDATED_RESET;
	363
	364	switch (c->mmc) {
	365	case 1:
	366	if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
	367	/* on-chip level shifting via PBIAS0/PBIAS1 */
	368	if (cpu_is_omap44xx()) {
	369	mmc->slots[0].before_set_reg =
	370	omap4_hsmmc1_before_set_reg;
	371	mmc->slots[0].after_set_reg =
	372	omap4_hsmmc1_after_set_reg;
	373	} else {
	374	mmc->slots[0].before_set_reg =
	375	omap_hsmmc1_before_set_reg;
	376	mmc->slots[0].after_set_reg =
	377	omap_hsmmc1_after_set_reg;
	378	}
	379	}
	380
e62245ba IG	381	if (cpu_is_omap3517() \|\| cpu_is_omap3505())
	382	mmc->slots[0].set_power = nop_mmc_set_power;
	383
4621d5f8 KK	384	/* OMAP3630 HSMMC1 supports only 4-bit */
	385	if (cpu_is_omap3630() &&
	386	(c->caps & MMC_CAP_8_BIT_DATA)) {
	387	c->caps &= ~MMC_CAP_8_BIT_DATA;
	388	c->caps \|= MMC_CAP_4_BIT_DATA;
	389	mmc->slots[0].caps = c->caps;
	390	}
	391	break;
	392	case 2:
e62245ba IG	393	if (cpu_is_omap3517() \|\| cpu_is_omap3505())
	394	mmc->slots[0].set_power = am35x_hsmmc2_set_power;
	395
4621d5f8 KK	396	if (c->ext_clock)
	397	c->transceiver = 1;
	398	if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
	399	c->caps &= ~MMC_CAP_8_BIT_DATA;
	400	c->caps \|= MMC_CAP_4_BIT_DATA;
	401	}
	402	/* FALLTHROUGH */
	403	case 3:
	404	if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
	405	/* off-chip level shifting, or none */
	406	mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
	407	mmc->slots[0].after_set_reg = NULL;
	408	}
	409	break;
	410	case 4:
	411	case 5:
	412	mmc->slots[0].before_set_reg = NULL;
	413	mmc->slots[0].after_set_reg = NULL;
	414	break;
	415	default:
	416	pr_err("MMC%d configuration not supported!\n", c->mmc);
	417	kfree(hc_name);
	418	return -ENODEV;
	419	}
	420	return 0;
	421	}
	422
4621d5f8 KK	423	#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
	424
	425	void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
	426	{
	427	struct omap_hwmod *oh;
3528c58e	428	struct platform_device *pdev;
4621d5f8 KK	429	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
	430	struct omap_mmc_platform_data *mmc_data;
	431	struct omap_mmc_dev_attr *mmc_dev_attr;
	432	char *name;
	433	int l;
4621d5f8 KK	434
	435	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
	436	if (!mmc_data) {
	437	pr_err("Cannot allocate memory for mmc device!\n");
	438	goto done;
	439	}
	440
	441	if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
	442	pr_err("%s fails!\n", __func__);
	443	goto done;
	444	}
	445	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
	446
0005ae73	447	name = "omap_hsmmc";
4621d5f8 KK	448
	449	l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
	450	"mmc%d", ctrl_nr);
	451	WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
	452	"String buffer overflow in MMC%d device setup\n", ctrl_nr);
	453	oh = omap_hwmod_lookup(oh_name);
	454	if (!oh) {
	455	pr_err("Could not look up %s\n", oh_name);
	456	kfree(mmc_data->slots[0].name);
	457	goto done;
	458	}
	459
	460	if (oh->dev_attr != NULL) {
	461	mmc_dev_attr = oh->dev_attr;
	462	mmc_data->controller_flags = mmc_dev_attr->flags;
	463	}
	464
3528c58e	465	pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
f718e2c0	466	sizeof(struct omap_mmc_platform_data), NULL, 0, false);
3528c58e	467	if (IS_ERR(pdev)) {
25985edc	468	WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
4621d5f8 KK	469	kfree(mmc_data->slots[0].name);
	470	goto done;
	471	}
	472	/*
	473	* return device handle to board setup code
	474	* required to populate for regulator framework structure
	475	*/
3528c58e	476	hsmmcinfo->dev = &pdev->dev;
4621d5f8 KK	477
	478	done:
	479	kfree(mmc_data);
	480	}
90c62bf0	481
68ff0423	482	void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
90c62bf0	483	{
c83c8e6c	484	u32 reg;
90c62bf0	485
c83c8e6c	486	if (!cpu_is_omap44xx()) {
	487	if (cpu_is_omap2430()) {
	488	control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
	489	control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
	490	} else {
	491	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
	492	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
	493	}
90c62bf0	494	} else {
dcf5ef3f SS	495	control_pbias_offset =
	496	OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
	497	control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
	498	reg = omap4_ctrl_pad_readl(control_mmc1);
	499	reg \|= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK \|
	500	OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
	501	reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK \|
	502	OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
c862dd70	503	reg \|= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK \|
dcf5ef3f SS	504	OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK \|
	505	OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
	506	omap4_ctrl_pad_writel(reg, control_mmc1);
90c62bf0 TL	507	}
90c62bf0 TL	508
4621d5f8 KK	509	for (; controllers->mmc; controllers++)
4621d5f8 KK	510	omap_init_hsmmc(controllers, controllers->mmc);
01971f65	511
90c62bf0 TL	512	}
	513
	514	#endif