Commit | Line | Data |
---|---|---|
90c62bf0 | 1 | /* |
d02a900b | 2 | * linux/arch/arm/mach-omap2/hsmmc.c |
90c62bf0 TL |
3 | * |
4 | * Copyright (C) 2007-2008 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Author: Texas Instruments | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
db0fefc5 AH |
12 | #include <linux/kernel.h> |
13 | #include <linux/slab.h> | |
14 | #include <linux/string.h> | |
90c62bf0 | 15 | #include <linux/delay.h> |
5e4698fc | 16 | #include <linux/gpio.h> |
90c62bf0 | 17 | #include <mach/hardware.h> |
ce491cf8 | 18 | #include <plat/mmc.h> |
e3df0fb4 | 19 | #include <plat/omap-pm.h> |
d8d0a61c | 20 | #include <plat/mux.h> |
4621d5f8 | 21 | #include <plat/omap_device.h> |
90c62bf0 | 22 | |
d8d0a61c | 23 | #include "mux.h" |
d02a900b | 24 | #include "hsmmc.h" |
4814ced5 | 25 | #include "control.h" |
90c62bf0 | 26 | |
db0fefc5 | 27 | #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) |
90c62bf0 TL |
28 | |
29 | static u16 control_pbias_offset; | |
30 | static u16 control_devconf1_offset; | |
c83c8e6c | 31 | static u16 control_mmc1; |
90c62bf0 TL |
32 | |
33 | #define HSMMC_NAME_LEN 9 | |
34 | ||
1887bde3 DK |
35 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
36 | ||
68ff0423 | 37 | static int hsmmc_get_context_loss(struct device *dev) |
1887bde3 | 38 | { |
e3df0fb4 | 39 | return omap_pm_get_dev_context_loss_count(dev); |
1887bde3 DK |
40 | } |
41 | ||
42 | #else | |
68ff0423 | 43 | #define hsmmc_get_context_loss NULL |
1887bde3 DK |
44 | #endif |
45 | ||
c83c8e6c | 46 | static void omap_hsmmc1_before_set_reg(struct device *dev, int slot, |
db0fefc5 | 47 | int power_on, int vdd) |
90c62bf0 | 48 | { |
555d503f | 49 | u32 reg, prog_io; |
90c62bf0 TL |
50 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
51 | ||
ce6f0016 AH |
52 | if (mmc->slots[0].remux) |
53 | mmc->slots[0].remux(dev, slot, power_on); | |
54 | ||
0329c377 DB |
55 | /* |
56 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | |
b583f26d | 57 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both |
0329c377 DB |
58 | * 1.8V and 3.0V modes, controlled by the PBIAS register. |
59 | * | |
60 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | |
61 | * is most naturally TWL VSIM; those pins also use PBIAS. | |
b583f26d DB |
62 | * |
63 | * FIXME handle VMMC1A as needed ... | |
0329c377 | 64 | */ |
90c62bf0 TL |
65 | if (power_on) { |
66 | if (cpu_is_omap2430()) { | |
67 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | |
68 | if ((1 << vdd) >= MMC_VDD_30_31) | |
69 | reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
70 | else | |
71 | reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
72 | omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); | |
73 | } | |
74 | ||
75 | if (mmc->slots[0].internal_clock) { | |
76 | reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
77 | reg |= OMAP2_MMCSDIO1ADPCLKISEL; | |
78 | omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); | |
79 | } | |
80 | ||
81 | reg = omap_ctrl_readl(control_pbias_offset); | |
555d503f M |
82 | if (cpu_is_omap3630()) { |
83 | /* Set MMC I/O to 52Mhz */ | |
84 | prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | |
85 | prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; | |
86 | omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); | |
87 | } else { | |
88 | reg |= OMAP2_PBIASSPEEDCTRL0; | |
89 | } | |
90c62bf0 TL |
90 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; |
91 | omap_ctrl_writel(reg, control_pbias_offset); | |
db0fefc5 AH |
92 | } else { |
93 | reg = omap_ctrl_readl(control_pbias_offset); | |
94 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | |
95 | omap_ctrl_writel(reg, control_pbias_offset); | |
96 | } | |
97 | } | |
98 | ||
c83c8e6c | 99 | static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, |
db0fefc5 AH |
100 | int power_on, int vdd) |
101 | { | |
102 | u32 reg; | |
90c62bf0 | 103 | |
db0fefc5 AH |
104 | /* 100ms delay required for PBIAS configuration */ |
105 | msleep(100); | |
90c62bf0 | 106 | |
db0fefc5 | 107 | if (power_on) { |
90c62bf0 TL |
108 | reg = omap_ctrl_readl(control_pbias_offset); |
109 | reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); | |
110 | if ((1 << vdd) <= MMC_VDD_165_195) | |
111 | reg &= ~OMAP2_PBIASLITEVMODE0; | |
112 | else | |
113 | reg |= OMAP2_PBIASLITEVMODE0; | |
114 | omap_ctrl_writel(reg, control_pbias_offset); | |
115 | } else { | |
90c62bf0 TL |
116 | reg = omap_ctrl_readl(control_pbias_offset); |
117 | reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | | |
118 | OMAP2_PBIASLITEVMODE0); | |
119 | omap_ctrl_writel(reg, control_pbias_offset); | |
120 | } | |
90c62bf0 TL |
121 | } |
122 | ||
c83c8e6c | 123 | static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, |
124 | int power_on, int vdd) | |
125 | { | |
126 | u32 reg; | |
127 | ||
128 | /* | |
129 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | |
130 | * card with Vcc regulator (from twl4030 or whatever). OMAP has both | |
131 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | |
c83c8e6c | 132 | */ |
dcf5ef3f SS |
133 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
134 | reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | |
ff2beb1d B |
135 | OMAP4_MMC1_PWRDNZ_MASK | |
136 | OMAP4_MMC1_PBIASLITE_VMODE_MASK); | |
dcf5ef3f | 137 | omap4_ctrl_pad_writel(reg, control_pbias_offset); |
c83c8e6c | 138 | } |
139 | ||
140 | static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, | |
141 | int power_on, int vdd) | |
142 | { | |
143 | u32 reg; | |
1fcecf28 | 144 | unsigned long timeout; |
c83c8e6c | 145 | |
146 | if (power_on) { | |
dcf5ef3f SS |
147 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
148 | reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; | |
c83c8e6c | 149 | if ((1 << vdd) <= MMC_VDD_165_195) |
dcf5ef3f | 150 | reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; |
c83c8e6c | 151 | else |
dcf5ef3f SS |
152 | reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; |
153 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | | |
3696d303 | 154 | OMAP4_MMC1_PWRDNZ_MASK); |
dcf5ef3f | 155 | omap4_ctrl_pad_writel(reg, control_pbias_offset); |
1fcecf28 B |
156 | |
157 | timeout = jiffies + msecs_to_jiffies(5); | |
158 | do { | |
159 | reg = omap4_ctrl_pad_readl(control_pbias_offset); | |
160 | if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK)) | |
161 | break; | |
162 | usleep_range(100, 200); | |
163 | } while (!time_after(jiffies, timeout)); | |
164 | ||
dcf5ef3f | 165 | if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { |
c83c8e6c | 166 | pr_err("Pbias Voltage is not same as LDO\n"); |
167 | /* Caution : On VMODE_ERROR Power Down MMC IO */ | |
3696d303 | 168 | reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); |
dcf5ef3f | 169 | omap4_ctrl_pad_writel(reg, control_pbias_offset); |
c83c8e6c | 170 | } |
c83c8e6c | 171 | } |
172 | } | |
173 | ||
e62245ba IG |
174 | static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) |
175 | { | |
176 | u32 reg; | |
177 | ||
d82e5190 GI |
178 | reg = omap_ctrl_readl(control_devconf1_offset); |
179 | if (mmc->slots[0].internal_clock) | |
e62245ba | 180 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; |
d82e5190 GI |
181 | else |
182 | reg &= ~OMAP2_MMCSDIO2ADPCLKISEL; | |
183 | omap_ctrl_writel(reg, control_devconf1_offset); | |
e62245ba IG |
184 | } |
185 | ||
ffa1e4ed | 186 | static void hsmmc2_before_set_reg(struct device *dev, int slot, |
db0fefc5 | 187 | int power_on, int vdd) |
90c62bf0 | 188 | { |
90c62bf0 | 189 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
b583f26d | 190 | |
ce6f0016 AH |
191 | if (mmc->slots[0].remux) |
192 | mmc->slots[0].remux(dev, slot, power_on); | |
193 | ||
e62245ba IG |
194 | if (power_on) |
195 | hsmmc2_select_input_clk_src(mmc); | |
196 | } | |
90c62bf0 | 197 | |
e62245ba IG |
198 | static int am35x_hsmmc2_set_power(struct device *dev, int slot, |
199 | int power_on, int vdd) | |
200 | { | |
201 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
202 | ||
203 | if (power_on) | |
204 | hsmmc2_select_input_clk_src(mmc); | |
205 | ||
206 | return 0; | |
9b7c18e0 AH |
207 | } |
208 | ||
03e7e170 | 209 | static int nop_mmc_set_power(struct device *dev, int slot, int power_on, |
210 | int vdd) | |
211 | { | |
212 | return 0; | |
213 | } | |
214 | ||
d8d0a61c KK |
215 | static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, |
216 | int controller_nr) | |
217 | { | |
a15164f1 TW |
218 | if (gpio_is_valid(mmc_controller->slots[0].switch_pin) && |
219 | (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) | |
d8d0a61c KK |
220 | omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, |
221 | OMAP_PIN_INPUT_PULLUP); | |
a15164f1 TW |
222 | if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) && |
223 | (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) | |
d8d0a61c KK |
224 | omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, |
225 | OMAP_PIN_INPUT_PULLUP); | |
226 | if (cpu_is_omap34xx()) { | |
227 | if (controller_nr == 0) { | |
228 | omap_mux_init_signal("sdmmc1_clk", | |
229 | OMAP_PIN_INPUT_PULLUP); | |
230 | omap_mux_init_signal("sdmmc1_cmd", | |
231 | OMAP_PIN_INPUT_PULLUP); | |
232 | omap_mux_init_signal("sdmmc1_dat0", | |
233 | OMAP_PIN_INPUT_PULLUP); | |
234 | if (mmc_controller->slots[0].caps & | |
235 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
236 | omap_mux_init_signal("sdmmc1_dat1", | |
237 | OMAP_PIN_INPUT_PULLUP); | |
238 | omap_mux_init_signal("sdmmc1_dat2", | |
239 | OMAP_PIN_INPUT_PULLUP); | |
240 | omap_mux_init_signal("sdmmc1_dat3", | |
241 | OMAP_PIN_INPUT_PULLUP); | |
242 | } | |
243 | if (mmc_controller->slots[0].caps & | |
244 | MMC_CAP_8_BIT_DATA) { | |
245 | omap_mux_init_signal("sdmmc1_dat4", | |
246 | OMAP_PIN_INPUT_PULLUP); | |
247 | omap_mux_init_signal("sdmmc1_dat5", | |
248 | OMAP_PIN_INPUT_PULLUP); | |
249 | omap_mux_init_signal("sdmmc1_dat6", | |
250 | OMAP_PIN_INPUT_PULLUP); | |
251 | omap_mux_init_signal("sdmmc1_dat7", | |
252 | OMAP_PIN_INPUT_PULLUP); | |
253 | } | |
254 | } | |
255 | if (controller_nr == 1) { | |
256 | /* MMC2 */ | |
257 | omap_mux_init_signal("sdmmc2_clk", | |
258 | OMAP_PIN_INPUT_PULLUP); | |
259 | omap_mux_init_signal("sdmmc2_cmd", | |
260 | OMAP_PIN_INPUT_PULLUP); | |
261 | omap_mux_init_signal("sdmmc2_dat0", | |
262 | OMAP_PIN_INPUT_PULLUP); | |
263 | ||
264 | /* | |
265 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 | |
266 | * need to be muxed in the board-*.c files | |
267 | */ | |
268 | if (mmc_controller->slots[0].caps & | |
269 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
270 | omap_mux_init_signal("sdmmc2_dat1", | |
271 | OMAP_PIN_INPUT_PULLUP); | |
272 | omap_mux_init_signal("sdmmc2_dat2", | |
273 | OMAP_PIN_INPUT_PULLUP); | |
274 | omap_mux_init_signal("sdmmc2_dat3", | |
275 | OMAP_PIN_INPUT_PULLUP); | |
276 | } | |
277 | if (mmc_controller->slots[0].caps & | |
278 | MMC_CAP_8_BIT_DATA) { | |
279 | omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", | |
280 | OMAP_PIN_INPUT_PULLUP); | |
281 | omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", | |
282 | OMAP_PIN_INPUT_PULLUP); | |
283 | omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", | |
284 | OMAP_PIN_INPUT_PULLUP); | |
285 | omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", | |
286 | OMAP_PIN_INPUT_PULLUP); | |
287 | } | |
288 | } | |
289 | ||
290 | /* | |
291 | * For MMC3 the pins need to be muxed in the board-*.c files | |
292 | */ | |
293 | } | |
294 | } | |
295 | ||
a98f77bb RK |
296 | static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, |
297 | struct omap_mmc_platform_data *mmc) | |
4621d5f8 KK |
298 | { |
299 | char *hc_name; | |
300 | ||
301 | hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); | |
302 | if (!hc_name) { | |
303 | pr_err("Cannot allocate memory for controller slot name\n"); | |
304 | kfree(hc_name); | |
305 | return -ENOMEM; | |
306 | } | |
307 | ||
308 | if (c->name) | |
309 | strncpy(hc_name, c->name, HSMMC_NAME_LEN); | |
310 | else | |
311 | snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", | |
312 | c->mmc, 1); | |
313 | mmc->slots[0].name = hc_name; | |
314 | mmc->nr_slots = 1; | |
315 | mmc->slots[0].caps = c->caps; | |
6fdc75de | 316 | mmc->slots[0].pm_caps = c->pm_caps; |
4621d5f8 KK |
317 | mmc->slots[0].internal_clock = !c->ext_clock; |
318 | mmc->dma_mask = 0xffffffff; | |
319 | if (cpu_is_omap44xx()) | |
320 | mmc->reg_offset = OMAP4_MMC_REG_OFFSET; | |
321 | else | |
322 | mmc->reg_offset = 0; | |
323 | ||
324 | mmc->get_context_loss_count = hsmmc_get_context_loss; | |
325 | ||
326 | mmc->slots[0].switch_pin = c->gpio_cd; | |
327 | mmc->slots[0].gpio_wp = c->gpio_wp; | |
328 | ||
329 | mmc->slots[0].remux = c->remux; | |
330 | mmc->slots[0].init_card = c->init_card; | |
331 | ||
332 | if (c->cover_only) | |
333 | mmc->slots[0].cover = 1; | |
334 | ||
335 | if (c->nonremovable) | |
336 | mmc->slots[0].nonremovable = 1; | |
337 | ||
338 | if (c->power_saving) | |
339 | mmc->slots[0].power_saving = 1; | |
340 | ||
341 | if (c->no_off) | |
342 | mmc->slots[0].no_off = 1; | |
343 | ||
b1c1df7a B |
344 | if (c->no_off_init) |
345 | mmc->slots[0].no_regulator_off_init = c->no_off_init; | |
346 | ||
4621d5f8 KK |
347 | if (c->vcc_aux_disable_is_sleep) |
348 | mmc->slots[0].vcc_aux_disable_is_sleep = 1; | |
349 | ||
350 | /* | |
351 | * NOTE: MMC slots should have a Vcc regulator set up. | |
352 | * This may be from a TWL4030-family chip, another | |
353 | * controllable regulator, or a fixed supply. | |
354 | * | |
355 | * temporary HACK: ocr_mask instead of fixed supply | |
356 | */ | |
e89715a7 A |
357 | if (cpu_is_omap3505() || cpu_is_omap3517()) |
358 | mmc->slots[0].ocr_mask = MMC_VDD_165_195 | | |
359 | MMC_VDD_26_27 | | |
360 | MMC_VDD_27_28 | | |
361 | MMC_VDD_29_30 | | |
362 | MMC_VDD_30_31 | | |
363 | MMC_VDD_31_32; | |
364 | else | |
365 | mmc->slots[0].ocr_mask = c->ocr_mask; | |
4621d5f8 | 366 | |
e62245ba | 367 | if (!cpu_is_omap3517() && !cpu_is_omap3505()) |
4621d5f8 KK |
368 | mmc->slots[0].features |= HSMMC_HAS_PBIAS; |
369 | ||
370 | if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) | |
371 | mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; | |
372 | ||
373 | switch (c->mmc) { | |
374 | case 1: | |
375 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { | |
376 | /* on-chip level shifting via PBIAS0/PBIAS1 */ | |
377 | if (cpu_is_omap44xx()) { | |
378 | mmc->slots[0].before_set_reg = | |
379 | omap4_hsmmc1_before_set_reg; | |
380 | mmc->slots[0].after_set_reg = | |
381 | omap4_hsmmc1_after_set_reg; | |
382 | } else { | |
383 | mmc->slots[0].before_set_reg = | |
384 | omap_hsmmc1_before_set_reg; | |
385 | mmc->slots[0].after_set_reg = | |
386 | omap_hsmmc1_after_set_reg; | |
387 | } | |
388 | } | |
389 | ||
e62245ba IG |
390 | if (cpu_is_omap3517() || cpu_is_omap3505()) |
391 | mmc->slots[0].set_power = nop_mmc_set_power; | |
392 | ||
4621d5f8 KK |
393 | /* OMAP3630 HSMMC1 supports only 4-bit */ |
394 | if (cpu_is_omap3630() && | |
395 | (c->caps & MMC_CAP_8_BIT_DATA)) { | |
396 | c->caps &= ~MMC_CAP_8_BIT_DATA; | |
397 | c->caps |= MMC_CAP_4_BIT_DATA; | |
398 | mmc->slots[0].caps = c->caps; | |
399 | } | |
400 | break; | |
401 | case 2: | |
e62245ba IG |
402 | if (cpu_is_omap3517() || cpu_is_omap3505()) |
403 | mmc->slots[0].set_power = am35x_hsmmc2_set_power; | |
404 | ||
4621d5f8 KK |
405 | if (c->ext_clock) |
406 | c->transceiver = 1; | |
407 | if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { | |
408 | c->caps &= ~MMC_CAP_8_BIT_DATA; | |
409 | c->caps |= MMC_CAP_4_BIT_DATA; | |
410 | } | |
4621d5f8 KK |
411 | if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { |
412 | /* off-chip level shifting, or none */ | |
ffa1e4ed | 413 | mmc->slots[0].before_set_reg = hsmmc2_before_set_reg; |
4621d5f8 KK |
414 | mmc->slots[0].after_set_reg = NULL; |
415 | } | |
416 | break; | |
ffa1e4ed | 417 | case 3: |
4621d5f8 KK |
418 | case 4: |
419 | case 5: | |
420 | mmc->slots[0].before_set_reg = NULL; | |
421 | mmc->slots[0].after_set_reg = NULL; | |
422 | break; | |
423 | default: | |
424 | pr_err("MMC%d configuration not supported!\n", c->mmc); | |
425 | kfree(hc_name); | |
426 | return -ENODEV; | |
427 | } | |
428 | return 0; | |
429 | } | |
430 | ||
97899e55 | 431 | static int omap_hsmmc_done; |
4621d5f8 KK |
432 | #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 |
433 | ||
a98f77bb | 434 | void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) |
4621d5f8 KK |
435 | { |
436 | struct omap_hwmod *oh; | |
3528c58e | 437 | struct platform_device *pdev; |
4621d5f8 KK |
438 | char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; |
439 | struct omap_mmc_platform_data *mmc_data; | |
440 | struct omap_mmc_dev_attr *mmc_dev_attr; | |
441 | char *name; | |
442 | int l; | |
4621d5f8 KK |
443 | |
444 | mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); | |
445 | if (!mmc_data) { | |
446 | pr_err("Cannot allocate memory for mmc device!\n"); | |
447 | goto done; | |
448 | } | |
449 | ||
450 | if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) { | |
451 | pr_err("%s fails!\n", __func__); | |
452 | goto done; | |
453 | } | |
454 | omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); | |
455 | ||
0005ae73 | 456 | name = "omap_hsmmc"; |
4621d5f8 KK |
457 | |
458 | l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, | |
459 | "mmc%d", ctrl_nr); | |
460 | WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN, | |
461 | "String buffer overflow in MMC%d device setup\n", ctrl_nr); | |
462 | oh = omap_hwmod_lookup(oh_name); | |
463 | if (!oh) { | |
464 | pr_err("Could not look up %s\n", oh_name); | |
465 | kfree(mmc_data->slots[0].name); | |
466 | goto done; | |
467 | } | |
468 | ||
469 | if (oh->dev_attr != NULL) { | |
470 | mmc_dev_attr = oh->dev_attr; | |
471 | mmc_data->controller_flags = mmc_dev_attr->flags; | |
472 | } | |
473 | ||
3528c58e | 474 | pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, |
f718e2c0 | 475 | sizeof(struct omap_mmc_platform_data), NULL, 0, false); |
3528c58e | 476 | if (IS_ERR(pdev)) { |
25985edc | 477 | WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); |
4621d5f8 KK |
478 | kfree(mmc_data->slots[0].name); |
479 | goto done; | |
480 | } | |
481 | /* | |
482 | * return device handle to board setup code | |
483 | * required to populate for regulator framework structure | |
484 | */ | |
3528c58e | 485 | hsmmcinfo->dev = &pdev->dev; |
4621d5f8 KK |
486 | |
487 | done: | |
488 | kfree(mmc_data); | |
489 | } | |
90c62bf0 | 490 | |
a98f77bb | 491 | void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) |
90c62bf0 | 492 | { |
c83c8e6c | 493 | u32 reg; |
90c62bf0 | 494 | |
97899e55 TL |
495 | if (omap_hsmmc_done) |
496 | return; | |
497 | ||
498 | omap_hsmmc_done = 1; | |
499 | ||
c83c8e6c | 500 | if (!cpu_is_omap44xx()) { |
501 | if (cpu_is_omap2430()) { | |
502 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | |
503 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | |
504 | } else { | |
505 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | |
506 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | |
507 | } | |
90c62bf0 | 508 | } else { |
dcf5ef3f SS |
509 | control_pbias_offset = |
510 | OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; | |
511 | control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; | |
512 | reg = omap4_ctrl_pad_readl(control_mmc1); | |
513 | reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | | |
514 | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); | |
515 | reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | | |
516 | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); | |
c862dd70 | 517 | reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | |
dcf5ef3f SS |
518 | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | |
519 | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); | |
520 | omap4_ctrl_pad_writel(reg, control_mmc1); | |
90c62bf0 TL |
521 | } |
522 | ||
4621d5f8 KK |
523 | for (; controllers->mmc; controllers++) |
524 | omap_init_hsmmc(controllers, controllers->mmc); | |
01971f65 | 525 | |
90c62bf0 TL |
526 | } |
527 | ||
528 | #endif |