[deliverable/linux.git] / arch / arm / mach-omap2 / i2c.c

/*
 * Helper module for board specific I2C bus registration
 *
 * Copyright (C) 2009 Nokia Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"

#include "prm.h"
#include "common.h"
#include "mux.h"
#include "i2c.h"

/* In register I2C_CON, Bit 15 is the I2C enable bit */
#define I2C_EN					BIT(15)
#define OMAP2_I2C_CON_OFFSET			0x24
#define OMAP4_I2C_CON_OFFSET			0xA4

#define MAX_OMAP_I2C_HWMOD_NAME_LEN	16

static void __init omap2_i2c_mux_pins(int bus_id)
{
	char mux_name[sizeof("i2c2_scl.i2c2_scl")];

	/* First I2C bus is not muxable */
	if (bus_id == 1)
		return;

	sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
	sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}

/**
 * omap_i2c_reset - reset the omap i2c module.
 * @oh: struct omap_hwmod *
 *
 * The i2c moudle in omap2, omap3 had a special sequence to reset. The
 * sequence is:
 * - Disable the I2C.
 * - Write to SOFTRESET bit.
 * - Enable the I2C.
 * - Poll on the RESETDONE bit.
 * The sequence is implemented in below function. This is called for 2420,
 * 2430 and omap3.
 */
int omap_i2c_reset(struct omap_hwmod *oh)
{
	u32 v;
	u16 i2c_con;
	int c = 0;

	if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
		i2c_con = OMAP4_I2C_CON_OFFSET;
	} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
		i2c_con = OMAP2_I2C_CON_OFFSET;
	} else {
		WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
		     oh->name);
		return -EINVAL;
	}

	/* Disable I2C */
	v = omap_hwmod_read(oh, i2c_con);
	v &= ~I2C_EN;
	omap_hwmod_write(v, oh, i2c_con);

	/* Write to the SOFTRESET bit */
	omap_hwmod_softreset(oh);

	/* Enable I2C */
	v = omap_hwmod_read(oh, i2c_con);
	v |= I2C_EN;
	omap_hwmod_write(v, oh, i2c_con);

	/* Poll on RESETDONE bit */
	omap_test_timeout((omap_hwmod_read(oh,
				oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
				MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("%s: %s: softreset failed (waited %d usec)\n",
			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
	else
		pr_debug("%s: %s: softreset in %d usec\n", __func__,
			oh->name, c);

	return 0;
}

static int __init omap_i2c_nr_ports(void)
{
	int ports = 0;

	if (cpu_is_omap24xx())
		ports = 2;
	else if (cpu_is_omap34xx())
		ports = 3;
	else if (cpu_is_omap44xx())
		ports = 4;
	return ports;
}

static const char name[] = "omap_i2c";

int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
				int bus_id)
{
	int l;
	struct omap_hwmod *oh;
	struct platform_device *pdev;
	char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
	struct omap_i2c_bus_platform_data *pdata;
	struct omap_i2c_dev_attr *dev_attr;

	if (bus_id > omap_i2c_nr_ports())
		return -EINVAL;

	omap2_i2c_mux_pins(bus_id);

	l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
	WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
		"String buffer overflow in I2C%d device setup\n", bus_id);
	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
			pr_err("Could not look up %s\n", oh_name);
			return -EEXIST;
	}

	pdata = i2c_pdata;
	/*
	 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
	 * use, and functionality implementation flags, up to the OMAP I2C
	 * driver via platform data
	 */
	pdata->rev = oh->class->rev;

	dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
	pdata->flags = dev_attr->flags;

	pdev = omap_device_build(name, bus_id, oh, pdata,
			sizeof(struct omap_i2c_bus_platform_data),
			NULL, 0, 0);
	WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);

	return PTR_RET(pdev);
}
Commit	Line	Data
b63128e8 TL	1	/*
	2	* Helper module for board specific I2C bus registration
	3	*
	4	* Copyright (C) 2009 Nokia Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* version 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	18	* 02110-1301 USA
	19	*
	20	*/
	21
e4c060db	22	#include "soc.h"
2a296c8f	23	#include "omap_hwmod.h"
25c7d49e	24	#include "omap_device.h"
b63128e8	25
b13159af PW	26	#include "prm.h"
b13159af PW	27	#include "common.h"
b63128e8	28	#include "mux.h"
3a8761c0	29	#include "i2c.h"
b63128e8	30
6d3c55fd A	31	/* In register I2C_CON, Bit 15 is the I2C enable bit */
	32	#define I2C_EN BIT(15)
	33	#define OMAP2_I2C_CON_OFFSET 0x24
	34	#define OMAP4_I2C_CON_OFFSET 0xA4
	35
3a8761c0 TL	36	#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
	37
	38	static void __init omap2_i2c_mux_pins(int bus_id)
b63128e8	39	{
f99bf16d	40	char mux_name[sizeof("i2c2_scl.i2c2_scl")];
b63128e8 TL	41
b63128e8 TL	42	/* First I2C bus is not muxable */
f99bf16d TL	43	if (bus_id == 1)
f99bf16d TL	44	return;
b63128e8	45
f99bf16d TL	46	sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
	47	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
	48	sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
	49	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
b63128e8	50	}
6d3c55fd A	51
	52	/**
	53	* omap_i2c_reset - reset the omap i2c module.
	54	* @oh: struct omap_hwmod *
	55	*
	56	* The i2c moudle in omap2, omap3 had a special sequence to reset. The
	57	* sequence is:
	58	* - Disable the I2C.
	59	* - Write to SOFTRESET bit.
	60	* - Enable the I2C.
	61	* - Poll on the RESETDONE bit.
	62	* The sequence is implemented in below function. This is called for 2420,
	63	* 2430 and omap3.
	64	*/
	65	int omap_i2c_reset(struct omap_hwmod *oh)
	66	{
	67	u32 v;
	68	u16 i2c_con;
	69	int c = 0;
	70
	71	if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
	72	i2c_con = OMAP4_I2C_CON_OFFSET;
	73	} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
	74	i2c_con = OMAP2_I2C_CON_OFFSET;
	75	} else {
	76	WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
	77	oh->name);
	78	return -EINVAL;
	79	}
	80
	81	/* Disable I2C */
	82	v = omap_hwmod_read(oh, i2c_con);
	83	v &= ~I2C_EN;
	84	omap_hwmod_write(v, oh, i2c_con);
	85
	86	/* Write to the SOFTRESET bit */
	87	omap_hwmod_softreset(oh);
	88
	89	/* Enable I2C */
	90	v = omap_hwmod_read(oh, i2c_con);
	91	v \|= I2C_EN;
	92	omap_hwmod_write(v, oh, i2c_con);
	93
	94	/* Poll on RESETDONE bit */
	95	omap_test_timeout((omap_hwmod_read(oh,
	96	oh->class->sysc->syss_offs)
	97	& SYSS_RESETDONE_MASK),
	98	MAX_MODULE_SOFTRESET_WAIT, c);
	99
	100	if (c == MAX_MODULE_SOFTRESET_WAIT)
	101	pr_warning("%s: %s: softreset failed (waited %d usec)\n",
	102	__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
	103	else
	104	pr_debug("%s: %s: softreset in %d usec\n", __func__,
	105	oh->name, c);
	106
	107	return 0;
	108	}
3a8761c0	109
c34f7c69 TL	110	static int __init omap_i2c_nr_ports(void)
	111	{
	112	int ports = 0;
	113
	114	if (cpu_is_omap24xx())
	115	ports = 2;
	116	else if (cpu_is_omap34xx())
	117	ports = 3;
	118	else if (cpu_is_omap44xx())
	119	ports = 4;
	120	return ports;
	121	}
	122
3a8761c0 TL	123	static const char name[] = "omap_i2c";
	124
	125	int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
	126	int bus_id)
	127	{
	128	int l;
	129	struct omap_hwmod *oh;
	130	struct platform_device *pdev;
	131	char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
	132	struct omap_i2c_bus_platform_data *pdata;
	133	struct omap_i2c_dev_attr *dev_attr;
	134
c34f7c69 TL	135	if (bus_id > omap_i2c_nr_ports())
	136	return -EINVAL;
	137
3a8761c0 TL	138	omap2_i2c_mux_pins(bus_id);
	139
	140	l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
	141	WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
	142	"String buffer overflow in I2C%d device setup\n", bus_id);
	143	oh = omap_hwmod_lookup(oh_name);
	144	if (!oh) {
	145	pr_err("Could not look up %s\n", oh_name);
	146	return -EEXIST;
	147	}
	148
	149	pdata = i2c_pdata;
	150	/*
	151	* pass the hwmod class's CPU-specific knowledge of I2C IP revision in
	152	* use, and functionality implementation flags, up to the OMAP I2C
	153	* driver via platform data
	154	*/
	155	pdata->rev = oh->class->rev;
	156
	157	dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
	158	pdata->flags = dev_attr->flags;
	159
	160	pdev = omap_device_build(name, bus_id, oh, pdata,
	161	sizeof(struct omap_i2c_bus_platform_data),
	162	NULL, 0, 0);
	163	WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
	164
	165	return PTR_RET(pdev);
	166	}
	167