Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
de26804b | 21 | #include <linux/random.h> |
6770b211 RB |
22 | #include <linux/slab.h> |
23 | ||
24 | #ifdef CONFIG_SOC_BUS | |
25 | #include <linux/sys_soc.h> | |
26 | #endif | |
1dbae815 | 27 | |
0ba8b9b2 | 28 | #include <asm/cputype.h> |
1dbae815 | 29 | |
4e65331c | 30 | #include "common.h" |
72d0f1c3 | 31 | |
4952af43 | 32 | #include "id.h" |
2e130fc3 | 33 | |
dbc04161 | 34 | #include "soc.h" |
4814ced5 PW |
35 | #include "control.h" |
36 | ||
42a1cc9c IK |
37 | #define OMAP4_SILICON_TYPE_STANDARD 0x01 |
38 | #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 | |
39 | ||
f9d41eef RB |
40 | #define OMAP_SOC_MAX_NAME_LENGTH 16 |
41 | ||
84a34344 | 42 | static unsigned int omap_revision; |
f9d41eef RB |
43 | static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; |
44 | static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; | |
cc0170b2 | 45 | u32 omap_features; |
84a34344 LL |
46 | |
47 | unsigned int omap_rev(void) | |
48 | { | |
49 | return omap_revision; | |
50 | } | |
51 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 52 | |
8e25ad96 KH |
53 | int omap_type(void) |
54 | { | |
55 | u32 val = 0; | |
56 | ||
edeae658 | 57 | if (cpu_is_omap24xx()) { |
8e25ad96 | 58 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
49cc485d | 59 | } else if (soc_is_am33xx() || soc_is_am43xx()) { |
fb3cfb1f | 60 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); |
edeae658 | 61 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 62 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 63 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 64 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
6852215a | 65 | } else if (soc_is_omap54xx() || soc_is_dra7xx()) { |
b13e80a8 S |
66 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); |
67 | val &= OMAP5_DEVICETYPE_MASK; | |
68 | val >>= 6; | |
69 | goto out; | |
edeae658 | 70 | } else { |
8e25ad96 KH |
71 | pr_err("Cannot detect omap type!\n"); |
72 | goto out; | |
73 | } | |
74 | ||
75 | val &= OMAP2_DEVICETYPE_MASK; | |
76 | val >>= 8; | |
77 | ||
78 | out: | |
79 | return val; | |
80 | } | |
81 | EXPORT_SYMBOL(omap_type); | |
82 | ||
83 | ||
a8823143 | 84 | /*----------------------------------------------------------------------------*/ |
097c584c | 85 | |
a8823143 TL |
86 | #define OMAP_TAP_IDCODE 0x0204 |
87 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
88 | #define OMAP_TAP_DIE_ID_1 0x021C | |
89 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
90 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 91 | |
b235e007 AG |
92 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
93 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
94 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
95 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
96 | ||
edfaf05c | 97 | #define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) |
097c584c | 98 | |
a8823143 TL |
99 | struct omap_id { |
100 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
101 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 102 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 103 | }; |
097c584c | 104 | |
a8823143 TL |
105 | /* Register values to detect the OMAP version */ |
106 | static struct omap_id omap_ids[] __initdata = { | |
107 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
108 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
109 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
110 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
111 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
112 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
113 | }; | |
097c584c | 114 | |
a8823143 TL |
115 | static void __iomem *tap_base; |
116 | static u16 tap_prod_id; | |
1dbae815 | 117 | |
2e130fc3 KRC |
118 | void omap_get_die_id(struct omap_die_id *odi) |
119 | { | |
6852215a | 120 | if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
b235e007 AG |
121 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); |
122 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
123 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
124 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
125 | ||
126 | return; | |
127 | } | |
2e130fc3 KRC |
128 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
129 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
130 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
131 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
132 | } | |
133 | ||
de26804b LW |
134 | static int __init omap_feed_randpool(void) |
135 | { | |
136 | struct omap_die_id odi; | |
137 | ||
138 | /* Throw the die ID into the entropy pool at boot */ | |
139 | omap_get_die_id(&odi); | |
140 | add_device_randomness(&odi, sizeof(odi)); | |
141 | return 0; | |
142 | } | |
143 | omap_device_initcall(omap_feed_randpool); | |
144 | ||
4de34f35 | 145 | void __init omap2xxx_check_revision(void) |
1dbae815 TL |
146 | { |
147 | int i, j; | |
a8823143 | 148 | u32 idcode, prod_id; |
1dbae815 | 149 | u16 hawkeye; |
a8823143 | 150 | u8 dev_type, rev; |
c46732bb | 151 | struct omap_die_id odi; |
1dbae815 TL |
152 | |
153 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 154 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
155 | hawkeye = (idcode >> 12) & 0xffff; |
156 | rev = (idcode >> 28) & 0x0f; | |
157 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 158 | omap_get_die_id(&odi); |
1dbae815 | 159 | |
097c584c PW |
160 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
161 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 162 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 163 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
164 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
165 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
166 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
167 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
168 | prod_id, dev_type); | |
169 | ||
1dbae815 TL |
170 | /* Check hawkeye ids */ |
171 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
172 | if (hawkeye == omap_ids[i].hawkeye) | |
173 | break; | |
174 | } | |
175 | ||
176 | if (i == ARRAY_SIZE(omap_ids)) { | |
177 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
178 | return; | |
179 | } | |
180 | ||
181 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
182 | if (dev_type == omap_ids[j].dev) | |
183 | break; | |
184 | } | |
185 | ||
186 | if (j == ARRAY_SIZE(omap_ids)) { | |
7852ec05 PW |
187 | pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", |
188 | omap_ids[i].type >> 16); | |
1dbae815 TL |
189 | j = i; |
190 | } | |
1dbae815 | 191 | |
f9d41eef RB |
192 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
193 | sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); | |
194 | ||
195 | pr_info("%s", soc_name); | |
84a34344 | 196 | if ((omap_rev() >> 8) & 0x0f) |
f9d41eef | 197 | pr_info("%s", soc_rev); |
097c584c | 198 | pr_info("\n"); |
a8823143 TL |
199 | } |
200 | ||
50a01e64 VH |
201 | #define OMAP3_SHOW_FEATURE(feat) \ |
202 | if (omap3_has_ ##feat()) \ | |
203 | printk(#feat" "); | |
204 | ||
205 | static void __init omap3_cpuinfo(void) | |
206 | { | |
207 | const char *cpu_name; | |
208 | ||
209 | /* | |
210 | * OMAP3430 and OMAP3530 are assumed to be same. | |
211 | * | |
212 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
213 | * on available features. Upon detection, update the CPU id | |
214 | * and CPU class bits. | |
215 | */ | |
216 | if (cpu_is_omap3630()) { | |
217 | cpu_name = "OMAP3630"; | |
68a88b98 | 218 | } else if (soc_is_am35xx()) { |
50a01e64 VH |
219 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; |
220 | } else if (cpu_is_ti816x()) { | |
221 | cpu_name = "TI816X"; | |
971b8a9c | 222 | } else if (soc_is_am335x()) { |
50a01e64 | 223 | cpu_name = "AM335X"; |
c04bbaa4 AM |
224 | } else if (soc_is_am437x()) { |
225 | cpu_name = "AM437x"; | |
50a01e64 VH |
226 | } else if (cpu_is_ti814x()) { |
227 | cpu_name = "TI814X"; | |
228 | } else if (omap3_has_iva() && omap3_has_sgx()) { | |
229 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
230 | cpu_name = "OMAP3430/3530"; | |
231 | } else if (omap3_has_iva()) { | |
232 | cpu_name = "OMAP3525"; | |
233 | } else if (omap3_has_sgx()) { | |
234 | cpu_name = "OMAP3515"; | |
235 | } else { | |
236 | cpu_name = "OMAP3503"; | |
237 | } | |
238 | ||
f9d41eef RB |
239 | sprintf(soc_name, "%s", cpu_name); |
240 | ||
50a01e64 | 241 | /* Print verbose information */ |
f9d41eef | 242 | pr_info("%s %s (", soc_name, soc_rev); |
50a01e64 VH |
243 | |
244 | OMAP3_SHOW_FEATURE(l2cache); | |
245 | OMAP3_SHOW_FEATURE(iva); | |
246 | OMAP3_SHOW_FEATURE(sgx); | |
247 | OMAP3_SHOW_FEATURE(neon); | |
248 | OMAP3_SHOW_FEATURE(isp); | |
249 | OMAP3_SHOW_FEATURE(192mhz_clk); | |
250 | ||
251 | printk(")\n"); | |
252 | } | |
253 | ||
8384ce07 SP |
254 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
255 | if (((status & OMAP3_ ##feat## _MASK) \ | |
256 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 257 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
258 | } |
259 | ||
4de34f35 | 260 | void __init omap3xxx_check_features(void) |
8384ce07 SP |
261 | { |
262 | u32 status; | |
263 | ||
cc0170b2 | 264 | omap_features = 0; |
8384ce07 SP |
265 | |
266 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
267 | ||
268 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
269 | OMAP3_CHECK_FEATURE(status, IVA); | |
270 | OMAP3_CHECK_FEATURE(status, SGX); | |
271 | OMAP3_CHECK_FEATURE(status, NEON); | |
272 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 | 273 | if (cpu_is_omap3630()) |
cc0170b2 | 274 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
b02b9172 | 275 | if (cpu_is_omap3430() || cpu_is_omap3630()) |
cc0170b2 | 276 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
b02b9172 PW |
277 | if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
278 | omap_rev() == OMAP3430_REV_ES3_1_2) | |
279 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 280 | |
cc0170b2 | 281 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 282 | |
1ce02996 MG |
283 | /* |
284 | * am35x fixups: | |
285 | * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as | |
286 | * reserved and therefore return 0 when read. Unfortunately, | |
287 | * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to | |
288 | * mean that a feature is present even though it isn't so clear | |
289 | * the incorrectly set feature bits. | |
290 | */ | |
291 | if (soc_is_am35xx()) | |
292 | omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); | |
293 | ||
8384ce07 SP |
294 | /* |
295 | * TODO: Get additional info (where applicable) | |
296 | * e.g. Size of L2 cache. | |
297 | */ | |
4de34f35 VH |
298 | |
299 | omap3_cpuinfo(); | |
8384ce07 SP |
300 | } |
301 | ||
4de34f35 | 302 | void __init omap4xxx_check_features(void) |
cc0170b2 A |
303 | { |
304 | u32 si_type; | |
305 | ||
42a1cc9c IK |
306 | si_type = |
307 | (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; | |
cc0170b2 | 308 | |
42a1cc9c IK |
309 | if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) |
310 | omap_features = OMAP4_HAS_PERF_SILICON; | |
cc0170b2 A |
311 | } |
312 | ||
4de34f35 | 313 | void __init ti81xx_check_features(void) |
01001712 | 314 | { |
cc0170b2 | 315 | omap_features = OMAP3_HAS_NEON; |
4de34f35 | 316 | omap3_cpuinfo(); |
01001712 HP |
317 | } |
318 | ||
7bcad170 VH |
319 | void __init am33xx_check_features(void) |
320 | { | |
321 | u32 status; | |
322 | ||
323 | omap_features = OMAP3_HAS_NEON; | |
324 | ||
325 | status = omap_ctrl_readl(AM33XX_DEV_FEATURE); | |
326 | if (status & AM33XX_SGX_MASK) | |
327 | omap_features |= OMAP3_HAS_SGX; | |
328 | ||
329 | omap3_cpuinfo(); | |
330 | } | |
331 | ||
4de34f35 | 332 | void __init omap3xxx_check_revision(void) |
a8823143 | 333 | { |
f9d41eef | 334 | const char *cpu_rev; |
a8823143 TL |
335 | u32 cpuid, idcode; |
336 | u16 hawkeye; | |
337 | u8 rev; | |
a8823143 TL |
338 | |
339 | /* | |
340 | * We cannot access revision registers on ES1.0. | |
341 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
342 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
343 | */ | |
ac52e83f | 344 | cpuid = read_cpuid_id(); |
a8823143 | 345 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { |
84a34344 | 346 | omap_revision = OMAP3430_REV_ES1_0; |
50a01e64 | 347 | cpu_rev = "1.0"; |
048f4bd7 | 348 | return; |
a8823143 TL |
349 | } |
350 | ||
351 | /* | |
352 | * Detection for 34xx ES2.0 and above can be done with just | |
353 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
354 | * Note that rev does not map directly to our defined processor | |
355 | * revision numbers as ES1.0 uses value 0. | |
356 | */ | |
357 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
358 | hawkeye = (idcode >> 12) & 0xffff; | |
359 | rev = (idcode >> 28) & 0xff; | |
097c584c | 360 | |
2456a10f NM |
361 | switch (hawkeye) { |
362 | case 0xb7ae: | |
363 | /* Handle 34xx/35xx devices */ | |
a8823143 | 364 | switch (rev) { |
048f4bd7 SP |
365 | case 0: /* Take care of early samples */ |
366 | case 1: | |
84a34344 | 367 | omap_revision = OMAP3430_REV_ES2_0; |
50a01e64 | 368 | cpu_rev = "2.0"; |
a8823143 TL |
369 | break; |
370 | case 2: | |
84a34344 | 371 | omap_revision = OMAP3430_REV_ES2_1; |
50a01e64 | 372 | cpu_rev = "2.1"; |
a8823143 TL |
373 | break; |
374 | case 3: | |
84a34344 | 375 | omap_revision = OMAP3430_REV_ES3_0; |
50a01e64 | 376 | cpu_rev = "3.0"; |
a8823143 | 377 | break; |
187e688d | 378 | case 4: |
e9acb9b6 | 379 | omap_revision = OMAP3430_REV_ES3_1; |
50a01e64 | 380 | cpu_rev = "3.1"; |
e9acb9b6 TL |
381 | break; |
382 | case 7: | |
edeae658 | 383 | /* FALLTHROUGH */ |
a8823143 TL |
384 | default: |
385 | /* Use the latest known revision as default */ | |
e9acb9b6 | 386 | omap_revision = OMAP3430_REV_ES3_1_2; |
50a01e64 | 387 | cpu_rev = "3.1.2"; |
a8823143 | 388 | } |
2456a10f | 389 | break; |
4cac6018 | 390 | case 0xb868: |
1f1b0353 PW |
391 | /* |
392 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 393 | * |
1f1b0353 | 394 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
395 | * is identified later based on the features. |
396 | */ | |
9ed2ba7a PW |
397 | switch (rev) { |
398 | case 0: | |
68a88b98 | 399 | omap_revision = AM35XX_REV_ES1_0; |
50a01e64 | 400 | cpu_rev = "1.0"; |
9ed2ba7a PW |
401 | break; |
402 | case 1: | |
403 | /* FALLTHROUGH */ | |
404 | default: | |
68a88b98 | 405 | omap_revision = AM35XX_REV_ES1_1; |
50a01e64 | 406 | cpu_rev = "1.1"; |
9ed2ba7a | 407 | } |
4cac6018 | 408 | break; |
edeae658 | 409 | case 0xb891: |
b0a1a6ce | 410 | /* Handle 36xx devices */ |
b0a1a6ce AG |
411 | |
412 | switch(rev) { | |
413 | case 0: /* Take care of early samples */ | |
414 | omap_revision = OMAP3630_REV_ES1_0; | |
50a01e64 | 415 | cpu_rev = "1.0"; |
b0a1a6ce AG |
416 | break; |
417 | case 1: | |
418 | omap_revision = OMAP3630_REV_ES1_1; | |
50a01e64 | 419 | cpu_rev = "1.1"; |
b0a1a6ce AG |
420 | break; |
421 | case 2: | |
51ec811a | 422 | /* FALLTHROUGH */ |
b0a1a6ce | 423 | default: |
51ec811a | 424 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 425 | cpu_rev = "1.2"; |
b0a1a6ce | 426 | } |
77c0870c | 427 | break; |
01001712 | 428 | case 0xb81e: |
01001712 HP |
429 | switch (rev) { |
430 | case 0: | |
431 | omap_revision = TI8168_REV_ES1_0; | |
50a01e64 | 432 | cpu_rev = "1.0"; |
01001712 HP |
433 | break; |
434 | case 1: | |
51ec811a | 435 | omap_revision = TI8168_REV_ES1_1; |
50a01e64 | 436 | cpu_rev = "1.1"; |
3b32b7d6 | 437 | break; |
a5f93d9d AM |
438 | case 2: |
439 | omap_revision = TI8168_REV_ES2_0; | |
440 | cpu_rev = "2.0"; | |
441 | break; | |
442 | case 3: | |
443 | /* FALLTHROUGH */ | |
444 | default: | |
445 | omap_revision = TI8168_REV_ES2_1; | |
446 | cpu_rev = "2.1"; | |
01001712 HP |
447 | } |
448 | break; | |
1e6cb146 | 449 | case 0xb944: |
5af044f4 AC |
450 | switch (rev) { |
451 | case 0: | |
452 | omap_revision = AM335X_REV_ES1_0; | |
453 | cpu_rev = "1.0"; | |
454 | break; | |
455 | case 1: | |
5af044f4 AC |
456 | omap_revision = AM335X_REV_ES2_0; |
457 | cpu_rev = "2.0"; | |
458 | break; | |
d240ef30 VH |
459 | case 2: |
460 | /* FALLTHROUGH */ | |
461 | default: | |
462 | omap_revision = AM335X_REV_ES2_1; | |
463 | cpu_rev = "2.1"; | |
464 | break; | |
5af044f4 | 465 | } |
c2d13554 | 466 | break; |
c04bbaa4 | 467 | case 0xb98c: |
4a2ed4c0 LV |
468 | switch (rev) { |
469 | case 0: | |
470 | omap_revision = AM437X_REV_ES1_0; | |
471 | cpu_rev = "1.0"; | |
472 | break; | |
473 | case 1: | |
474 | /* FALLTHROUGH */ | |
475 | default: | |
476 | omap_revision = AM437X_REV_ES1_1; | |
477 | cpu_rev = "1.1"; | |
478 | break; | |
479 | } | |
c04bbaa4 | 480 | break; |
4390f5b2 HP |
481 | case 0xb8f2: |
482 | switch (rev) { | |
483 | case 0: | |
484 | /* FALLTHROUGH */ | |
485 | case 1: | |
486 | omap_revision = TI8148_REV_ES1_0; | |
50a01e64 | 487 | cpu_rev = "1.0"; |
4390f5b2 HP |
488 | break; |
489 | case 2: | |
490 | omap_revision = TI8148_REV_ES2_0; | |
50a01e64 | 491 | cpu_rev = "2.0"; |
4390f5b2 HP |
492 | break; |
493 | case 3: | |
494 | /* FALLTHROUGH */ | |
495 | default: | |
496 | omap_revision = TI8148_REV_ES2_1; | |
50a01e64 | 497 | cpu_rev = "2.1"; |
4390f5b2 HP |
498 | break; |
499 | } | |
1e6cb146 | 500 | break; |
2456a10f | 501 | default: |
51ec811a | 502 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 503 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 504 | cpu_rev = "1.2"; |
51ec811a | 505 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
a8823143 | 506 | } |
f9d41eef | 507 | sprintf(soc_rev, "ES%s", cpu_rev); |
1dbae815 TL |
508 | } |
509 | ||
4de34f35 | 510 | void __init omap4xxx_check_revision(void) |
b570e0ec SS |
511 | { |
512 | u32 idcode; | |
513 | u16 hawkeye; | |
514 | u8 rev; | |
b570e0ec SS |
515 | |
516 | /* | |
517 | * The IC rev detection is done with hawkeye and rev. | |
518 | * Note that rev does not map directly to defined processor | |
519 | * revision numbers as ES1.0 uses value 0. | |
520 | */ | |
521 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
522 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 523 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 524 | |
ed6be0ba | 525 | /* |
fa54dccd | 526 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
527 | * Use ARM register to detect the correct ES version |
528 | */ | |
ec023e46 | 529 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ac52e83f | 530 | idcode = read_cpuid_id(); |
ed6be0ba SS |
531 | rev = (idcode & 0xf) - 1; |
532 | } | |
533 | ||
534 | switch (hawkeye) { | |
535 | case 0xb852: | |
536 | switch (rev) { | |
537 | case 0: | |
538 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
539 | break; |
540 | case 1: | |
e49c4d27 | 541 | default: |
ed6be0ba | 542 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
543 | } |
544 | break; | |
545 | case 0xb95c: | |
546 | switch (rev) { | |
547 | case 3: | |
548 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 549 | break; |
e49c4d27 | 550 | case 4: |
e49c4d27 | 551 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
552 | break; |
553 | case 6: | |
554 | default: | |
555 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
556 | } |
557 | break; | |
fa54dccd A |
558 | case 0xb94e: |
559 | switch (rev) { | |
560 | case 0: | |
fa54dccd | 561 | omap_revision = OMAP4460_REV_ES1_0; |
fa54dccd | 562 | break; |
33ee0db5 CL |
563 | case 2: |
564 | default: | |
565 | omap_revision = OMAP4460_REV_ES1_1; | |
566 | break; | |
fa54dccd A |
567 | } |
568 | break; | |
ec023e46 LI |
569 | case 0xb975: |
570 | switch (rev) { | |
571 | case 0: | |
572 | default: | |
573 | omap_revision = OMAP4470_REV_ES1_0; | |
574 | break; | |
575 | } | |
576 | break; | |
ed6be0ba | 577 | default: |
e49c4d27 | 578 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 579 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
580 | } |
581 | ||
f9d41eef RB |
582 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
583 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, | |
584 | (omap_rev() >> 8) & 0xf); | |
585 | pr_info("%s %s\n", soc_name, soc_rev); | |
b570e0ec SS |
586 | } |
587 | ||
b13e80a8 S |
588 | void __init omap5xxx_check_revision(void) |
589 | { | |
590 | u32 idcode; | |
591 | u16 hawkeye; | |
592 | u8 rev; | |
593 | ||
594 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
595 | hawkeye = (idcode >> 12) & 0xffff; | |
596 | rev = (idcode >> 28) & 0xff; | |
597 | switch (hawkeye) { | |
598 | case 0xb942: | |
599 | switch (rev) { | |
600 | case 0: | |
aa2f4b16 NM |
601 | /* No support for ES1.0 Test chip */ |
602 | BUG(); | |
5a898a78 SS |
603 | case 1: |
604 | default: | |
605 | omap_revision = OMAP5430_REV_ES2_0; | |
b13e80a8 S |
606 | } |
607 | break; | |
608 | ||
609 | case 0xb998: | |
610 | switch (rev) { | |
611 | case 0: | |
aa2f4b16 NM |
612 | /* No support for ES1.0 Test chip */ |
613 | BUG(); | |
5a898a78 SS |
614 | case 1: |
615 | default: | |
616 | omap_revision = OMAP5432_REV_ES2_0; | |
b13e80a8 S |
617 | } |
618 | break; | |
619 | ||
620 | default: | |
621 | /* Unknown default to latest silicon rev as default*/ | |
5a898a78 | 622 | omap_revision = OMAP5430_REV_ES2_0; |
b13e80a8 S |
623 | } |
624 | ||
f9d41eef RB |
625 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
626 | sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); | |
627 | ||
628 | pr_info("%s %s\n", soc_name, soc_rev); | |
b13e80a8 S |
629 | } |
630 | ||
733d20ee NM |
631 | void __init dra7xxx_check_revision(void) |
632 | { | |
633 | u32 idcode; | |
634 | u16 hawkeye; | |
635 | u8 rev; | |
636 | ||
637 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
638 | hawkeye = (idcode >> 12) & 0xffff; | |
639 | rev = (idcode >> 28) & 0xff; | |
640 | switch (hawkeye) { | |
641 | case 0xb990: | |
642 | switch (rev) { | |
643 | case 0: | |
644 | omap_revision = DRA752_REV_ES1_0; | |
645 | break; | |
646 | case 1: | |
647 | default: | |
648 | omap_revision = DRA752_REV_ES1_1; | |
649 | } | |
650 | break; | |
651 | ||
73d20280 NM |
652 | case 0xb9bc: |
653 | switch (rev) { | |
654 | case 0: | |
655 | omap_revision = DRA722_REV_ES1_0; | |
656 | break; | |
657 | default: | |
658 | /* If we have no new revisions */ | |
659 | omap_revision = DRA722_REV_ES1_0; | |
660 | break; | |
661 | } | |
662 | break; | |
663 | ||
733d20ee NM |
664 | default: |
665 | /* Unknown default to latest silicon rev as default*/ | |
666 | pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n", | |
667 | __func__, idcode, hawkeye, rev); | |
668 | omap_revision = DRA752_REV_ES1_1; | |
669 | } | |
670 | ||
671 | sprintf(soc_name, "DRA%03x", omap_rev() >> 16); | |
672 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, | |
673 | (omap_rev() >> 8) & 0xf); | |
674 | ||
675 | pr_info("%s %s\n", soc_name, soc_rev); | |
676 | } | |
677 | ||
a8823143 TL |
678 | /* |
679 | * Set up things for map_io and processor detection later on. Gets called | |
680 | * pretty much first thing from board init. For multi-omap, this gets | |
681 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
682 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
683 | * is done. | |
684 | */ | |
b6a4226c | 685 | void __init omap2_set_globals_tap(u32 class, void __iomem *tap) |
0e564848 | 686 | { |
b6a4226c PW |
687 | omap_revision = class; |
688 | tap_base = tap; | |
0e564848 | 689 | |
b6a4226c | 690 | /* XXX What is this intended to do? */ |
a8823143 | 691 | if (cpu_is_omap34xx()) |
0e564848 TL |
692 | tap_prod_id = 0x0210; |
693 | else | |
694 | tap_prod_id = 0x0208; | |
695 | } | |
6770b211 RB |
696 | |
697 | #ifdef CONFIG_SOC_BUS | |
698 | ||
415ab328 | 699 | static const char * const omap_types[] = { |
6770b211 RB |
700 | [OMAP2_DEVICE_TYPE_TEST] = "TST", |
701 | [OMAP2_DEVICE_TYPE_EMU] = "EMU", | |
702 | [OMAP2_DEVICE_TYPE_SEC] = "HS", | |
703 | [OMAP2_DEVICE_TYPE_GP] = "GP", | |
704 | [OMAP2_DEVICE_TYPE_BAD] = "BAD", | |
705 | }; | |
706 | ||
707 | static const char * __init omap_get_family(void) | |
708 | { | |
709 | if (cpu_is_omap24xx()) | |
710 | return kasprintf(GFP_KERNEL, "OMAP2"); | |
711 | else if (cpu_is_omap34xx()) | |
712 | return kasprintf(GFP_KERNEL, "OMAP3"); | |
713 | else if (cpu_is_omap44xx()) | |
714 | return kasprintf(GFP_KERNEL, "OMAP4"); | |
715 | else if (soc_is_omap54xx()) | |
716 | return kasprintf(GFP_KERNEL, "OMAP5"); | |
7a2e0513 AM |
717 | else if (soc_is_am43xx()) |
718 | return kasprintf(GFP_KERNEL, "AM43xx"); | |
733d20ee NM |
719 | else if (soc_is_dra7xx()) |
720 | return kasprintf(GFP_KERNEL, "DRA7"); | |
6770b211 RB |
721 | else |
722 | return kasprintf(GFP_KERNEL, "Unknown"); | |
723 | } | |
724 | ||
725 | static ssize_t omap_get_type(struct device *dev, | |
726 | struct device_attribute *attr, | |
727 | char *buf) | |
728 | { | |
729 | return sprintf(buf, "%s\n", omap_types[omap_type()]); | |
730 | } | |
731 | ||
732 | static struct device_attribute omap_soc_attr = | |
733 | __ATTR(type, S_IRUGO, omap_get_type, NULL); | |
734 | ||
735 | void __init omap_soc_device_init(void) | |
736 | { | |
737 | struct device *parent; | |
738 | struct soc_device *soc_dev; | |
739 | struct soc_device_attribute *soc_dev_attr; | |
740 | ||
741 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
742 | if (!soc_dev_attr) | |
743 | return; | |
744 | ||
745 | soc_dev_attr->machine = soc_name; | |
746 | soc_dev_attr->family = omap_get_family(); | |
747 | soc_dev_attr->revision = soc_rev; | |
748 | ||
749 | soc_dev = soc_device_register(soc_dev_attr); | |
b1dd11d6 | 750 | if (IS_ERR(soc_dev)) { |
6770b211 RB |
751 | kfree(soc_dev_attr); |
752 | return; | |
753 | } | |
754 | ||
755 | parent = soc_device_to_device(soc_dev); | |
b1dd11d6 | 756 | device_create_file(parent, &omap_soc_attr); |
6770b211 RB |
757 | } |
758 | #endif /* CONFIG_SOC_BUS */ |