[deliverable/linux.git] / arch / arm / mach-omap2 / id.c

/*
 * linux/arch/arm/mach-omap2/id.c
 *
 * OMAP2 CPU identification code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/cputype.h>

#include <plat/common.h>
#include <plat/control.h>
#include <plat/cpu.h>

#include <mach/id.h>

static struct omap_chip_id omap_chip;
static unsigned int omap_revision;

u32 omap3_features;

unsigned int omap_rev(void)
{
	return omap_revision;
}
EXPORT_SYMBOL(omap_rev);

/**
 * omap_chip_is - test whether currently running OMAP matches a chip type
 * @oc: omap_chip_t to test against
 *
 * Test whether the currently-running OMAP chip matches the supplied
 * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
 */
int omap_chip_is(struct omap_chip_id oci)
{
	return (oci.oc & omap_chip.oc) ? 1 : 0;
}
EXPORT_SYMBOL(omap_chip_is);

int omap_type(void)
{
	u32 val = 0;

	if (cpu_is_omap24xx()) {
		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
	} else if (cpu_is_omap34xx()) {
		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
	} else if (cpu_is_omap44xx()) {
		val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
	} else {
		pr_err("Cannot detect omap type!\n");
		goto out;
	}

	val &= OMAP2_DEVICETYPE_MASK;
	val >>= 8;

out:
	return val;
}
EXPORT_SYMBOL(omap_type);


/*----------------------------------------------------------------------------*/

#define OMAP_TAP_IDCODE		0x0204
#define OMAP_TAP_DIE_ID_0	0x0218
#define OMAP_TAP_DIE_ID_1	0x021C
#define OMAP_TAP_DIE_ID_2	0x0220
#define OMAP_TAP_DIE_ID_3	0x0224

#define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))

struct omap_id {
	u16	hawkeye;	/* Silicon type (Hawkeye id) */
	u8	dev;		/* Device type from production_id reg */
	u32	type;		/* Combined type id copied to omap_revision */
};

/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
};

static void __iomem *tap_base;
static u16 tap_prod_id;

void omap_get_die_id(struct omap_die_id *odi)
{
	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
}

static void __init omap24xx_check_revision(void)
{
	int i, j;
	u32 idcode, prod_id;
	u16 hawkeye;
	u8  dev_type, rev;

	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	prod_id = read_tap_reg(tap_prod_id);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0x0f;
	dev_type = (prod_id >> 16) & 0x0f;

	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
		 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_0));
	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_1),
		 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_2));
	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_3));
	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
		 prod_id, dev_type);

	/* Check hawkeye ids */
	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
		if (hawkeye == omap_ids[i].hawkeye)
			break;
	}

	if (i == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP CPU id\n");
		return;
	}

	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
		if (dev_type == omap_ids[j].dev)
			break;
	}

	if (j == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP device type. "
				"Handling it as OMAP%04x\n",
				omap_ids[i].type >> 16);
		j = i;
	}

	pr_info("OMAP%04x", omap_rev() >> 16);
	if ((omap_rev() >> 8) & 0x0f)
		pr_info("ES%x", (omap_rev() >> 12) & 0xf);
	pr_info("\n");
}

#define OMAP3_CHECK_FEATURE(status,feat)				\
	if (((status & OMAP3_ ##feat## _MASK) 				\
		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
		omap3_features |= OMAP3_HAS_ ##feat;			\
	}

static void __init omap3_check_features(void)
{
	u32 status;

	omap3_features = 0;

	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);

	OMAP3_CHECK_FEATURE(status, L2CACHE);
	OMAP3_CHECK_FEATURE(status, IVA);
	OMAP3_CHECK_FEATURE(status, SGX);
	OMAP3_CHECK_FEATURE(status, NEON);
	OMAP3_CHECK_FEATURE(status, ISP);
	if (cpu_is_omap3630())
		omap3_features |= OMAP3_HAS_192MHZ_CLK;
	if (!cpu_is_omap3505() && !cpu_is_omap3517())
		omap3_features |= OMAP3_HAS_IO_WAKEUP;

	/*
	 * TODO: Get additional info (where applicable)
	 *       e.g. Size of L2 cache.
	 */
}

static void __init omap3_check_revision(void)
{
	u32 cpuid, idcode;
	u16 hawkeye;
	u8 rev;

	omap_chip.oc = CHIP_IS_OMAP3430;

	/*
	 * We cannot access revision registers on ES1.0.
	 * If the processor type is Cortex-A8 and the revision is 0x0
	 * it means its Cortex r0p0 which is 3430 ES1.0.
	 */
	cpuid = read_cpuid(CPUID_ID);
	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
		omap_revision = OMAP3430_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP3430ES1;
		return;
	}

	/*
	 * Detection for 34xx ES2.0 and above can be done with just
	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
	 * Note that rev does not map directly to our defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	switch (hawkeye) {
	case 0xb7ae:
		/* Handle 34xx/35xx devices */
		switch (rev) {
		case 0: /* Take care of early samples */
		case 1:
			omap_revision = OMAP3430_REV_ES2_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 2:
			omap_revision = OMAP3430_REV_ES2_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 3:
			omap_revision = OMAP3430_REV_ES3_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
			break;
		case 4:
			omap_revision = OMAP3430_REV_ES3_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
			break;
		case 7:
		/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			omap_revision = OMAP3430_REV_ES3_1_2;

			/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		}
		break;
	case 0xb868:
		/* Handle OMAP35xx/AM35xx devices
		 *
		 * Set the device to be OMAP3505 here. Actual device
		 * is identified later based on the features.
		 *
		 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
		 */
		omap_revision = OMAP3505_REV(rev);
		omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		break;
	case 0xb891:
	/* FALLTHROUGH */
	default:
		/* Unknown default to latest silicon rev as default*/
		omap_revision = OMAP3630_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP3630ES1;
	}
}

static void __init omap4_check_revision(void)
{
	u32 idcode;
	u16 hawkeye;
	u8 rev;
	char *rev_name = "ES1.0";

	/*
	 * The IC rev detection is done with hawkeye and rev.
	 * Note that rev does not map directly to defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	if ((hawkeye == 0xb852) && (rev == 0x0)) {
		omap_revision = OMAP4430_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP4430ES1;
		pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
		return;
	}

	pr_err("Unknown OMAP4 CPU id\n");
}

#define OMAP3_SHOW_FEATURE(feat)		\
	if (omap3_has_ ##feat())		\
		printk(#feat" ");

static void __init omap3_cpuinfo(void)
{
	u8 rev = GET_OMAP_REVISION();
	char cpu_name[16], cpu_rev[16];

	/* OMAP3430 and OMAP3530 are assumed to be same.
	 *
	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	 * on available features. Upon detection, update the CPU id
	 * and CPU class bits.
	 */
	if (cpu_is_omap3630()) {
		strcpy(cpu_name, "OMAP3630");
	} else if (cpu_is_omap3505()) {
		/*
		 * AM35xx devices
		 */
		if (omap3_has_sgx()) {
			omap_revision = OMAP3517_REV(rev);
			strcpy(cpu_name, "AM3517");
		} else {
			/* Already set in omap3_check_revision() */
			strcpy(cpu_name, "AM3505");
		}
	} else if (omap3_has_iva() && omap3_has_sgx()) {
		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
		strcpy(cpu_name, "OMAP3430/3530");
	} else if (omap3_has_iva()) {
		omap_revision = OMAP3525_REV(rev);
		strcpy(cpu_name, "OMAP3525");
	} else if (omap3_has_sgx()) {
		omap_revision = OMAP3515_REV(rev);
		strcpy(cpu_name, "OMAP3515");
	} else {
		omap_revision = OMAP3503_REV(rev);
		strcpy(cpu_name, "OMAP3503");
	}

	switch (rev) {
	case OMAP_REVBITS_00:
		strcpy(cpu_rev, "1.0");
		break;
	case OMAP_REVBITS_10:
		strcpy(cpu_rev, "2.0");
		break;
	case OMAP_REVBITS_20:
		strcpy(cpu_rev, "2.1");
		break;
	case OMAP_REVBITS_30:
		strcpy(cpu_rev, "3.0");
		break;
	case OMAP_REVBITS_40:
	/* FALLTHROUGH */
	default:
		/* Use the latest known revision as default */
		strcpy(cpu_rev, "3.1");
	}

	/* Print verbose information */
	pr_info("%s ES%s (", cpu_name, cpu_rev);

	OMAP3_SHOW_FEATURE(l2cache);
	OMAP3_SHOW_FEATURE(iva);
	OMAP3_SHOW_FEATURE(sgx);
	OMAP3_SHOW_FEATURE(neon);
	OMAP3_SHOW_FEATURE(isp);
	OMAP3_SHOW_FEATURE(192mhz_clk);

	printk(")\n");
}

/*
 * Try to detect the exact revision of the omap we're running on
 */
void __init omap2_check_revision(void)
{
	/*
	 * At this point we have an idea about the processor revision set
	 * earlier with omap2_set_globals_tap().
	 */
	if (cpu_is_omap24xx()) {
		omap24xx_check_revision();
	} else if (cpu_is_omap34xx()) {
		omap3_check_revision();
		omap3_check_features();
		omap3_cpuinfo();
		return;
	} else if (cpu_is_omap44xx()) {
		omap4_check_revision();
		return;
	} else {
		pr_err("OMAP revision unknown, please fix!\n");
	}

	/*
	 * OK, now we know the exact revision. Initialize omap_chip bits
	 * for powerdowmain and clockdomain code.
	 */
	if (cpu_is_omap243x()) {
		/* Currently only supports 2430ES2.1 and 2430-all */
		omap_chip.oc |= CHIP_IS_OMAP2430;
		return;
	} else if (cpu_is_omap242x()) {
		/* Currently only supports 2420ES2.1.1 and 2420-all */
		omap_chip.oc |= CHIP_IS_OMAP2420;
		return;
	}

	pr_err("Uninitialized omap_chip, please fix!\n");
}

/*
 * Set up things for map_io and processor detection later on. Gets called
 * pretty much first thing from board init. For multi-omap, this gets
 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 * detect the exact revision later on in omap2_detect_revision() once map_io
 * is done.
 */
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
{
	omap_revision = omap2_globals->class;
	tap_base = omap2_globals->tap;

	if (cpu_is_omap34xx())
		tap_prod_id = 0x0210;
	else
		tap_prod_id = 0x0208;
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/id.c
	3	*
	4	* OMAP2 CPU identification code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
44169075 SS	9	* Copyright (C) 2009 Texas Instruments
	10	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	11	*
1dbae815 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
1dbae815 TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
fced80c7	20	#include <linux/io.h>
1dbae815	21
0ba8b9b2	22	#include <asm/cputype.h>
1dbae815	23
ce491cf8 TL	24	#include <plat/common.h>
	25	#include <plat/control.h>
	26	#include <plat/cpu.h>
72d0f1c3	27
2e130fc3 KRC	28	#include <mach/id.h>
2e130fc3 KRC	29
097c584c	30	static struct omap_chip_id omap_chip;
84a34344 LL	31	static unsigned int omap_revision;
84a34344 LL	32
8384ce07	33	u32 omap3_features;
84a34344 LL	34
	35	unsigned int omap_rev(void)
	36	{
	37	return omap_revision;
	38	}
	39	EXPORT_SYMBOL(omap_rev);
097c584c PW	40
	41	/**
	42	* omap_chip_is - test whether currently running OMAP matches a chip type
	43	* @oc: omap_chip_t to test against
	44	*
	45	* Test whether the currently-running OMAP chip matches the supplied
	46	* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
	47	*/
	48	int omap_chip_is(struct omap_chip_id oci)
	49	{
	50	return (oci.oc & omap_chip.oc) ? 1 : 0;
	51	}
	52	EXPORT_SYMBOL(omap_chip_is);
	53
8e25ad96 KH	54	int omap_type(void)
	55	{
	56	u32 val = 0;
	57
edeae658	58	if (cpu_is_omap24xx()) {
8e25ad96	59	val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
edeae658	60	} else if (cpu_is_omap34xx()) {
8e25ad96	61	val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
737daa03 SS	62	} else if (cpu_is_omap44xx()) {
737daa03 SS	63	val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
edeae658	64	} else {
8e25ad96 KH	65	pr_err("Cannot detect omap type!\n");
	66	goto out;
	67	}
	68
	69	val &= OMAP2_DEVICETYPE_MASK;
	70	val >>= 8;
	71
	72	out:
	73	return val;
	74	}
	75	EXPORT_SYMBOL(omap_type);
	76
	77
a8823143	78	/----------------------------------------------------------------------------/
097c584c	79
a8823143 TL	80	#define OMAP_TAP_IDCODE 0x0204
	81	#define OMAP_TAP_DIE_ID_0 0x0218
	82	#define OMAP_TAP_DIE_ID_1 0x021C
	83	#define OMAP_TAP_DIE_ID_2 0x0220
	84	#define OMAP_TAP_DIE_ID_3 0x0224
097c584c	85
a8823143	86	#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
097c584c	87
a8823143 TL	88	struct omap_id {
	89	u16 hawkeye; /* Silicon type (Hawkeye id) */
	90	u8 dev; /* Device type from production_id reg */
84a34344	91	u32 type; /* Combined type id copied to omap_revision */
a8823143	92	};
097c584c	93
a8823143 TL	94	/* Register values to detect the OMAP version */
	95	static struct omap_id omap_ids[] __initdata = {
	96	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	97	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	98	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	99	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	100	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	101	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
	102	};
097c584c	103
a8823143 TL	104	static void __iomem *tap_base;
a8823143 TL	105	static u16 tap_prod_id;
1dbae815	106
2e130fc3 KRC	107	void omap_get_die_id(struct omap_die_id *odi)
	108	{
	109	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
	110	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
	111	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
	112	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
	113	}
	114
5ebc0d52	115	static void __init omap24xx_check_revision(void)
1dbae815 TL	116	{
1dbae815 TL	117	int i, j;
a8823143	118	u32 idcode, prod_id;
1dbae815	119	u16 hawkeye;
a8823143	120	u8 dev_type, rev;
1dbae815 TL	121
1dbae815 TL	122	idcode = read_tap_reg(OMAP_TAP_IDCODE);
0e564848	123	prod_id = read_tap_reg(tap_prod_id);
1dbae815 TL	124	hawkeye = (idcode >> 12) & 0xffff;
	125	rev = (idcode >> 28) & 0x0f;
	126	dev_type = (prod_id >> 16) & 0x0f;
	127
097c584c PW	128	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
	129	idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	130	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
	131	read_tap_reg(OMAP_TAP_DIE_ID_0));
	132	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
	133	read_tap_reg(OMAP_TAP_DIE_ID_1),
	134	(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	135	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
	136	read_tap_reg(OMAP_TAP_DIE_ID_2));
	137	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
	138	read_tap_reg(OMAP_TAP_DIE_ID_3));
	139	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
	140	prod_id, dev_type);
	141
1dbae815 TL	142	/* Check hawkeye ids */
	143	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
	144	if (hawkeye == omap_ids[i].hawkeye)
	145	break;
	146	}
	147
	148	if (i == ARRAY_SIZE(omap_ids)) {
	149	printk(KERN_ERR "Unknown OMAP CPU id\n");
	150	return;
	151	}
	152
	153	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
	154	if (dev_type == omap_ids[j].dev)
	155	break;
	156	}
	157
	158	if (j == ARRAY_SIZE(omap_ids)) {
	159	printk(KERN_ERR "Unknown OMAP device type. "
	160	"Handling it as OMAP%04x\n",
	161	omap_ids[i].type >> 16);
	162	j = i;
	163	}
1dbae815	164
84a34344 LL	165	pr_info("OMAP%04x", omap_rev() >> 16);
	166	if ((omap_rev() >> 8) & 0x0f)
	167	pr_info("ES%x", (omap_rev() >> 12) & 0xf);
097c584c	168	pr_info("\n");
a8823143 TL	169	}
a8823143 TL	170
8384ce07 SP	171	#define OMAP3_CHECK_FEATURE(status,feat) \
	172	if (((status & OMAP3_ ##feat## _MASK) \
	173	>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
	174	omap3_features \|= OMAP3_HAS_ ##feat; \
	175	}
	176
5ebc0d52	177	static void __init omap3_check_features(void)
8384ce07 SP	178	{
	179	u32 status;
	180
	181	omap3_features = 0;
	182
	183	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
	184
	185	OMAP3_CHECK_FEATURE(status, L2CACHE);
	186	OMAP3_CHECK_FEATURE(status, IVA);
	187	OMAP3_CHECK_FEATURE(status, SGX);
	188	OMAP3_CHECK_FEATURE(status, NEON);
	189	OMAP3_CHECK_FEATURE(status, ISP);
7356f0b2 VB	190	if (cpu_is_omap3630())
7356f0b2 VB	191	omap3_features \|= OMAP3_HAS_192MHZ_CLK;
ad0c63f1	192	if (!cpu_is_omap3505() && !cpu_is_omap3517())
ad0c63f1	193	omap3_features \|= OMAP3_HAS_IO_WAKEUP;
8384ce07 SP	194
	195	/*
	196	* TODO: Get additional info (where applicable)
	197	* e.g. Size of L2 cache.
	198	*/
	199	}
	200
5ebc0d52	201	static void __init omap3_check_revision(void)
a8823143 TL	202	{
	203	u32 cpuid, idcode;
	204	u16 hawkeye;
	205	u8 rev;
a8823143	206
e9acb9b6 TL	207	omap_chip.oc = CHIP_IS_OMAP3430;
e9acb9b6 TL	208
a8823143 TL	209	/*
	210	* We cannot access revision registers on ES1.0.
	211	* If the processor type is Cortex-A8 and the revision is 0x0
	212	* it means its Cortex r0p0 which is 3430 ES1.0.
	213	*/
	214	cpuid = read_cpuid(CPUID_ID);
	215	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
84a34344	216	omap_revision = OMAP3430_REV_ES1_0;
e9acb9b6	217	omap_chip.oc \|= CHIP_IS_OMAP3430ES1;
048f4bd7	218	return;
a8823143 TL	219	}
	220
	221	/*
	222	* Detection for 34xx ES2.0 and above can be done with just
	223	* hawkeye and rev. See TRM 1.5.2 Device Identification.
	224	* Note that rev does not map directly to our defined processor
	225	* revision numbers as ES1.0 uses value 0.
	226	*/
	227	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	228	hawkeye = (idcode >> 12) & 0xffff;
	229	rev = (idcode >> 28) & 0xff;
097c584c	230
2456a10f NM	231	switch (hawkeye) {
	232	case 0xb7ae:
	233	/* Handle 34xx/35xx devices */
a8823143	234	switch (rev) {
048f4bd7 SP	235	case 0: /* Take care of early samples */
048f4bd7 SP	236	case 1:
84a34344	237	omap_revision = OMAP3430_REV_ES2_0;
e9acb9b6	238	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	239	break;
a8823143 TL	240	case 2:
84a34344	241	omap_revision = OMAP3430_REV_ES2_1;
e9acb9b6	242	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	243	break;
a8823143 TL	244	case 3:
84a34344	245	omap_revision = OMAP3430_REV_ES3_0;
e9acb9b6	246	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_0;
a8823143	247	break;
187e688d	248	case 4:
e9acb9b6 TL	249	omap_revision = OMAP3430_REV_ES3_1;
	250	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
	251	break;
	252	case 7:
edeae658	253	/* FALLTHROUGH */
a8823143 TL	254	default:
a8823143 TL	255	/* Use the latest known revision as default */
e9acb9b6 TL	256	omap_revision = OMAP3430_REV_ES3_1_2;
	257
	258	/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
	259	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
a8823143	260	}
2456a10f	261	break;
4cac6018 SP	262	case 0xb868:
	263	/* Handle OMAP35xx/AM35xx devices
	264	*
	265	* Set the device to be OMAP3505 here. Actual device
	266	* is identified later based on the features.
e9acb9b6 TL	267	*
e9acb9b6 TL	268	* REVISIT: AM3505/AM3517 should have their own CHIP_IS
4cac6018 SP	269	*/
4cac6018 SP	270	omap_revision = OMAP3505_REV(rev);
e9acb9b6	271	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
4cac6018	272	break;
edeae658 FB	273	case 0xb891:
edeae658 FB	274	/* FALLTHROUGH */
2456a10f NM	275	default:
	276	/* Unknown default to latest silicon rev as default*/
	277	omap_revision = OMAP3630_REV_ES1_0;
e9acb9b6	278	omap_chip.oc \|= CHIP_IS_OMAP3630ES1;
a8823143	279	}
1dbae815 TL	280	}
1dbae815 TL	281
5ebc0d52	282	static void __init omap4_check_revision(void)
b570e0ec SS	283	{
	284	u32 idcode;
	285	u16 hawkeye;
	286	u8 rev;
	287	char *rev_name = "ES1.0";
	288
	289	/*
	290	* The IC rev detection is done with hawkeye and rev.
	291	* Note that rev does not map directly to defined processor
	292	* revision numbers as ES1.0 uses value 0.
	293	*/
	294	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	295	hawkeye = (idcode >> 12) & 0xffff;
	296	rev = (idcode >> 28) & 0xff;
	297
	298	if ((hawkeye == 0xb852) && (rev == 0x0)) {
	299	omap_revision = OMAP4430_REV_ES1_0;
c6a6e6e2	300	omap_chip.oc \|= CHIP_IS_OMAP4430ES1;
b570e0ec SS	301	pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
	302	return;
	303	}
	304
	305	pr_err("Unknown OMAP4 CPU id\n");
	306	}
	307
8384ce07	308	#define OMAP3_SHOW_FEATURE(feat) \
cedf900d KH	309	if (omap3_has_ ##feat()) \
cedf900d KH	310	printk(#feat" ");
8384ce07	311
5ebc0d52	312	static void __init omap3_cpuinfo(void)
8384ce07	313	{
048f4bd7 SP	314	u8 rev = GET_OMAP_REVISION();
	315	char cpu_name[16], cpu_rev[16];
	316
	317	/* OMAP3430 and OMAP3530 are assumed to be same.
	318	*
	319	* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	320	* on available features. Upon detection, update the CPU id
	321	* and CPU class bits.
	322	*/
edeae658	323	if (cpu_is_omap3630()) {
4cac6018	324	strcpy(cpu_name, "OMAP3630");
edeae658	325	} else if (cpu_is_omap3505()) {
4cac6018 SP	326	/*
	327	* AM35xx devices
	328	*/
	329	if (omap3_has_sgx()) {
	330	omap_revision = OMAP3517_REV(rev);
	331	strcpy(cpu_name, "AM3517");
edeae658	332	} else {
4cac6018 SP	333	/* Already set in omap3_check_revision() */
	334	strcpy(cpu_name, "AM3505");
	335	}
edeae658 FB	336	} else if (omap3_has_iva() && omap3_has_sgx()) {
edeae658 FB	337	/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
4cac6018	338	strcpy(cpu_name, "OMAP3430/3530");
0712fb39	339	} else if (omap3_has_iva()) {
048f4bd7	340	omap_revision = OMAP3525_REV(rev);
4cac6018	341	strcpy(cpu_name, "OMAP3525");
0712fb39	342	} else if (omap3_has_sgx()) {
048f4bd7	343	omap_revision = OMAP3515_REV(rev);
4cac6018	344	strcpy(cpu_name, "OMAP3515");
edeae658	345	} else {
048f4bd7	346	omap_revision = OMAP3503_REV(rev);
4cac6018	347	strcpy(cpu_name, "OMAP3503");
048f4bd7 SP	348	}
	349
	350	switch (rev) {
	351	case OMAP_REVBITS_00:
	352	strcpy(cpu_rev, "1.0");
	353	break;
	354	case OMAP_REVBITS_10:
	355	strcpy(cpu_rev, "2.0");
	356	break;
	357	case OMAP_REVBITS_20:
	358	strcpy(cpu_rev, "2.1");
	359	break;
	360	case OMAP_REVBITS_30:
	361	strcpy(cpu_rev, "3.0");
	362	break;
	363	case OMAP_REVBITS_40:
edeae658	364	/* FALLTHROUGH */
048f4bd7 SP	365	default:
	366	/* Use the latest known revision as default */
	367	strcpy(cpu_rev, "3.1");
	368	}
	369
edeae658	370	/* Print verbose information */
cedf900d	371	pr_info("%s ES%s (", cpu_name, cpu_rev);
048f4bd7	372
8384ce07 SP	373	OMAP3_SHOW_FEATURE(l2cache);
	374	OMAP3_SHOW_FEATURE(iva);
	375	OMAP3_SHOW_FEATURE(sgx);
	376	OMAP3_SHOW_FEATURE(neon);
	377	OMAP3_SHOW_FEATURE(isp);
7356f0b2	378	OMAP3_SHOW_FEATURE(192mhz_clk);
cedf900d KH	379
cedf900d KH	380	printk(")\n");
8384ce07 SP	381	}
8384ce07 SP	382
a8823143 TL	383	/*
	384	* Try to detect the exact revision of the omap we're running on
	385	*/
5ba02dca TL	386	void __init omap2_check_revision(void)
5ba02dca TL	387	{
a8823143 TL	388	/*
	389	* At this point we have an idea about the processor revision set
	390	* earlier with omap2_set_globals_tap().
	391	*/
edeae658	392	if (cpu_is_omap24xx()) {
a8823143	393	omap24xx_check_revision();
edeae658	394	} else if (cpu_is_omap34xx()) {
8384ce07	395	omap3_check_revision();
05574bb2	396	omap3_check_features();
8384ce07	397	omap3_cpuinfo();
e9acb9b6	398	return;
edeae658	399	} else if (cpu_is_omap44xx()) {
b570e0ec	400	omap4_check_revision();
44169075	401	return;
edeae658	402	} else {
a8823143	403	pr_err("OMAP revision unknown, please fix!\n");
edeae658	404	}
a8823143 TL	405
	406	/*
	407	* OK, now we know the exact revision. Initialize omap_chip bits
	408	* for powerdowmain and clockdomain code.
	409	*/
	410	if (cpu_is_omap243x()) {
	411	/* Currently only supports 2430ES2.1 and 2430-all */
	412	omap_chip.oc \|= CHIP_IS_OMAP2430;
e9acb9b6	413	return;
a8823143 TL	414	} else if (cpu_is_omap242x()) {
	415	/* Currently only supports 2420ES2.1.1 and 2420-all */
	416	omap_chip.oc \|= CHIP_IS_OMAP2420;
e9acb9b6	417	return;
a8823143	418	}
e9acb9b6 TL	419
e9acb9b6 TL	420	pr_err("Uninitialized omap_chip, please fix!\n");
5ba02dca TL	421	}
5ba02dca TL	422
a8823143 TL	423	/*
	424	* Set up things for map_io and processor detection later on. Gets called
	425	* pretty much first thing from board init. For multi-omap, this gets
	426	* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
	427	* detect the exact revision later on in omap2_detect_revision() once map_io
	428	* is done.
	429	*/
0e564848 TL	430	void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
0e564848 TL	431	{
84a34344	432	omap_revision = omap2_globals->class;
0e564848 TL	433	tap_base = omap2_globals->tap;
0e564848 TL	434
a8823143	435	if (cpu_is_omap34xx())
0e564848 TL	436	tap_prod_id = 0x0210;
	437	else
	438	tap_prod_id = 0x0208;
	439	}