Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
1dbae815 | 21 | |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
1dbae815 | 23 | |
ce491cf8 | 24 | #include <plat/common.h> |
ce491cf8 | 25 | #include <plat/cpu.h> |
72d0f1c3 | 26 | |
2e130fc3 KRC |
27 | #include <mach/id.h> |
28 | ||
4814ced5 PW |
29 | #include "control.h" |
30 | ||
097c584c | 31 | static struct omap_chip_id omap_chip; |
84a34344 LL |
32 | static unsigned int omap_revision; |
33 | ||
cc0170b2 | 34 | u32 omap_features; |
84a34344 LL |
35 | |
36 | unsigned int omap_rev(void) | |
37 | { | |
38 | return omap_revision; | |
39 | } | |
40 | EXPORT_SYMBOL(omap_rev); | |
097c584c PW |
41 | |
42 | /** | |
43 | * omap_chip_is - test whether currently running OMAP matches a chip type | |
44 | * @oc: omap_chip_t to test against | |
45 | * | |
46 | * Test whether the currently-running OMAP chip matches the supplied | |
47 | * chip type 'oc'. Returns 1 upon a match; 0 upon failure. | |
48 | */ | |
49 | int omap_chip_is(struct omap_chip_id oci) | |
50 | { | |
51 | return (oci.oc & omap_chip.oc) ? 1 : 0; | |
52 | } | |
53 | EXPORT_SYMBOL(omap_chip_is); | |
54 | ||
8e25ad96 KH |
55 | int omap_type(void) |
56 | { | |
57 | u32 val = 0; | |
58 | ||
edeae658 | 59 | if (cpu_is_omap24xx()) { |
8e25ad96 | 60 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
edeae658 | 61 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 62 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 63 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 64 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
edeae658 | 65 | } else { |
8e25ad96 KH |
66 | pr_err("Cannot detect omap type!\n"); |
67 | goto out; | |
68 | } | |
69 | ||
70 | val &= OMAP2_DEVICETYPE_MASK; | |
71 | val >>= 8; | |
72 | ||
73 | out: | |
74 | return val; | |
75 | } | |
76 | EXPORT_SYMBOL(omap_type); | |
77 | ||
78 | ||
a8823143 | 79 | /*----------------------------------------------------------------------------*/ |
097c584c | 80 | |
a8823143 TL |
81 | #define OMAP_TAP_IDCODE 0x0204 |
82 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
83 | #define OMAP_TAP_DIE_ID_1 0x021C | |
84 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
85 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 86 | |
b235e007 AG |
87 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
88 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
89 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
90 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
91 | ||
a8823143 | 92 | #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) |
097c584c | 93 | |
a8823143 TL |
94 | struct omap_id { |
95 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
96 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 97 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 98 | }; |
097c584c | 99 | |
a8823143 TL |
100 | /* Register values to detect the OMAP version */ |
101 | static struct omap_id omap_ids[] __initdata = { | |
102 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
103 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
104 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
105 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
106 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
107 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
108 | }; | |
097c584c | 109 | |
a8823143 TL |
110 | static void __iomem *tap_base; |
111 | static u16 tap_prod_id; | |
1dbae815 | 112 | |
2e130fc3 KRC |
113 | void omap_get_die_id(struct omap_die_id *odi) |
114 | { | |
b235e007 AG |
115 | if (cpu_is_omap44xx()) { |
116 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); | |
117 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
118 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
119 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
120 | ||
121 | return; | |
122 | } | |
2e130fc3 KRC |
123 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
124 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
125 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
126 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
127 | } | |
128 | ||
5ebc0d52 | 129 | static void __init omap24xx_check_revision(void) |
1dbae815 TL |
130 | { |
131 | int i, j; | |
a8823143 | 132 | u32 idcode, prod_id; |
1dbae815 | 133 | u16 hawkeye; |
a8823143 | 134 | u8 dev_type, rev; |
c46732bb | 135 | struct omap_die_id odi; |
1dbae815 TL |
136 | |
137 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 138 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
139 | hawkeye = (idcode >> 12) & 0xffff; |
140 | rev = (idcode >> 28) & 0x0f; | |
141 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 142 | omap_get_die_id(&odi); |
1dbae815 | 143 | |
097c584c PW |
144 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
145 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 146 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 147 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
148 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
149 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
150 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
151 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
152 | prod_id, dev_type); | |
153 | ||
1dbae815 TL |
154 | /* Check hawkeye ids */ |
155 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
156 | if (hawkeye == omap_ids[i].hawkeye) | |
157 | break; | |
158 | } | |
159 | ||
160 | if (i == ARRAY_SIZE(omap_ids)) { | |
161 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
162 | return; | |
163 | } | |
164 | ||
165 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
166 | if (dev_type == omap_ids[j].dev) | |
167 | break; | |
168 | } | |
169 | ||
170 | if (j == ARRAY_SIZE(omap_ids)) { | |
171 | printk(KERN_ERR "Unknown OMAP device type. " | |
172 | "Handling it as OMAP%04x\n", | |
173 | omap_ids[i].type >> 16); | |
174 | j = i; | |
175 | } | |
1dbae815 | 176 | |
84a34344 LL |
177 | pr_info("OMAP%04x", omap_rev() >> 16); |
178 | if ((omap_rev() >> 8) & 0x0f) | |
179 | pr_info("ES%x", (omap_rev() >> 12) & 0xf); | |
097c584c | 180 | pr_info("\n"); |
a8823143 TL |
181 | } |
182 | ||
8384ce07 SP |
183 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
184 | if (((status & OMAP3_ ##feat## _MASK) \ | |
185 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 186 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
187 | } |
188 | ||
5ebc0d52 | 189 | static void __init omap3_check_features(void) |
8384ce07 SP |
190 | { |
191 | u32 status; | |
192 | ||
cc0170b2 | 193 | omap_features = 0; |
8384ce07 SP |
194 | |
195 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
196 | ||
197 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
198 | OMAP3_CHECK_FEATURE(status, IVA); | |
199 | OMAP3_CHECK_FEATURE(status, SGX); | |
200 | OMAP3_CHECK_FEATURE(status, NEON); | |
201 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 | 202 | if (cpu_is_omap3630()) |
cc0170b2 | 203 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
ad0c63f1 | 204 | if (!cpu_is_omap3505() && !cpu_is_omap3517()) |
cc0170b2 | 205 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
8384ce07 | 206 | |
cc0170b2 | 207 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 208 | |
8384ce07 SP |
209 | /* |
210 | * TODO: Get additional info (where applicable) | |
211 | * e.g. Size of L2 cache. | |
212 | */ | |
213 | } | |
214 | ||
cc0170b2 A |
215 | static void __init omap4_check_features(void) |
216 | { | |
217 | u32 si_type; | |
218 | ||
219 | if (cpu_is_omap443x()) | |
220 | omap_features |= OMAP4_HAS_MPU_1GHZ; | |
221 | ||
222 | ||
223 | if (cpu_is_omap446x()) { | |
224 | si_type = | |
225 | read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1); | |
226 | switch ((si_type & (3 << 16)) >> 16) { | |
227 | case 2: | |
228 | /* High performance device */ | |
229 | omap_features |= OMAP4_HAS_MPU_1_5GHZ; | |
230 | break; | |
231 | case 1: | |
232 | default: | |
233 | /* Standard device */ | |
234 | omap_features |= OMAP4_HAS_MPU_1_2GHZ; | |
235 | break; | |
236 | } | |
237 | } | |
238 | } | |
239 | ||
01001712 HP |
240 | static void __init ti816x_check_features(void) |
241 | { | |
cc0170b2 | 242 | omap_features = OMAP3_HAS_NEON; |
01001712 HP |
243 | } |
244 | ||
5ebc0d52 | 245 | static void __init omap3_check_revision(void) |
a8823143 TL |
246 | { |
247 | u32 cpuid, idcode; | |
248 | u16 hawkeye; | |
249 | u8 rev; | |
a8823143 | 250 | |
e9acb9b6 TL |
251 | omap_chip.oc = CHIP_IS_OMAP3430; |
252 | ||
a8823143 TL |
253 | /* |
254 | * We cannot access revision registers on ES1.0. | |
255 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
256 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
257 | */ | |
258 | cpuid = read_cpuid(CPUID_ID); | |
259 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { | |
84a34344 | 260 | omap_revision = OMAP3430_REV_ES1_0; |
e9acb9b6 | 261 | omap_chip.oc |= CHIP_IS_OMAP3430ES1; |
048f4bd7 | 262 | return; |
a8823143 TL |
263 | } |
264 | ||
265 | /* | |
266 | * Detection for 34xx ES2.0 and above can be done with just | |
267 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
268 | * Note that rev does not map directly to our defined processor | |
269 | * revision numbers as ES1.0 uses value 0. | |
270 | */ | |
271 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
272 | hawkeye = (idcode >> 12) & 0xffff; | |
273 | rev = (idcode >> 28) & 0xff; | |
097c584c | 274 | |
2456a10f NM |
275 | switch (hawkeye) { |
276 | case 0xb7ae: | |
277 | /* Handle 34xx/35xx devices */ | |
a8823143 | 278 | switch (rev) { |
048f4bd7 SP |
279 | case 0: /* Take care of early samples */ |
280 | case 1: | |
84a34344 | 281 | omap_revision = OMAP3430_REV_ES2_0; |
e9acb9b6 | 282 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; |
a8823143 TL |
283 | break; |
284 | case 2: | |
84a34344 | 285 | omap_revision = OMAP3430_REV_ES2_1; |
e9acb9b6 | 286 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; |
a8823143 TL |
287 | break; |
288 | case 3: | |
84a34344 | 289 | omap_revision = OMAP3430_REV_ES3_0; |
e9acb9b6 | 290 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; |
a8823143 | 291 | break; |
187e688d | 292 | case 4: |
e9acb9b6 TL |
293 | omap_revision = OMAP3430_REV_ES3_1; |
294 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; | |
295 | break; | |
296 | case 7: | |
edeae658 | 297 | /* FALLTHROUGH */ |
a8823143 TL |
298 | default: |
299 | /* Use the latest known revision as default */ | |
e9acb9b6 TL |
300 | omap_revision = OMAP3430_REV_ES3_1_2; |
301 | ||
302 | /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */ | |
303 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; | |
a8823143 | 304 | } |
2456a10f | 305 | break; |
4cac6018 | 306 | case 0xb868: |
1f1b0353 PW |
307 | /* |
308 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 309 | * |
1f1b0353 | 310 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 | 311 | * is identified later based on the features. |
e9acb9b6 TL |
312 | * |
313 | * REVISIT: AM3505/AM3517 should have their own CHIP_IS | |
4cac6018 | 314 | */ |
9ed2ba7a PW |
315 | switch (rev) { |
316 | case 0: | |
317 | omap_revision = OMAP3517_REV_ES1_0; | |
318 | break; | |
319 | case 1: | |
320 | /* FALLTHROUGH */ | |
321 | default: | |
322 | omap_revision = OMAP3517_REV_ES1_1; | |
323 | } | |
e9acb9b6 | 324 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; |
4cac6018 | 325 | break; |
edeae658 | 326 | case 0xb891: |
b0a1a6ce AG |
327 | /* Handle 36xx devices */ |
328 | omap_chip.oc |= CHIP_IS_OMAP3630ES1; | |
329 | ||
330 | switch(rev) { | |
331 | case 0: /* Take care of early samples */ | |
332 | omap_revision = OMAP3630_REV_ES1_0; | |
333 | break; | |
334 | case 1: | |
335 | omap_revision = OMAP3630_REV_ES1_1; | |
336 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; | |
337 | break; | |
338 | case 2: | |
51ec811a | 339 | /* FALLTHROUGH */ |
b0a1a6ce | 340 | default: |
51ec811a | 341 | omap_revision = OMAP3630_REV_ES1_2; |
b0a1a6ce | 342 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; |
b0a1a6ce | 343 | } |
77c0870c | 344 | break; |
01001712 HP |
345 | case 0xb81e: |
346 | omap_chip.oc = CHIP_IS_TI816X; | |
347 | ||
348 | switch (rev) { | |
349 | case 0: | |
350 | omap_revision = TI8168_REV_ES1_0; | |
351 | break; | |
352 | case 1: | |
51ec811a | 353 | /* FALLTHROUGH */ |
01001712 | 354 | default: |
51ec811a | 355 | omap_revision = TI8168_REV_ES1_1; |
01001712 HP |
356 | } |
357 | break; | |
2456a10f | 358 | default: |
51ec811a | 359 | /* Unknown default to latest silicon rev as default */ |
b0a1a6ce AG |
360 | omap_revision = OMAP3630_REV_ES1_2; |
361 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; | |
51ec811a | 362 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
a8823143 | 363 | } |
1dbae815 TL |
364 | } |
365 | ||
5ebc0d52 | 366 | static void __init omap4_check_revision(void) |
b570e0ec SS |
367 | { |
368 | u32 idcode; | |
369 | u16 hawkeye; | |
370 | u8 rev; | |
b570e0ec SS |
371 | |
372 | /* | |
373 | * The IC rev detection is done with hawkeye and rev. | |
374 | * Note that rev does not map directly to defined processor | |
375 | * revision numbers as ES1.0 uses value 0. | |
376 | */ | |
377 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
378 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 379 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 380 | |
ed6be0ba | 381 | /* |
fa54dccd | 382 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
383 | * Use ARM register to detect the correct ES version |
384 | */ | |
fa54dccd | 385 | if (!rev && (hawkeye != 0xb94e)) { |
ed6be0ba SS |
386 | idcode = read_cpuid(CPUID_ID); |
387 | rev = (idcode & 0xf) - 1; | |
388 | } | |
389 | ||
390 | switch (hawkeye) { | |
391 | case 0xb852: | |
392 | switch (rev) { | |
393 | case 0: | |
394 | omap_revision = OMAP4430_REV_ES1_0; | |
395 | omap_chip.oc |= CHIP_IS_OMAP4430ES1; | |
396 | break; | |
397 | case 1: | |
e49c4d27 | 398 | default: |
ed6be0ba SS |
399 | omap_revision = OMAP4430_REV_ES2_0; |
400 | omap_chip.oc |= CHIP_IS_OMAP4430ES2; | |
e49c4d27 NK |
401 | } |
402 | break; | |
403 | case 0xb95c: | |
404 | switch (rev) { | |
405 | case 3: | |
406 | omap_revision = OMAP4430_REV_ES2_1; | |
407 | omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; | |
ed6be0ba | 408 | break; |
e49c4d27 | 409 | case 4: |
ed6be0ba | 410 | default: |
e49c4d27 NK |
411 | omap_revision = OMAP4430_REV_ES2_2; |
412 | omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; | |
413 | } | |
414 | break; | |
fa54dccd A |
415 | case 0xb94e: |
416 | switch (rev) { | |
417 | case 0: | |
418 | default: | |
419 | omap_revision = OMAP4460_REV_ES1_0; | |
420 | omap_chip.oc |= CHIP_IS_OMAP4460ES1_0; | |
421 | break; | |
422 | } | |
423 | break; | |
ed6be0ba | 424 | default: |
e49c4d27 NK |
425 | /* Unknown default to latest silicon rev as default */ |
426 | omap_revision = OMAP4430_REV_ES2_2; | |
427 | omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; | |
b570e0ec SS |
428 | } |
429 | ||
e49c4d27 NK |
430 | pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, |
431 | ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); | |
b570e0ec SS |
432 | } |
433 | ||
8384ce07 | 434 | #define OMAP3_SHOW_FEATURE(feat) \ |
cedf900d KH |
435 | if (omap3_has_ ##feat()) \ |
436 | printk(#feat" "); | |
8384ce07 | 437 | |
5ebc0d52 | 438 | static void __init omap3_cpuinfo(void) |
8384ce07 | 439 | { |
048f4bd7 | 440 | u8 rev = GET_OMAP_REVISION(); |
91d92d6c | 441 | const char *cpu_name, *cpu_rev; |
048f4bd7 | 442 | |
91d92d6c PW |
443 | /* |
444 | * OMAP3430 and OMAP3530 are assumed to be same. | |
048f4bd7 SP |
445 | * |
446 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
447 | * on available features. Upon detection, update the CPU id | |
448 | * and CPU class bits. | |
449 | */ | |
edeae658 | 450 | if (cpu_is_omap3630()) { |
91d92d6c | 451 | cpu_name = "OMAP3630"; |
1f1b0353 | 452 | } else if (cpu_is_omap3517()) { |
91d92d6c PW |
453 | /* AM35xx devices */ |
454 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; | |
01001712 | 455 | } else if (cpu_is_ti816x()) { |
91d92d6c | 456 | cpu_name = "TI816X"; |
edeae658 FB |
457 | } else if (omap3_has_iva() && omap3_has_sgx()) { |
458 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
91d92d6c | 459 | cpu_name = "OMAP3430/3530"; |
0712fb39 | 460 | } else if (omap3_has_iva()) { |
91d92d6c | 461 | cpu_name = "OMAP3525"; |
0712fb39 | 462 | } else if (omap3_has_sgx()) { |
91d92d6c | 463 | cpu_name = "OMAP3515"; |
edeae658 | 464 | } else { |
91d92d6c | 465 | cpu_name = "OMAP3503"; |
048f4bd7 SP |
466 | } |
467 | ||
01001712 | 468 | if (cpu_is_omap3630() || cpu_is_ti816x()) { |
76abab21 SP |
469 | switch (rev) { |
470 | case OMAP_REVBITS_00: | |
91d92d6c | 471 | cpu_rev = "1.0"; |
76abab21 SP |
472 | break; |
473 | case OMAP_REVBITS_01: | |
91d92d6c | 474 | cpu_rev = "1.1"; |
76abab21 SP |
475 | break; |
476 | case OMAP_REVBITS_02: | |
477 | /* FALLTHROUGH */ | |
478 | default: | |
479 | /* Use the latest known revision as default */ | |
91d92d6c | 480 | cpu_rev = "1.2"; |
76abab21 SP |
481 | } |
482 | } else if (cpu_is_omap3505() || cpu_is_omap3517()) { | |
483 | switch (rev) { | |
484 | case OMAP_REVBITS_00: | |
91d92d6c | 485 | cpu_rev = "1.0"; |
76abab21 SP |
486 | break; |
487 | case OMAP_REVBITS_01: | |
488 | /* FALLTHROUGH */ | |
489 | default: | |
490 | /* Use the latest known revision as default */ | |
91d92d6c | 491 | cpu_rev = "1.1"; |
76abab21 SP |
492 | } |
493 | } else { | |
494 | switch (rev) { | |
495 | case OMAP_REVBITS_00: | |
91d92d6c | 496 | cpu_rev = "1.0"; |
76abab21 SP |
497 | break; |
498 | case OMAP_REVBITS_01: | |
91d92d6c | 499 | cpu_rev = "2.0"; |
76abab21 SP |
500 | break; |
501 | case OMAP_REVBITS_02: | |
91d92d6c | 502 | cpu_rev = "2.1"; |
76abab21 SP |
503 | break; |
504 | case OMAP_REVBITS_03: | |
91d92d6c | 505 | cpu_rev = "3.0"; |
76abab21 SP |
506 | break; |
507 | case OMAP_REVBITS_04: | |
91d92d6c | 508 | cpu_rev = "3.1"; |
76abab21 SP |
509 | break; |
510 | case OMAP_REVBITS_05: | |
511 | /* FALLTHROUGH */ | |
512 | default: | |
513 | /* Use the latest known revision as default */ | |
91d92d6c | 514 | cpu_rev = "3.1.2"; |
76abab21 | 515 | } |
048f4bd7 SP |
516 | } |
517 | ||
edeae658 | 518 | /* Print verbose information */ |
cedf900d | 519 | pr_info("%s ES%s (", cpu_name, cpu_rev); |
048f4bd7 | 520 | |
8384ce07 SP |
521 | OMAP3_SHOW_FEATURE(l2cache); |
522 | OMAP3_SHOW_FEATURE(iva); | |
523 | OMAP3_SHOW_FEATURE(sgx); | |
524 | OMAP3_SHOW_FEATURE(neon); | |
525 | OMAP3_SHOW_FEATURE(isp); | |
7356f0b2 | 526 | OMAP3_SHOW_FEATURE(192mhz_clk); |
cedf900d KH |
527 | |
528 | printk(")\n"); | |
8384ce07 SP |
529 | } |
530 | ||
a8823143 TL |
531 | /* |
532 | * Try to detect the exact revision of the omap we're running on | |
533 | */ | |
5ba02dca TL |
534 | void __init omap2_check_revision(void) |
535 | { | |
a8823143 TL |
536 | /* |
537 | * At this point we have an idea about the processor revision set | |
538 | * earlier with omap2_set_globals_tap(). | |
539 | */ | |
edeae658 | 540 | if (cpu_is_omap24xx()) { |
a8823143 | 541 | omap24xx_check_revision(); |
edeae658 | 542 | } else if (cpu_is_omap34xx()) { |
8384ce07 | 543 | omap3_check_revision(); |
01001712 HP |
544 | |
545 | /* TI816X doesn't have feature register */ | |
546 | if (!cpu_is_ti816x()) | |
547 | omap3_check_features(); | |
548 | else | |
549 | ti816x_check_features(); | |
550 | ||
8384ce07 | 551 | omap3_cpuinfo(); |
e9acb9b6 | 552 | return; |
edeae658 | 553 | } else if (cpu_is_omap44xx()) { |
b570e0ec | 554 | omap4_check_revision(); |
cc0170b2 | 555 | omap4_check_features(); |
44169075 | 556 | return; |
edeae658 | 557 | } else { |
a8823143 | 558 | pr_err("OMAP revision unknown, please fix!\n"); |
edeae658 | 559 | } |
a8823143 TL |
560 | |
561 | /* | |
562 | * OK, now we know the exact revision. Initialize omap_chip bits | |
563 | * for powerdowmain and clockdomain code. | |
564 | */ | |
565 | if (cpu_is_omap243x()) { | |
566 | /* Currently only supports 2430ES2.1 and 2430-all */ | |
567 | omap_chip.oc |= CHIP_IS_OMAP2430; | |
e9acb9b6 | 568 | return; |
a8823143 TL |
569 | } else if (cpu_is_omap242x()) { |
570 | /* Currently only supports 2420ES2.1.1 and 2420-all */ | |
571 | omap_chip.oc |= CHIP_IS_OMAP2420; | |
e9acb9b6 | 572 | return; |
a8823143 | 573 | } |
e9acb9b6 TL |
574 | |
575 | pr_err("Uninitialized omap_chip, please fix!\n"); | |
5ba02dca TL |
576 | } |
577 | ||
a8823143 TL |
578 | /* |
579 | * Set up things for map_io and processor detection later on. Gets called | |
580 | * pretty much first thing from board init. For multi-omap, this gets | |
581 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
582 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
583 | * is done. | |
584 | */ | |
0e564848 TL |
585 | void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) |
586 | { | |
84a34344 | 587 | omap_revision = omap2_globals->class; |
0e564848 TL |
588 | tap_base = omap2_globals->tap; |
589 | ||
a8823143 | 590 | if (cpu_is_omap34xx()) |
0e564848 TL |
591 | tap_prod_id = 0x0210; |
592 | else | |
593 | tap_prod_id = 0x0208; | |
594 | } |