[deliverable/linux.git] / arch / arm / mach-omap2 / id.c

/*
 * linux/arch/arm/mach-omap2/id.c
 *
 * OMAP2 CPU identification code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/cputype.h>

#include <plat/common.h>
#include <plat/cpu.h>

#include <mach/id.h>

#include "control.h"

static struct omap_chip_id omap_chip;
static unsigned int omap_revision;

u32 omap3_features;

unsigned int omap_rev(void)
{
	return omap_revision;
}
EXPORT_SYMBOL(omap_rev);

/**
 * omap_chip_is - test whether currently running OMAP matches a chip type
 * @oc: omap_chip_t to test against
 *
 * Test whether the currently-running OMAP chip matches the supplied
 * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
 */
int omap_chip_is(struct omap_chip_id oci)
{
	return (oci.oc & omap_chip.oc) ? 1 : 0;
}
EXPORT_SYMBOL(omap_chip_is);

int omap_type(void)
{
	u32 val = 0;

	if (cpu_is_omap24xx()) {
		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
	} else if (cpu_is_omap34xx()) {
		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
	} else if (cpu_is_omap44xx()) {
		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
	} else {
		pr_err("Cannot detect omap type!\n");
		goto out;
	}

	val &= OMAP2_DEVICETYPE_MASK;
	val >>= 8;

out:
	return val;
}
EXPORT_SYMBOL(omap_type);


/*----------------------------------------------------------------------------*/

#define OMAP_TAP_IDCODE		0x0204
#define OMAP_TAP_DIE_ID_0	0x0218
#define OMAP_TAP_DIE_ID_1	0x021C
#define OMAP_TAP_DIE_ID_2	0x0220
#define OMAP_TAP_DIE_ID_3	0x0224

#define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))

struct omap_id {
	u16	hawkeye;	/* Silicon type (Hawkeye id) */
	u8	dev;		/* Device type from production_id reg */
	u32	type;		/* Combined type id copied to omap_revision */
};

/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
};

static void __iomem *tap_base;
static u16 tap_prod_id;

void omap_get_die_id(struct omap_die_id *odi)
{
	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
}

static void __init omap24xx_check_revision(void)
{
	int i, j;
	u32 idcode, prod_id;
	u16 hawkeye;
	u8  dev_type, rev;
	struct omap_die_id odi;

	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	prod_id = read_tap_reg(tap_prod_id);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0x0f;
	dev_type = (prod_id >> 16) & 0x0f;
	omap_get_die_id(&odi);

	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
		 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
		 odi.id_1, (odi.id_1 >> 28) & 0xf);
	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
		 prod_id, dev_type);

	/* Check hawkeye ids */
	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
		if (hawkeye == omap_ids[i].hawkeye)
			break;
	}

	if (i == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP CPU id\n");
		return;
	}

	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
		if (dev_type == omap_ids[j].dev)
			break;
	}

	if (j == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP device type. "
				"Handling it as OMAP%04x\n",
				omap_ids[i].type >> 16);
		j = i;
	}

	pr_info("OMAP%04x", omap_rev() >> 16);
	if ((omap_rev() >> 8) & 0x0f)
		pr_info("ES%x", (omap_rev() >> 12) & 0xf);
	pr_info("\n");
}

#define OMAP3_CHECK_FEATURE(status,feat)				\
	if (((status & OMAP3_ ##feat## _MASK) 				\
		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
		omap3_features |= OMAP3_HAS_ ##feat;			\
	}

static void __init omap3_check_features(void)
{
	u32 status;

	omap3_features = 0;

	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);

	OMAP3_CHECK_FEATURE(status, L2CACHE);
	OMAP3_CHECK_FEATURE(status, IVA);
	OMAP3_CHECK_FEATURE(status, SGX);
	OMAP3_CHECK_FEATURE(status, NEON);
	OMAP3_CHECK_FEATURE(status, ISP);
	if (cpu_is_omap3630())
		omap3_features |= OMAP3_HAS_192MHZ_CLK;
	if (!cpu_is_omap3505() && !cpu_is_omap3517())
		omap3_features |= OMAP3_HAS_IO_WAKEUP;

	omap3_features |= OMAP3_HAS_SDRC;

	/*
	 * TODO: Get additional info (where applicable)
	 *       e.g. Size of L2 cache.
	 */
}

static void __init ti816x_check_features(void)
{
	omap3_features = OMAP3_HAS_NEON;
}

static void __init omap3_check_revision(void)
{
	u32 cpuid, idcode;
	u16 hawkeye;
	u8 rev;

	omap_chip.oc = CHIP_IS_OMAP3430;

	/*
	 * We cannot access revision registers on ES1.0.
	 * If the processor type is Cortex-A8 and the revision is 0x0
	 * it means its Cortex r0p0 which is 3430 ES1.0.
	 */
	cpuid = read_cpuid(CPUID_ID);
	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
		omap_revision = OMAP3430_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP3430ES1;
		return;
	}

	/*
	 * Detection for 34xx ES2.0 and above can be done with just
	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
	 * Note that rev does not map directly to our defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	switch (hawkeye) {
	case 0xb7ae:
		/* Handle 34xx/35xx devices */
		switch (rev) {
		case 0: /* Take care of early samples */
		case 1:
			omap_revision = OMAP3430_REV_ES2_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 2:
			omap_revision = OMAP3430_REV_ES2_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 3:
			omap_revision = OMAP3430_REV_ES3_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
			break;
		case 4:
			omap_revision = OMAP3430_REV_ES3_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
			break;
		case 7:
		/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			omap_revision = OMAP3430_REV_ES3_1_2;

			/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		}
		break;
	case 0xb868:
		/* Handle OMAP35xx/AM35xx devices
		 *
		 * Set the device to be OMAP3505 here. Actual device
		 * is identified later based on the features.
		 *
		 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
		 */
		omap_revision = OMAP3505_REV(rev);
		omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		break;
	case 0xb891:
		/* Handle 36xx devices */
		omap_chip.oc |= CHIP_IS_OMAP3630ES1;

		switch(rev) {
		case 0: /* Take care of early samples */
			omap_revision = OMAP3630_REV_ES1_0;
			break;
		case 1:
			omap_revision = OMAP3630_REV_ES1_1;
			omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
			break;
		case 2:
		default:
			omap_revision =  OMAP3630_REV_ES1_2;
			omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
		}
		break;
	case 0xb81e:
		omap_chip.oc = CHIP_IS_TI816X;

		switch (rev) {
		case 0:
			omap_revision = TI8168_REV_ES1_0;
			break;
		case 1:
			omap_revision = TI8168_REV_ES1_1;
			break;
		default:
			omap_revision =  TI8168_REV_ES1_1;
		}
		break;
	default:
		/* Unknown default to latest silicon rev as default*/
		omap_revision =  OMAP3630_REV_ES1_2;
		omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
	}
}

static void __init omap4_check_revision(void)
{
	u32 idcode;
	u16 hawkeye;
	u8 rev;

	/*
	 * The IC rev detection is done with hawkeye and rev.
	 * Note that rev does not map directly to defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	/*
	 * Few initial ES2.0 samples IDCODE is same as ES1.0
	 * Use ARM register to detect the correct ES version
	 */
	if (!rev) {
		idcode = read_cpuid(CPUID_ID);
		rev = (idcode & 0xf) - 1;
	}

	switch (hawkeye) {
	case 0xb852:
		switch (rev) {
		case 0:
			omap_revision = OMAP4430_REV_ES1_0;
			omap_chip.oc |= CHIP_IS_OMAP4430ES1;
			break;
		case 1:
			omap_revision = OMAP4430_REV_ES2_0;
			omap_chip.oc |= CHIP_IS_OMAP4430ES2;
			break;
		default:
			omap_revision = OMAP4430_REV_ES2_0;
			omap_chip.oc |= CHIP_IS_OMAP4430ES2;
	}
	break;
	default:
		/* Unknown default to latest silicon rev as default*/
		omap_revision = OMAP4430_REV_ES2_0;
		omap_chip.oc |= CHIP_IS_OMAP4430ES2;
	}

	pr_info("OMAP%04x ES%d.0\n",
			omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
}

#define OMAP3_SHOW_FEATURE(feat)		\
	if (omap3_has_ ##feat())		\
		printk(#feat" ");

static void __init omap3_cpuinfo(void)
{
	u8 rev = GET_OMAP_REVISION();
	char cpu_name[16], cpu_rev[16];

	/* OMAP3430 and OMAP3530 are assumed to be same.
	 *
	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	 * on available features. Upon detection, update the CPU id
	 * and CPU class bits.
	 */
	if (cpu_is_omap3630()) {
		strcpy(cpu_name, "OMAP3630");
	} else if (cpu_is_omap3505()) {
		/*
		 * AM35xx devices
		 */
		if (omap3_has_sgx()) {
			omap_revision = OMAP3517_REV(rev);
			strcpy(cpu_name, "AM3517");
		} else {
			/* Already set in omap3_check_revision() */
			strcpy(cpu_name, "AM3505");
		}
	} else if (cpu_is_ti816x()) {
		strcpy(cpu_name, "TI816X");
	} else if (omap3_has_iva() && omap3_has_sgx()) {
		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
		strcpy(cpu_name, "OMAP3430/3530");
	} else if (omap3_has_iva()) {
		omap_revision = OMAP3525_REV(rev);
		strcpy(cpu_name, "OMAP3525");
	} else if (omap3_has_sgx()) {
		omap_revision = OMAP3515_REV(rev);
		strcpy(cpu_name, "OMAP3515");
	} else {
		omap_revision = OMAP3503_REV(rev);
		strcpy(cpu_name, "OMAP3503");
	}

	if (cpu_is_omap3630() || cpu_is_ti816x()) {
		switch (rev) {
		case OMAP_REVBITS_00:
			strcpy(cpu_rev, "1.0");
			break;
		case OMAP_REVBITS_01:
			strcpy(cpu_rev, "1.1");
			break;
		case OMAP_REVBITS_02:
			/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			strcpy(cpu_rev, "1.2");
		}
	} else if (cpu_is_omap3505() || cpu_is_omap3517()) {
		switch (rev) {
		case OMAP_REVBITS_00:
			strcpy(cpu_rev, "1.0");
			break;
		case OMAP_REVBITS_01:
			/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			strcpy(cpu_rev, "1.1");
		}
	} else {
		switch (rev) {
		case OMAP_REVBITS_00:
			strcpy(cpu_rev, "1.0");
			break;
		case OMAP_REVBITS_01:
			strcpy(cpu_rev, "2.0");
			break;
		case OMAP_REVBITS_02:
			strcpy(cpu_rev, "2.1");
			break;
		case OMAP_REVBITS_03:
			strcpy(cpu_rev, "3.0");
			break;
		case OMAP_REVBITS_04:
			strcpy(cpu_rev, "3.1");
			break;
		case OMAP_REVBITS_05:
			/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			strcpy(cpu_rev, "3.1.2");
		}
	}

	/* Print verbose information */
	pr_info("%s ES%s (", cpu_name, cpu_rev);

	OMAP3_SHOW_FEATURE(l2cache);
	OMAP3_SHOW_FEATURE(iva);
	OMAP3_SHOW_FEATURE(sgx);
	OMAP3_SHOW_FEATURE(neon);
	OMAP3_SHOW_FEATURE(isp);
	OMAP3_SHOW_FEATURE(192mhz_clk);

	printk(")\n");
}

/*
 * Try to detect the exact revision of the omap we're running on
 */
void __init omap2_check_revision(void)
{
	/*
	 * At this point we have an idea about the processor revision set
	 * earlier with omap2_set_globals_tap().
	 */
	if (cpu_is_omap24xx()) {
		omap24xx_check_revision();
	} else if (cpu_is_omap34xx()) {
		omap3_check_revision();

		/* TI816X doesn't have feature register */
		if (!cpu_is_ti816x())
			omap3_check_features();
		else
			ti816x_check_features();

		omap3_cpuinfo();
		return;
	} else if (cpu_is_omap44xx()) {
		omap4_check_revision();
		return;
	} else {
		pr_err("OMAP revision unknown, please fix!\n");
	}

	/*
	 * OK, now we know the exact revision. Initialize omap_chip bits
	 * for powerdowmain and clockdomain code.
	 */
	if (cpu_is_omap243x()) {
		/* Currently only supports 2430ES2.1 and 2430-all */
		omap_chip.oc |= CHIP_IS_OMAP2430;
		return;
	} else if (cpu_is_omap242x()) {
		/* Currently only supports 2420ES2.1.1 and 2420-all */
		omap_chip.oc |= CHIP_IS_OMAP2420;
		return;
	}

	pr_err("Uninitialized omap_chip, please fix!\n");
}

/*
 * Set up things for map_io and processor detection later on. Gets called
 * pretty much first thing from board init. For multi-omap, this gets
 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 * detect the exact revision later on in omap2_detect_revision() once map_io
 * is done.
 */
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
{
	omap_revision = omap2_globals->class;
	tap_base = omap2_globals->tap;

	if (cpu_is_omap34xx())
		tap_prod_id = 0x0210;
	else
		tap_prod_id = 0x0208;
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/id.c
	3	*
	4	* OMAP2 CPU identification code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
44169075 SS	9	* Copyright (C) 2009 Texas Instruments
	10	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	11	*
1dbae815 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
1dbae815 TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
fced80c7	20	#include <linux/io.h>
1dbae815	21
0ba8b9b2	22	#include <asm/cputype.h>
1dbae815	23
ce491cf8	24	#include <plat/common.h>
ce491cf8	25	#include <plat/cpu.h>
72d0f1c3	26
2e130fc3 KRC	27	#include <mach/id.h>
2e130fc3 KRC	28
4814ced5 PW	29	#include "control.h"
4814ced5 PW	30
097c584c	31	static struct omap_chip_id omap_chip;
84a34344 LL	32	static unsigned int omap_revision;
84a34344 LL	33
8384ce07	34	u32 omap3_features;
84a34344 LL	35
	36	unsigned int omap_rev(void)
	37	{
	38	return omap_revision;
	39	}
	40	EXPORT_SYMBOL(omap_rev);
097c584c PW	41
	42	/**
	43	* omap_chip_is - test whether currently running OMAP matches a chip type
	44	* @oc: omap_chip_t to test against
	45	*
	46	* Test whether the currently-running OMAP chip matches the supplied
	47	* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
	48	*/
	49	int omap_chip_is(struct omap_chip_id oci)
	50	{
	51	return (oci.oc & omap_chip.oc) ? 1 : 0;
	52	}
	53	EXPORT_SYMBOL(omap_chip_is);
	54
8e25ad96 KH	55	int omap_type(void)
	56	{
	57	u32 val = 0;
	58
edeae658	59	if (cpu_is_omap24xx()) {
8e25ad96	60	val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
edeae658	61	} else if (cpu_is_omap34xx()) {
8e25ad96	62	val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
737daa03	63	} else if (cpu_is_omap44xx()) {
dcf5ef3f	64	val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
edeae658	65	} else {
8e25ad96 KH	66	pr_err("Cannot detect omap type!\n");
	67	goto out;
	68	}
	69
	70	val &= OMAP2_DEVICETYPE_MASK;
	71	val >>= 8;
	72
	73	out:
	74	return val;
	75	}
	76	EXPORT_SYMBOL(omap_type);
	77
	78
a8823143	79	/----------------------------------------------------------------------------/
097c584c	80
a8823143 TL	81	#define OMAP_TAP_IDCODE 0x0204
	82	#define OMAP_TAP_DIE_ID_0 0x0218
	83	#define OMAP_TAP_DIE_ID_1 0x021C
	84	#define OMAP_TAP_DIE_ID_2 0x0220
	85	#define OMAP_TAP_DIE_ID_3 0x0224
097c584c	86
a8823143	87	#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
097c584c	88
a8823143 TL	89	struct omap_id {
	90	u16 hawkeye; /* Silicon type (Hawkeye id) */
	91	u8 dev; /* Device type from production_id reg */
84a34344	92	u32 type; /* Combined type id copied to omap_revision */
a8823143	93	};
097c584c	94
a8823143 TL	95	/* Register values to detect the OMAP version */
	96	static struct omap_id omap_ids[] __initdata = {
	97	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	98	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	99	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	100	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	101	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	102	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
	103	};
097c584c	104
a8823143 TL	105	static void __iomem *tap_base;
a8823143 TL	106	static u16 tap_prod_id;
1dbae815	107
2e130fc3 KRC	108	void omap_get_die_id(struct omap_die_id *odi)
	109	{
	110	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
	111	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
	112	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
	113	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
	114	}
	115
5ebc0d52	116	static void __init omap24xx_check_revision(void)
1dbae815 TL	117	{
1dbae815 TL	118	int i, j;
a8823143	119	u32 idcode, prod_id;
1dbae815	120	u16 hawkeye;
a8823143	121	u8 dev_type, rev;
c46732bb	122	struct omap_die_id odi;
1dbae815 TL	123
1dbae815 TL	124	idcode = read_tap_reg(OMAP_TAP_IDCODE);
0e564848	125	prod_id = read_tap_reg(tap_prod_id);
1dbae815 TL	126	hawkeye = (idcode >> 12) & 0xffff;
	127	rev = (idcode >> 28) & 0x0f;
	128	dev_type = (prod_id >> 16) & 0x0f;
c46732bb	129	omap_get_die_id(&odi);
1dbae815	130
097c584c PW	131	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
097c584c PW	132	idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
c46732bb	133	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
097c584c	134	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
c46732bb KRC	135	odi.id_1, (odi.id_1 >> 28) & 0xf);
	136	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
	137	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
097c584c PW	138	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
	139	prod_id, dev_type);
	140
1dbae815 TL	141	/* Check hawkeye ids */
	142	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
	143	if (hawkeye == omap_ids[i].hawkeye)
	144	break;
	145	}
	146
	147	if (i == ARRAY_SIZE(omap_ids)) {
	148	printk(KERN_ERR "Unknown OMAP CPU id\n");
	149	return;
	150	}
	151
	152	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
	153	if (dev_type == omap_ids[j].dev)
	154	break;
	155	}
	156
	157	if (j == ARRAY_SIZE(omap_ids)) {
	158	printk(KERN_ERR "Unknown OMAP device type. "
	159	"Handling it as OMAP%04x\n",
	160	omap_ids[i].type >> 16);
	161	j = i;
	162	}
1dbae815	163
84a34344 LL	164	pr_info("OMAP%04x", omap_rev() >> 16);
	165	if ((omap_rev() >> 8) & 0x0f)
	166	pr_info("ES%x", (omap_rev() >> 12) & 0xf);
097c584c	167	pr_info("\n");
a8823143 TL	168	}
a8823143 TL	169
8384ce07 SP	170	#define OMAP3_CHECK_FEATURE(status,feat) \
	171	if (((status & OMAP3_ ##feat## _MASK) \
	172	>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
	173	omap3_features \|= OMAP3_HAS_ ##feat; \
	174	}
	175
5ebc0d52	176	static void __init omap3_check_features(void)
8384ce07 SP	177	{
	178	u32 status;
	179
	180	omap3_features = 0;
	181
	182	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
	183
	184	OMAP3_CHECK_FEATURE(status, L2CACHE);
	185	OMAP3_CHECK_FEATURE(status, IVA);
	186	OMAP3_CHECK_FEATURE(status, SGX);
	187	OMAP3_CHECK_FEATURE(status, NEON);
	188	OMAP3_CHECK_FEATURE(status, ISP);
7356f0b2 VB	189	if (cpu_is_omap3630())
7356f0b2 VB	190	omap3_features \|= OMAP3_HAS_192MHZ_CLK;
ad0c63f1	191	if (!cpu_is_omap3505() && !cpu_is_omap3517())
ad0c63f1	192	omap3_features \|= OMAP3_HAS_IO_WAKEUP;
8384ce07	193
01001712 HP	194	omap3_features \|= OMAP3_HAS_SDRC;
01001712 HP	195
8384ce07 SP	196	/*
	197	* TODO: Get additional info (where applicable)
	198	* e.g. Size of L2 cache.
	199	*/
	200	}
	201
01001712 HP	202	static void __init ti816x_check_features(void)
	203	{
	204	omap3_features = OMAP3_HAS_NEON;
	205	}
	206
5ebc0d52	207	static void __init omap3_check_revision(void)
a8823143 TL	208	{
	209	u32 cpuid, idcode;
	210	u16 hawkeye;
	211	u8 rev;
a8823143	212
e9acb9b6 TL	213	omap_chip.oc = CHIP_IS_OMAP3430;
e9acb9b6 TL	214
a8823143 TL	215	/*
	216	* We cannot access revision registers on ES1.0.
	217	* If the processor type is Cortex-A8 and the revision is 0x0
	218	* it means its Cortex r0p0 which is 3430 ES1.0.
	219	*/
	220	cpuid = read_cpuid(CPUID_ID);
	221	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
84a34344	222	omap_revision = OMAP3430_REV_ES1_0;
e9acb9b6	223	omap_chip.oc \|= CHIP_IS_OMAP3430ES1;
048f4bd7	224	return;
a8823143 TL	225	}
	226
	227	/*
	228	* Detection for 34xx ES2.0 and above can be done with just
	229	* hawkeye and rev. See TRM 1.5.2 Device Identification.
	230	* Note that rev does not map directly to our defined processor
	231	* revision numbers as ES1.0 uses value 0.
	232	*/
	233	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	234	hawkeye = (idcode >> 12) & 0xffff;
	235	rev = (idcode >> 28) & 0xff;
097c584c	236
2456a10f NM	237	switch (hawkeye) {
	238	case 0xb7ae:
	239	/* Handle 34xx/35xx devices */
a8823143	240	switch (rev) {
048f4bd7 SP	241	case 0: /* Take care of early samples */
048f4bd7 SP	242	case 1:
84a34344	243	omap_revision = OMAP3430_REV_ES2_0;
e9acb9b6	244	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	245	break;
a8823143 TL	246	case 2:
84a34344	247	omap_revision = OMAP3430_REV_ES2_1;
e9acb9b6	248	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	249	break;
a8823143 TL	250	case 3:
84a34344	251	omap_revision = OMAP3430_REV_ES3_0;
e9acb9b6	252	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_0;
a8823143	253	break;
187e688d	254	case 4:
e9acb9b6 TL	255	omap_revision = OMAP3430_REV_ES3_1;
	256	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
	257	break;
	258	case 7:
edeae658	259	/* FALLTHROUGH */
a8823143 TL	260	default:
a8823143 TL	261	/* Use the latest known revision as default */
e9acb9b6 TL	262	omap_revision = OMAP3430_REV_ES3_1_2;
	263
	264	/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
	265	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
a8823143	266	}
2456a10f	267	break;
4cac6018 SP	268	case 0xb868:
	269	/* Handle OMAP35xx/AM35xx devices
	270	*
	271	* Set the device to be OMAP3505 here. Actual device
	272	* is identified later based on the features.
e9acb9b6 TL	273	*
e9acb9b6 TL	274	* REVISIT: AM3505/AM3517 should have their own CHIP_IS
4cac6018 SP	275	*/
4cac6018 SP	276	omap_revision = OMAP3505_REV(rev);
e9acb9b6	277	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
4cac6018	278	break;
edeae658	279	case 0xb891:
b0a1a6ce AG	280	/* Handle 36xx devices */
	281	omap_chip.oc \|= CHIP_IS_OMAP3630ES1;
	282
	283	switch(rev) {
	284	case 0: /* Take care of early samples */
	285	omap_revision = OMAP3630_REV_ES1_0;
	286	break;
	287	case 1:
	288	omap_revision = OMAP3630_REV_ES1_1;
	289	omap_chip.oc \|= CHIP_IS_OMAP3630ES1_1;
	290	break;
	291	case 2:
	292	default:
	293	omap_revision = OMAP3630_REV_ES1_2;
	294	omap_chip.oc \|= CHIP_IS_OMAP3630ES1_2;
b0a1a6ce	295	}
77c0870c	296	break;
01001712 HP	297	case 0xb81e:
	298	omap_chip.oc = CHIP_IS_TI816X;
	299
	300	switch (rev) {
	301	case 0:
	302	omap_revision = TI8168_REV_ES1_0;
	303	break;
	304	case 1:
	305	omap_revision = TI8168_REV_ES1_1;
	306	break;
	307	default:
	308	omap_revision = TI8168_REV_ES1_1;
	309	}
	310	break;
2456a10f NM	311	default:
2456a10f NM	312	/* Unknown default to latest silicon rev as default*/
b0a1a6ce AG	313	omap_revision = OMAP3630_REV_ES1_2;
b0a1a6ce AG	314	omap_chip.oc \|= CHIP_IS_OMAP3630ES1_2;
a8823143	315	}
1dbae815 TL	316	}
1dbae815 TL	317
5ebc0d52	318	static void __init omap4_check_revision(void)
b570e0ec SS	319	{
	320	u32 idcode;
	321	u16 hawkeye;
	322	u8 rev;
b570e0ec SS	323
	324	/*
	325	* The IC rev detection is done with hawkeye and rev.
	326	* Note that rev does not map directly to defined processor
	327	* revision numbers as ES1.0 uses value 0.
	328	*/
	329	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	330	hawkeye = (idcode >> 12) & 0xffff;
	331	rev = (idcode >> 28) & 0xff;
	332
ed6be0ba SS	333	/*
	334	* Few initial ES2.0 samples IDCODE is same as ES1.0
	335	* Use ARM register to detect the correct ES version
	336	*/
	337	if (!rev) {
	338	idcode = read_cpuid(CPUID_ID);
	339	rev = (idcode & 0xf) - 1;
	340	}
	341
	342	switch (hawkeye) {
	343	case 0xb852:
	344	switch (rev) {
	345	case 0:
	346	omap_revision = OMAP4430_REV_ES1_0;
	347	omap_chip.oc \|= CHIP_IS_OMAP4430ES1;
	348	break;
	349	case 1:
	350	omap_revision = OMAP4430_REV_ES2_0;
	351	omap_chip.oc \|= CHIP_IS_OMAP4430ES2;
	352	break;
	353	default:
	354	omap_revision = OMAP4430_REV_ES2_0;
	355	omap_chip.oc \|= CHIP_IS_OMAP4430ES2;
	356	}
	357	break;
	358	default:
	359	/* Unknown default to latest silicon rev as default*/
	360	omap_revision = OMAP4430_REV_ES2_0;
	361	omap_chip.oc \|= CHIP_IS_OMAP4430ES2;
b570e0ec SS	362	}
b570e0ec SS	363
ed6be0ba SS	364	pr_info("OMAP%04x ES%d.0\n",
ed6be0ba SS	365	omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
b570e0ec SS	366	}
b570e0ec SS	367
8384ce07	368	#define OMAP3_SHOW_FEATURE(feat) \
cedf900d KH	369	if (omap3_has_ ##feat()) \
cedf900d KH	370	printk(#feat" ");
8384ce07	371
5ebc0d52	372	static void __init omap3_cpuinfo(void)
8384ce07	373	{
048f4bd7 SP	374	u8 rev = GET_OMAP_REVISION();
	375	char cpu_name[16], cpu_rev[16];
	376
	377	/* OMAP3430 and OMAP3530 are assumed to be same.
	378	*
	379	* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	380	* on available features. Upon detection, update the CPU id
	381	* and CPU class bits.
	382	*/
edeae658	383	if (cpu_is_omap3630()) {
4cac6018	384	strcpy(cpu_name, "OMAP3630");
edeae658	385	} else if (cpu_is_omap3505()) {
4cac6018 SP	386	/*
	387	* AM35xx devices
	388	*/
	389	if (omap3_has_sgx()) {
	390	omap_revision = OMAP3517_REV(rev);
	391	strcpy(cpu_name, "AM3517");
edeae658	392	} else {
4cac6018 SP	393	/* Already set in omap3_check_revision() */
	394	strcpy(cpu_name, "AM3505");
	395	}
01001712 HP	396	} else if (cpu_is_ti816x()) {
01001712 HP	397	strcpy(cpu_name, "TI816X");
edeae658 FB	398	} else if (omap3_has_iva() && omap3_has_sgx()) {
edeae658 FB	399	/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
4cac6018	400	strcpy(cpu_name, "OMAP3430/3530");
0712fb39	401	} else if (omap3_has_iva()) {
048f4bd7	402	omap_revision = OMAP3525_REV(rev);
4cac6018	403	strcpy(cpu_name, "OMAP3525");
0712fb39	404	} else if (omap3_has_sgx()) {
048f4bd7	405	omap_revision = OMAP3515_REV(rev);
4cac6018	406	strcpy(cpu_name, "OMAP3515");
edeae658	407	} else {
048f4bd7	408	omap_revision = OMAP3503_REV(rev);
4cac6018	409	strcpy(cpu_name, "OMAP3503");
048f4bd7 SP	410	}
048f4bd7 SP	411
01001712	412	if (cpu_is_omap3630() \|\| cpu_is_ti816x()) {
76abab21 SP	413	switch (rev) {
	414	case OMAP_REVBITS_00:
	415	strcpy(cpu_rev, "1.0");
	416	break;
	417	case OMAP_REVBITS_01:
	418	strcpy(cpu_rev, "1.1");
	419	break;
	420	case OMAP_REVBITS_02:
	421	/* FALLTHROUGH */
	422	default:
	423	/* Use the latest known revision as default */
	424	strcpy(cpu_rev, "1.2");
	425	}
	426	} else if (cpu_is_omap3505() \|\| cpu_is_omap3517()) {
	427	switch (rev) {
	428	case OMAP_REVBITS_00:
	429	strcpy(cpu_rev, "1.0");
	430	break;
	431	case OMAP_REVBITS_01:
	432	/* FALLTHROUGH */
	433	default:
	434	/* Use the latest known revision as default */
	435	strcpy(cpu_rev, "1.1");
	436	}
	437	} else {
	438	switch (rev) {
	439	case OMAP_REVBITS_00:
	440	strcpy(cpu_rev, "1.0");
	441	break;
	442	case OMAP_REVBITS_01:
	443	strcpy(cpu_rev, "2.0");
	444	break;
	445	case OMAP_REVBITS_02:
	446	strcpy(cpu_rev, "2.1");
	447	break;
	448	case OMAP_REVBITS_03:
	449	strcpy(cpu_rev, "3.0");
	450	break;
	451	case OMAP_REVBITS_04:
	452	strcpy(cpu_rev, "3.1");
	453	break;
	454	case OMAP_REVBITS_05:
	455	/* FALLTHROUGH */
	456	default:
	457	/* Use the latest known revision as default */
	458	strcpy(cpu_rev, "3.1.2");
	459	}
048f4bd7 SP	460	}
048f4bd7 SP	461
edeae658	462	/* Print verbose information */
cedf900d	463	pr_info("%s ES%s (", cpu_name, cpu_rev);
048f4bd7	464
8384ce07 SP	465	OMAP3_SHOW_FEATURE(l2cache);
	466	OMAP3_SHOW_FEATURE(iva);
	467	OMAP3_SHOW_FEATURE(sgx);
	468	OMAP3_SHOW_FEATURE(neon);
	469	OMAP3_SHOW_FEATURE(isp);
7356f0b2	470	OMAP3_SHOW_FEATURE(192mhz_clk);
cedf900d KH	471
cedf900d KH	472	printk(")\n");
8384ce07 SP	473	}
8384ce07 SP	474
a8823143 TL	475	/*
	476	* Try to detect the exact revision of the omap we're running on
	477	*/
5ba02dca TL	478	void __init omap2_check_revision(void)
5ba02dca TL	479	{
a8823143 TL	480	/*
	481	* At this point we have an idea about the processor revision set
	482	* earlier with omap2_set_globals_tap().
	483	*/
edeae658	484	if (cpu_is_omap24xx()) {
a8823143	485	omap24xx_check_revision();
edeae658	486	} else if (cpu_is_omap34xx()) {
8384ce07	487	omap3_check_revision();
01001712 HP	488
	489	/* TI816X doesn't have feature register */
	490	if (!cpu_is_ti816x())
	491	omap3_check_features();
	492	else
	493	ti816x_check_features();
	494
8384ce07	495	omap3_cpuinfo();
e9acb9b6	496	return;
edeae658	497	} else if (cpu_is_omap44xx()) {
b570e0ec	498	omap4_check_revision();
44169075	499	return;
edeae658	500	} else {
a8823143	501	pr_err("OMAP revision unknown, please fix!\n");
edeae658	502	}
a8823143 TL	503
	504	/*
	505	* OK, now we know the exact revision. Initialize omap_chip bits
	506	* for powerdowmain and clockdomain code.
	507	*/
	508	if (cpu_is_omap243x()) {
	509	/* Currently only supports 2430ES2.1 and 2430-all */
	510	omap_chip.oc \|= CHIP_IS_OMAP2430;
e9acb9b6	511	return;
a8823143 TL	512	} else if (cpu_is_omap242x()) {
	513	/* Currently only supports 2420ES2.1.1 and 2420-all */
	514	omap_chip.oc \|= CHIP_IS_OMAP2420;
e9acb9b6	515	return;
a8823143	516	}
e9acb9b6 TL	517
e9acb9b6 TL	518	pr_err("Uninitialized omap_chip, please fix!\n");
5ba02dca TL	519	}
5ba02dca TL	520
a8823143 TL	521	/*
	522	* Set up things for map_io and processor detection later on. Gets called
	523	* pretty much first thing from board init. For multi-omap, this gets
	524	* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
	525	* detect the exact revision later on in omap2_detect_revision() once map_io
	526	* is done.
	527	*/
0e564848 TL	528	void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
0e564848 TL	529	{
84a34344	530	omap_revision = omap2_globals->class;
0e564848 TL	531	tap_base = omap2_globals->tap;
0e564848 TL	532
a8823143	533	if (cpu_is_omap34xx())
0e564848 TL	534	tap_prod_id = 0x0210;
	535	else
	536	tap_prod_id = 0x0208;
	537	}