[deliverable/linux.git] / arch / arm / mach-omap2 / id.c

/*
 * linux/arch/arm/mach-omap2/id.c
 *
 * OMAP2 CPU identification code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/cputype.h>

#include <plat/common.h>
#include <plat/control.h>
#include <plat/cpu.h>

static struct omap_chip_id omap_chip;
static unsigned int omap_revision;

u32 omap3_features;

unsigned int omap_rev(void)
{
	return omap_revision;
}
EXPORT_SYMBOL(omap_rev);

/**
 * omap_chip_is - test whether currently running OMAP matches a chip type
 * @oc: omap_chip_t to test against
 *
 * Test whether the currently-running OMAP chip matches the supplied
 * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
 */
int omap_chip_is(struct omap_chip_id oci)
{
	return (oci.oc & omap_chip.oc) ? 1 : 0;
}
EXPORT_SYMBOL(omap_chip_is);

int omap_type(void)
{
	u32 val = 0;

	if (cpu_is_omap24xx()) {
		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
	} else if (cpu_is_omap34xx()) {
		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
	} else {
		pr_err("Cannot detect omap type!\n");
		goto out;
	}

	val &= OMAP2_DEVICETYPE_MASK;
	val >>= 8;

out:
	return val;
}
EXPORT_SYMBOL(omap_type);


/*----------------------------------------------------------------------------*/

#define OMAP_TAP_IDCODE		0x0204
#define OMAP_TAP_DIE_ID_0	0x0218
#define OMAP_TAP_DIE_ID_1	0x021C
#define OMAP_TAP_DIE_ID_2	0x0220
#define OMAP_TAP_DIE_ID_3	0x0224

#define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))

struct omap_id {
	u16	hawkeye;	/* Silicon type (Hawkeye id) */
	u8	dev;		/* Device type from production_id reg */
	u32	type;		/* Combined type id copied to omap_revision */
};

/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
};

static void __iomem *tap_base;
static u16 tap_prod_id;

void __init omap24xx_check_revision(void)
{
	int i, j;
	u32 idcode, prod_id;
	u16 hawkeye;
	u8  dev_type, rev;

	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	prod_id = read_tap_reg(tap_prod_id);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0x0f;
	dev_type = (prod_id >> 16) & 0x0f;

	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
		 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_0));
	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_1),
		 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_2));
	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_3));
	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
		 prod_id, dev_type);

	/* Check hawkeye ids */
	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
		if (hawkeye == omap_ids[i].hawkeye)
			break;
	}

	if (i == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP CPU id\n");
		return;
	}

	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
		if (dev_type == omap_ids[j].dev)
			break;
	}

	if (j == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP device type. "
				"Handling it as OMAP%04x\n",
				omap_ids[i].type >> 16);
		j = i;
	}

	pr_info("OMAP%04x", omap_rev() >> 16);
	if ((omap_rev() >> 8) & 0x0f)
		pr_info("ES%x", (omap_rev() >> 12) & 0xf);
	pr_info("\n");
}

#define OMAP3_CHECK_FEATURE(status,feat)				\
	if (((status & OMAP3_ ##feat## _MASK) 				\
		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
		omap3_features |= OMAP3_HAS_ ##feat;			\
	}

void __init omap3_check_features(void)
{
	u32 status;

	omap3_features = 0;

	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);

	OMAP3_CHECK_FEATURE(status, L2CACHE);
	OMAP3_CHECK_FEATURE(status, IVA);
	OMAP3_CHECK_FEATURE(status, SGX);
	OMAP3_CHECK_FEATURE(status, NEON);
	OMAP3_CHECK_FEATURE(status, ISP);

	/*
	 * TODO: Get additional info (where applicable)
	 *       e.g. Size of L2 cache.
	 */
}

void __init omap3_check_revision(void)
{
	u32 cpuid, idcode;
	u16 hawkeye;
	u8 rev;

	omap_chip.oc = CHIP_IS_OMAP3430;

	/*
	 * We cannot access revision registers on ES1.0.
	 * If the processor type is Cortex-A8 and the revision is 0x0
	 * it means its Cortex r0p0 which is 3430 ES1.0.
	 */
	cpuid = read_cpuid(CPUID_ID);
	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
		omap_revision = OMAP3430_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP3430ES1;
		return;
	}

	/*
	 * Detection for 34xx ES2.0 and above can be done with just
	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
	 * Note that rev does not map directly to our defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	switch (hawkeye) {
	case 0xb7ae:
		/* Handle 34xx/35xx devices */
		switch (rev) {
		case 0: /* Take care of early samples */
		case 1:
			omap_revision = OMAP3430_REV_ES2_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 2:
			omap_revision = OMAP3430_REV_ES2_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 3:
			omap_revision = OMAP3430_REV_ES3_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
			break;
		case 4:
			omap_revision = OMAP3430_REV_ES3_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
			break;
		case 7:
		/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			omap_revision = OMAP3430_REV_ES3_1_2;

			/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		}
		break;
	case 0xb868:
		/* Handle OMAP35xx/AM35xx devices
		 *
		 * Set the device to be OMAP3505 here. Actual device
		 * is identified later based on the features.
		 *
		 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
		 */
		omap_revision = OMAP3505_REV(rev);
		omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		break;
	case 0xb891:
	/* FALLTHROUGH */
	default:
		/* Unknown default to latest silicon rev as default*/
		omap_revision = OMAP3630_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP3630ES1;
	}
}

void __init omap4_check_revision(void)
{
	u32 idcode;
	u16 hawkeye;
	u8 rev;
	char *rev_name = "ES1.0";

	/*
	 * The IC rev detection is done with hawkeye and rev.
	 * Note that rev does not map directly to defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	if ((hawkeye == 0xb852) && (rev == 0x0)) {
		omap_revision = OMAP4430_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP4430ES1;
		pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
		return;
	}

	pr_err("Unknown OMAP4 CPU id\n");
}

#define OMAP3_SHOW_FEATURE(feat)		\
	if (omap3_has_ ##feat())		\
		printk(#feat" ");

void __init omap3_cpuinfo(void)
{
	u8 rev = GET_OMAP_REVISION();
	char cpu_name[16], cpu_rev[16];

	/* OMAP3430 and OMAP3530 are assumed to be same.
	 *
	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	 * on available features. Upon detection, update the CPU id
	 * and CPU class bits.
	 */
	if (cpu_is_omap3630()) {
		strcpy(cpu_name, "OMAP3630");
	} else if (cpu_is_omap3505()) {
		/*
		 * AM35xx devices
		 */
		if (omap3_has_sgx()) {
			omap_revision = OMAP3517_REV(rev);
			strcpy(cpu_name, "AM3517");
		} else {
			/* Already set in omap3_check_revision() */
			strcpy(cpu_name, "AM3505");
		}
	} else if (omap3_has_iva() && omap3_has_sgx()) {
		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
		strcpy(cpu_name, "OMAP3430/3530");
	} else if (omap3_has_iva()) {
		omap_revision = OMAP3525_REV(rev);
		strcpy(cpu_name, "OMAP3525");
	} else if (omap3_has_sgx()) {
		omap_revision = OMAP3515_REV(rev);
		strcpy(cpu_name, "OMAP3515");
	} else {
		omap_revision = OMAP3503_REV(rev);
		strcpy(cpu_name, "OMAP3503");
	}

	switch (rev) {
	case OMAP_REVBITS_00:
		strcpy(cpu_rev, "1.0");
		break;
	case OMAP_REVBITS_10:
		strcpy(cpu_rev, "2.0");
		break;
	case OMAP_REVBITS_20:
		strcpy(cpu_rev, "2.1");
		break;
	case OMAP_REVBITS_30:
		strcpy(cpu_rev, "3.0");
		break;
	case OMAP_REVBITS_40:
	/* FALLTHROUGH */
	default:
		/* Use the latest known revision as default */
		strcpy(cpu_rev, "3.1");
	}

	/* Print verbose information */
	pr_info("%s ES%s (", cpu_name, cpu_rev);

	OMAP3_SHOW_FEATURE(l2cache);
	OMAP3_SHOW_FEATURE(iva);
	OMAP3_SHOW_FEATURE(sgx);
	OMAP3_SHOW_FEATURE(neon);
	OMAP3_SHOW_FEATURE(isp);

	printk(")\n");
}

/*
 * Try to detect the exact revision of the omap we're running on
 */
void __init omap2_check_revision(void)
{
	/*
	 * At this point we have an idea about the processor revision set
	 * earlier with omap2_set_globals_tap().
	 */
	if (cpu_is_omap24xx()) {
		omap24xx_check_revision();
	} else if (cpu_is_omap34xx()) {
		omap3_check_revision();
		omap3_check_features();
		omap3_cpuinfo();
		return;
	} else if (cpu_is_omap44xx()) {
		omap4_check_revision();
		return;
	} else {
		pr_err("OMAP revision unknown, please fix!\n");
	}

	/*
	 * OK, now we know the exact revision. Initialize omap_chip bits
	 * for powerdowmain and clockdomain code.
	 */
	if (cpu_is_omap243x()) {
		/* Currently only supports 2430ES2.1 and 2430-all */
		omap_chip.oc |= CHIP_IS_OMAP2430;
		return;
	} else if (cpu_is_omap242x()) {
		/* Currently only supports 2420ES2.1.1 and 2420-all */
		omap_chip.oc |= CHIP_IS_OMAP2420;
		return;
	}

	pr_err("Uninitialized omap_chip, please fix!\n");
}

/*
 * Set up things for map_io and processor detection later on. Gets called
 * pretty much first thing from board init. For multi-omap, this gets
 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 * detect the exact revision later on in omap2_detect_revision() once map_io
 * is done.
 */
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
{
	omap_revision = omap2_globals->class;
	tap_base = omap2_globals->tap;

	if (cpu_is_omap34xx())
		tap_prod_id = 0x0210;
	else
		tap_prod_id = 0x0208;
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/id.c
	3	*
	4	* OMAP2 CPU identification code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
44169075 SS	9	* Copyright (C) 2009 Texas Instruments
	10	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	11	*
1dbae815 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
1dbae815 TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
fced80c7	20	#include <linux/io.h>
1dbae815	21
0ba8b9b2	22	#include <asm/cputype.h>
1dbae815	23
ce491cf8 TL	24	#include <plat/common.h>
	25	#include <plat/control.h>
	26	#include <plat/cpu.h>
72d0f1c3	27
097c584c	28	static struct omap_chip_id omap_chip;
84a34344 LL	29	static unsigned int omap_revision;
84a34344 LL	30
8384ce07	31	u32 omap3_features;
84a34344 LL	32
	33	unsigned int omap_rev(void)
	34	{
	35	return omap_revision;
	36	}
	37	EXPORT_SYMBOL(omap_rev);
097c584c PW	38
	39	/**
	40	* omap_chip_is - test whether currently running OMAP matches a chip type
	41	* @oc: omap_chip_t to test against
	42	*
	43	* Test whether the currently-running OMAP chip matches the supplied
	44	* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
	45	*/
	46	int omap_chip_is(struct omap_chip_id oci)
	47	{
	48	return (oci.oc & omap_chip.oc) ? 1 : 0;
	49	}
	50	EXPORT_SYMBOL(omap_chip_is);
	51
8e25ad96 KH	52	int omap_type(void)
	53	{
	54	u32 val = 0;
	55
edeae658	56	if (cpu_is_omap24xx()) {
8e25ad96	57	val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
edeae658	58	} else if (cpu_is_omap34xx()) {
8e25ad96	59	val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
edeae658	60	} else {
8e25ad96 KH	61	pr_err("Cannot detect omap type!\n");
	62	goto out;
	63	}
	64
	65	val &= OMAP2_DEVICETYPE_MASK;
	66	val >>= 8;
	67
	68	out:
	69	return val;
	70	}
	71	EXPORT_SYMBOL(omap_type);
	72
	73
a8823143	74	/----------------------------------------------------------------------------/
097c584c	75
a8823143 TL	76	#define OMAP_TAP_IDCODE 0x0204
	77	#define OMAP_TAP_DIE_ID_0 0x0218
	78	#define OMAP_TAP_DIE_ID_1 0x021C
	79	#define OMAP_TAP_DIE_ID_2 0x0220
	80	#define OMAP_TAP_DIE_ID_3 0x0224
097c584c	81
a8823143	82	#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
097c584c	83
a8823143 TL	84	struct omap_id {
	85	u16 hawkeye; /* Silicon type (Hawkeye id) */
	86	u8 dev; /* Device type from production_id reg */
84a34344	87	u32 type; /* Combined type id copied to omap_revision */
a8823143	88	};
097c584c	89
a8823143 TL	90	/* Register values to detect the OMAP version */
	91	static struct omap_id omap_ids[] __initdata = {
	92	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	93	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	94	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	95	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	96	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	97	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
	98	};
097c584c	99
a8823143 TL	100	static void __iomem *tap_base;
a8823143 TL	101	static u16 tap_prod_id;
1dbae815	102
5ba02dca	103	void __init omap24xx_check_revision(void)
1dbae815 TL	104	{
1dbae815 TL	105	int i, j;
a8823143	106	u32 idcode, prod_id;
1dbae815	107	u16 hawkeye;
a8823143	108	u8 dev_type, rev;
1dbae815 TL	109
1dbae815 TL	110	idcode = read_tap_reg(OMAP_TAP_IDCODE);
0e564848	111	prod_id = read_tap_reg(tap_prod_id);
1dbae815 TL	112	hawkeye = (idcode >> 12) & 0xffff;
	113	rev = (idcode >> 28) & 0x0f;
	114	dev_type = (prod_id >> 16) & 0x0f;
	115
097c584c PW	116	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
	117	idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	118	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
	119	read_tap_reg(OMAP_TAP_DIE_ID_0));
	120	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
	121	read_tap_reg(OMAP_TAP_DIE_ID_1),
	122	(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	123	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
	124	read_tap_reg(OMAP_TAP_DIE_ID_2));
	125	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
	126	read_tap_reg(OMAP_TAP_DIE_ID_3));
	127	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
	128	prod_id, dev_type);
	129
1dbae815 TL	130	/* Check hawkeye ids */
	131	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
	132	if (hawkeye == omap_ids[i].hawkeye)
	133	break;
	134	}
	135
	136	if (i == ARRAY_SIZE(omap_ids)) {
	137	printk(KERN_ERR "Unknown OMAP CPU id\n");
	138	return;
	139	}
	140
	141	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
	142	if (dev_type == omap_ids[j].dev)
	143	break;
	144	}
	145
	146	if (j == ARRAY_SIZE(omap_ids)) {
	147	printk(KERN_ERR "Unknown OMAP device type. "
	148	"Handling it as OMAP%04x\n",
	149	omap_ids[i].type >> 16);
	150	j = i;
	151	}
1dbae815	152
84a34344 LL	153	pr_info("OMAP%04x", omap_rev() >> 16);
	154	if ((omap_rev() >> 8) & 0x0f)
	155	pr_info("ES%x", (omap_rev() >> 12) & 0xf);
097c584c	156	pr_info("\n");
a8823143 TL	157	}
a8823143 TL	158
8384ce07 SP	159	#define OMAP3_CHECK_FEATURE(status,feat) \
	160	if (((status & OMAP3_ ##feat## _MASK) \
	161	>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
	162	omap3_features \|= OMAP3_HAS_ ##feat; \
	163	}
	164
	165	void __init omap3_check_features(void)
	166	{
	167	u32 status;
	168
	169	omap3_features = 0;
	170
	171	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
	172
	173	OMAP3_CHECK_FEATURE(status, L2CACHE);
	174	OMAP3_CHECK_FEATURE(status, IVA);
	175	OMAP3_CHECK_FEATURE(status, SGX);
	176	OMAP3_CHECK_FEATURE(status, NEON);
	177	OMAP3_CHECK_FEATURE(status, ISP);
	178
	179	/*
	180	* TODO: Get additional info (where applicable)
	181	* e.g. Size of L2 cache.
	182	*/
	183	}
	184
	185	void __init omap3_check_revision(void)
a8823143 TL	186	{
	187	u32 cpuid, idcode;
	188	u16 hawkeye;
	189	u8 rev;
a8823143	190
e9acb9b6 TL	191	omap_chip.oc = CHIP_IS_OMAP3430;
e9acb9b6 TL	192
a8823143 TL	193	/*
	194	* We cannot access revision registers on ES1.0.
	195	* If the processor type is Cortex-A8 and the revision is 0x0
	196	* it means its Cortex r0p0 which is 3430 ES1.0.
	197	*/
	198	cpuid = read_cpuid(CPUID_ID);
	199	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
84a34344	200	omap_revision = OMAP3430_REV_ES1_0;
e9acb9b6	201	omap_chip.oc \|= CHIP_IS_OMAP3430ES1;
048f4bd7	202	return;
a8823143 TL	203	}
	204
	205	/*
	206	* Detection for 34xx ES2.0 and above can be done with just
	207	* hawkeye and rev. See TRM 1.5.2 Device Identification.
	208	* Note that rev does not map directly to our defined processor
	209	* revision numbers as ES1.0 uses value 0.
	210	*/
	211	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	212	hawkeye = (idcode >> 12) & 0xffff;
	213	rev = (idcode >> 28) & 0xff;
097c584c	214
2456a10f NM	215	switch (hawkeye) {
	216	case 0xb7ae:
	217	/* Handle 34xx/35xx devices */
a8823143	218	switch (rev) {
048f4bd7 SP	219	case 0: /* Take care of early samples */
048f4bd7 SP	220	case 1:
84a34344	221	omap_revision = OMAP3430_REV_ES2_0;
e9acb9b6	222	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	223	break;
a8823143 TL	224	case 2:
84a34344	225	omap_revision = OMAP3430_REV_ES2_1;
e9acb9b6	226	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	227	break;
a8823143 TL	228	case 3:
84a34344	229	omap_revision = OMAP3430_REV_ES3_0;
e9acb9b6	230	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_0;
a8823143	231	break;
187e688d	232	case 4:
e9acb9b6 TL	233	omap_revision = OMAP3430_REV_ES3_1;
	234	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
	235	break;
	236	case 7:
edeae658	237	/* FALLTHROUGH */
a8823143 TL	238	default:
a8823143 TL	239	/* Use the latest known revision as default */
e9acb9b6 TL	240	omap_revision = OMAP3430_REV_ES3_1_2;
	241
	242	/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
	243	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
a8823143	244	}
2456a10f	245	break;
4cac6018 SP	246	case 0xb868:
	247	/* Handle OMAP35xx/AM35xx devices
	248	*
	249	* Set the device to be OMAP3505 here. Actual device
	250	* is identified later based on the features.
e9acb9b6 TL	251	*
e9acb9b6 TL	252	* REVISIT: AM3505/AM3517 should have their own CHIP_IS
4cac6018 SP	253	*/
4cac6018 SP	254	omap_revision = OMAP3505_REV(rev);
e9acb9b6	255	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
4cac6018	256	break;
edeae658 FB	257	case 0xb891:
edeae658 FB	258	/* FALLTHROUGH */
2456a10f NM	259	default:
	260	/* Unknown default to latest silicon rev as default*/
	261	omap_revision = OMAP3630_REV_ES1_0;
e9acb9b6	262	omap_chip.oc \|= CHIP_IS_OMAP3630ES1;
a8823143	263	}
1dbae815 TL	264	}
1dbae815 TL	265
b570e0ec SS	266	void __init omap4_check_revision(void)
	267	{
	268	u32 idcode;
	269	u16 hawkeye;
	270	u8 rev;
	271	char *rev_name = "ES1.0";
	272
	273	/*
	274	* The IC rev detection is done with hawkeye and rev.
	275	* Note that rev does not map directly to defined processor
	276	* revision numbers as ES1.0 uses value 0.
	277	*/
	278	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	279	hawkeye = (idcode >> 12) & 0xffff;
	280	rev = (idcode >> 28) & 0xff;
	281
	282	if ((hawkeye == 0xb852) && (rev == 0x0)) {
	283	omap_revision = OMAP4430_REV_ES1_0;
c6a6e6e2	284	omap_chip.oc \|= CHIP_IS_OMAP4430ES1;
b570e0ec SS	285	pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
	286	return;
	287	}
	288
	289	pr_err("Unknown OMAP4 CPU id\n");
	290	}
	291
8384ce07	292	#define OMAP3_SHOW_FEATURE(feat) \
cedf900d KH	293	if (omap3_has_ ##feat()) \
cedf900d KH	294	printk(#feat" ");
8384ce07 SP	295
	296	void __init omap3_cpuinfo(void)
	297	{
048f4bd7 SP	298	u8 rev = GET_OMAP_REVISION();
	299	char cpu_name[16], cpu_rev[16];
	300
	301	/* OMAP3430 and OMAP3530 are assumed to be same.
	302	*
	303	* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	304	* on available features. Upon detection, update the CPU id
	305	* and CPU class bits.
	306	*/
edeae658	307	if (cpu_is_omap3630()) {
4cac6018	308	strcpy(cpu_name, "OMAP3630");
edeae658	309	} else if (cpu_is_omap3505()) {
4cac6018 SP	310	/*
	311	* AM35xx devices
	312	*/
	313	if (omap3_has_sgx()) {
	314	omap_revision = OMAP3517_REV(rev);
	315	strcpy(cpu_name, "AM3517");
edeae658	316	} else {
4cac6018 SP	317	/* Already set in omap3_check_revision() */
	318	strcpy(cpu_name, "AM3505");
	319	}
edeae658 FB	320	} else if (omap3_has_iva() && omap3_has_sgx()) {
edeae658 FB	321	/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
4cac6018	322	strcpy(cpu_name, "OMAP3430/3530");
0712fb39	323	} else if (omap3_has_iva()) {
048f4bd7	324	omap_revision = OMAP3525_REV(rev);
4cac6018	325	strcpy(cpu_name, "OMAP3525");
0712fb39	326	} else if (omap3_has_sgx()) {
048f4bd7	327	omap_revision = OMAP3515_REV(rev);
4cac6018	328	strcpy(cpu_name, "OMAP3515");
edeae658	329	} else {
048f4bd7	330	omap_revision = OMAP3503_REV(rev);
4cac6018	331	strcpy(cpu_name, "OMAP3503");
048f4bd7 SP	332	}
	333
	334	switch (rev) {
	335	case OMAP_REVBITS_00:
	336	strcpy(cpu_rev, "1.0");
	337	break;
	338	case OMAP_REVBITS_10:
	339	strcpy(cpu_rev, "2.0");
	340	break;
	341	case OMAP_REVBITS_20:
	342	strcpy(cpu_rev, "2.1");
	343	break;
	344	case OMAP_REVBITS_30:
	345	strcpy(cpu_rev, "3.0");
	346	break;
	347	case OMAP_REVBITS_40:
edeae658	348	/* FALLTHROUGH */
048f4bd7 SP	349	default:
	350	/* Use the latest known revision as default */
	351	strcpy(cpu_rev, "3.1");
	352	}
	353
edeae658	354	/* Print verbose information */
cedf900d	355	pr_info("%s ES%s (", cpu_name, cpu_rev);
048f4bd7	356
8384ce07 SP	357	OMAP3_SHOW_FEATURE(l2cache);
	358	OMAP3_SHOW_FEATURE(iva);
	359	OMAP3_SHOW_FEATURE(sgx);
	360	OMAP3_SHOW_FEATURE(neon);
	361	OMAP3_SHOW_FEATURE(isp);
cedf900d KH	362
cedf900d KH	363	printk(")\n");
8384ce07 SP	364	}
8384ce07 SP	365
a8823143 TL	366	/*
	367	* Try to detect the exact revision of the omap we're running on
	368	*/
5ba02dca TL	369	void __init omap2_check_revision(void)
5ba02dca TL	370	{
a8823143 TL	371	/*
	372	* At this point we have an idea about the processor revision set
	373	* earlier with omap2_set_globals_tap().
	374	*/
edeae658	375	if (cpu_is_omap24xx()) {
a8823143	376	omap24xx_check_revision();
edeae658	377	} else if (cpu_is_omap34xx()) {
8384ce07	378	omap3_check_revision();
05574bb2	379	omap3_check_features();
8384ce07	380	omap3_cpuinfo();
e9acb9b6	381	return;
edeae658	382	} else if (cpu_is_omap44xx()) {
b570e0ec	383	omap4_check_revision();
44169075	384	return;
edeae658	385	} else {
a8823143	386	pr_err("OMAP revision unknown, please fix!\n");
edeae658	387	}
a8823143 TL	388
	389	/*
	390	* OK, now we know the exact revision. Initialize omap_chip bits
	391	* for powerdowmain and clockdomain code.
	392	*/
	393	if (cpu_is_omap243x()) {
	394	/* Currently only supports 2430ES2.1 and 2430-all */
	395	omap_chip.oc \|= CHIP_IS_OMAP2430;
e9acb9b6	396	return;
a8823143 TL	397	} else if (cpu_is_omap242x()) {
	398	/* Currently only supports 2420ES2.1.1 and 2420-all */
	399	omap_chip.oc \|= CHIP_IS_OMAP2420;
e9acb9b6	400	return;
a8823143	401	}
e9acb9b6 TL	402
e9acb9b6 TL	403	pr_err("Uninitialized omap_chip, please fix!\n");
5ba02dca TL	404	}
5ba02dca TL	405
a8823143 TL	406	/*
	407	* Set up things for map_io and processor detection later on. Gets called
	408	* pretty much first thing from board init. For multi-omap, this gets
	409	* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
	410	* detect the exact revision later on in omap2_detect_revision() once map_io
	411	* is done.
	412	*/
0e564848 TL	413	void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
0e564848 TL	414	{
84a34344	415	omap_revision = omap2_globals->class;
0e564848 TL	416	tap_base = omap2_globals->tap;
0e564848 TL	417
a8823143	418	if (cpu_is_omap34xx())
0e564848 TL	419	tap_prod_id = 0x0210;
	420	else
	421	tap_prod_id = 0x0208;
	422	}