Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
6770b211 RB |
21 | #include <linux/slab.h> |
22 | ||
23 | #ifdef CONFIG_SOC_BUS | |
24 | #include <linux/sys_soc.h> | |
25 | #endif | |
1dbae815 | 26 | |
0ba8b9b2 | 27 | #include <asm/cputype.h> |
1dbae815 | 28 | |
4e65331c | 29 | #include "common.h" |
72d0f1c3 | 30 | |
4952af43 | 31 | #include "id.h" |
2e130fc3 | 32 | |
dbc04161 | 33 | #include "soc.h" |
4814ced5 PW |
34 | #include "control.h" |
35 | ||
42a1cc9c IK |
36 | #define OMAP4_SILICON_TYPE_STANDARD 0x01 |
37 | #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 | |
38 | ||
f9d41eef RB |
39 | #define OMAP_SOC_MAX_NAME_LENGTH 16 |
40 | ||
84a34344 | 41 | static unsigned int omap_revision; |
f9d41eef RB |
42 | static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; |
43 | static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; | |
cc0170b2 | 44 | u32 omap_features; |
84a34344 LL |
45 | |
46 | unsigned int omap_rev(void) | |
47 | { | |
48 | return omap_revision; | |
49 | } | |
50 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 51 | |
8e25ad96 KH |
52 | int omap_type(void) |
53 | { | |
54 | u32 val = 0; | |
55 | ||
edeae658 | 56 | if (cpu_is_omap24xx()) { |
8e25ad96 | 57 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
49cc485d | 58 | } else if (soc_is_am33xx() || soc_is_am43xx()) { |
fb3cfb1f | 59 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); |
edeae658 | 60 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 61 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 62 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 63 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
b13e80a8 S |
64 | } else if (soc_is_omap54xx()) { |
65 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); | |
66 | val &= OMAP5_DEVICETYPE_MASK; | |
67 | val >>= 6; | |
68 | goto out; | |
edeae658 | 69 | } else { |
8e25ad96 KH |
70 | pr_err("Cannot detect omap type!\n"); |
71 | goto out; | |
72 | } | |
73 | ||
74 | val &= OMAP2_DEVICETYPE_MASK; | |
75 | val >>= 8; | |
76 | ||
77 | out: | |
78 | return val; | |
79 | } | |
80 | EXPORT_SYMBOL(omap_type); | |
81 | ||
82 | ||
a8823143 | 83 | /*----------------------------------------------------------------------------*/ |
097c584c | 84 | |
a8823143 TL |
85 | #define OMAP_TAP_IDCODE 0x0204 |
86 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
87 | #define OMAP_TAP_DIE_ID_1 0x021C | |
88 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
89 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 90 | |
b235e007 AG |
91 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
92 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
93 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
94 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
95 | ||
a8823143 | 96 | #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) |
097c584c | 97 | |
a8823143 TL |
98 | struct omap_id { |
99 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
100 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 101 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 102 | }; |
097c584c | 103 | |
a8823143 TL |
104 | /* Register values to detect the OMAP version */ |
105 | static struct omap_id omap_ids[] __initdata = { | |
106 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
107 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
108 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
109 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
110 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
111 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
112 | }; | |
097c584c | 113 | |
a8823143 TL |
114 | static void __iomem *tap_base; |
115 | static u16 tap_prod_id; | |
1dbae815 | 116 | |
2e130fc3 KRC |
117 | void omap_get_die_id(struct omap_die_id *odi) |
118 | { | |
b13e80a8 | 119 | if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
b235e007 AG |
120 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); |
121 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
122 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
123 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
124 | ||
125 | return; | |
126 | } | |
2e130fc3 KRC |
127 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
128 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
129 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
130 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
131 | } | |
132 | ||
4de34f35 | 133 | void __init omap2xxx_check_revision(void) |
1dbae815 TL |
134 | { |
135 | int i, j; | |
a8823143 | 136 | u32 idcode, prod_id; |
1dbae815 | 137 | u16 hawkeye; |
a8823143 | 138 | u8 dev_type, rev; |
c46732bb | 139 | struct omap_die_id odi; |
1dbae815 TL |
140 | |
141 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 142 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
143 | hawkeye = (idcode >> 12) & 0xffff; |
144 | rev = (idcode >> 28) & 0x0f; | |
145 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 146 | omap_get_die_id(&odi); |
1dbae815 | 147 | |
097c584c PW |
148 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
149 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 150 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 151 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
152 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
153 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
154 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
155 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
156 | prod_id, dev_type); | |
157 | ||
1dbae815 TL |
158 | /* Check hawkeye ids */ |
159 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
160 | if (hawkeye == omap_ids[i].hawkeye) | |
161 | break; | |
162 | } | |
163 | ||
164 | if (i == ARRAY_SIZE(omap_ids)) { | |
165 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
166 | return; | |
167 | } | |
168 | ||
169 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
170 | if (dev_type == omap_ids[j].dev) | |
171 | break; | |
172 | } | |
173 | ||
174 | if (j == ARRAY_SIZE(omap_ids)) { | |
7852ec05 PW |
175 | pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", |
176 | omap_ids[i].type >> 16); | |
1dbae815 TL |
177 | j = i; |
178 | } | |
1dbae815 | 179 | |
f9d41eef RB |
180 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
181 | sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); | |
182 | ||
183 | pr_info("%s", soc_name); | |
84a34344 | 184 | if ((omap_rev() >> 8) & 0x0f) |
f9d41eef | 185 | pr_info("%s", soc_rev); |
097c584c | 186 | pr_info("\n"); |
a8823143 TL |
187 | } |
188 | ||
50a01e64 VH |
189 | #define OMAP3_SHOW_FEATURE(feat) \ |
190 | if (omap3_has_ ##feat()) \ | |
191 | printk(#feat" "); | |
192 | ||
193 | static void __init omap3_cpuinfo(void) | |
194 | { | |
195 | const char *cpu_name; | |
196 | ||
197 | /* | |
198 | * OMAP3430 and OMAP3530 are assumed to be same. | |
199 | * | |
200 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
201 | * on available features. Upon detection, update the CPU id | |
202 | * and CPU class bits. | |
203 | */ | |
204 | if (cpu_is_omap3630()) { | |
205 | cpu_name = "OMAP3630"; | |
68a88b98 | 206 | } else if (soc_is_am35xx()) { |
50a01e64 VH |
207 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; |
208 | } else if (cpu_is_ti816x()) { | |
209 | cpu_name = "TI816X"; | |
971b8a9c | 210 | } else if (soc_is_am335x()) { |
50a01e64 | 211 | cpu_name = "AM335X"; |
c04bbaa4 AM |
212 | } else if (soc_is_am437x()) { |
213 | cpu_name = "AM437x"; | |
50a01e64 VH |
214 | } else if (cpu_is_ti814x()) { |
215 | cpu_name = "TI814X"; | |
216 | } else if (omap3_has_iva() && omap3_has_sgx()) { | |
217 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
218 | cpu_name = "OMAP3430/3530"; | |
219 | } else if (omap3_has_iva()) { | |
220 | cpu_name = "OMAP3525"; | |
221 | } else if (omap3_has_sgx()) { | |
222 | cpu_name = "OMAP3515"; | |
223 | } else { | |
224 | cpu_name = "OMAP3503"; | |
225 | } | |
226 | ||
f9d41eef RB |
227 | sprintf(soc_name, "%s", cpu_name); |
228 | ||
50a01e64 | 229 | /* Print verbose information */ |
f9d41eef | 230 | pr_info("%s %s (", soc_name, soc_rev); |
50a01e64 VH |
231 | |
232 | OMAP3_SHOW_FEATURE(l2cache); | |
233 | OMAP3_SHOW_FEATURE(iva); | |
234 | OMAP3_SHOW_FEATURE(sgx); | |
235 | OMAP3_SHOW_FEATURE(neon); | |
236 | OMAP3_SHOW_FEATURE(isp); | |
237 | OMAP3_SHOW_FEATURE(192mhz_clk); | |
238 | ||
239 | printk(")\n"); | |
240 | } | |
241 | ||
8384ce07 SP |
242 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
243 | if (((status & OMAP3_ ##feat## _MASK) \ | |
244 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 245 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
246 | } |
247 | ||
4de34f35 | 248 | void __init omap3xxx_check_features(void) |
8384ce07 SP |
249 | { |
250 | u32 status; | |
251 | ||
cc0170b2 | 252 | omap_features = 0; |
8384ce07 SP |
253 | |
254 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
255 | ||
256 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
257 | OMAP3_CHECK_FEATURE(status, IVA); | |
258 | OMAP3_CHECK_FEATURE(status, SGX); | |
259 | OMAP3_CHECK_FEATURE(status, NEON); | |
260 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 | 261 | if (cpu_is_omap3630()) |
cc0170b2 | 262 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
b02b9172 | 263 | if (cpu_is_omap3430() || cpu_is_omap3630()) |
cc0170b2 | 264 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
b02b9172 PW |
265 | if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
266 | omap_rev() == OMAP3430_REV_ES3_1_2) | |
267 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 268 | |
cc0170b2 | 269 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 270 | |
1ce02996 MG |
271 | /* |
272 | * am35x fixups: | |
273 | * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as | |
274 | * reserved and therefore return 0 when read. Unfortunately, | |
275 | * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to | |
276 | * mean that a feature is present even though it isn't so clear | |
277 | * the incorrectly set feature bits. | |
278 | */ | |
279 | if (soc_is_am35xx()) | |
280 | omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); | |
281 | ||
8384ce07 SP |
282 | /* |
283 | * TODO: Get additional info (where applicable) | |
284 | * e.g. Size of L2 cache. | |
285 | */ | |
4de34f35 VH |
286 | |
287 | omap3_cpuinfo(); | |
8384ce07 SP |
288 | } |
289 | ||
4de34f35 | 290 | void __init omap4xxx_check_features(void) |
cc0170b2 A |
291 | { |
292 | u32 si_type; | |
293 | ||
42a1cc9c IK |
294 | si_type = |
295 | (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; | |
cc0170b2 | 296 | |
42a1cc9c IK |
297 | if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) |
298 | omap_features = OMAP4_HAS_PERF_SILICON; | |
cc0170b2 A |
299 | } |
300 | ||
4de34f35 | 301 | void __init ti81xx_check_features(void) |
01001712 | 302 | { |
cc0170b2 | 303 | omap_features = OMAP3_HAS_NEON; |
4de34f35 | 304 | omap3_cpuinfo(); |
01001712 HP |
305 | } |
306 | ||
7bcad170 VH |
307 | void __init am33xx_check_features(void) |
308 | { | |
309 | u32 status; | |
310 | ||
311 | omap_features = OMAP3_HAS_NEON; | |
312 | ||
313 | status = omap_ctrl_readl(AM33XX_DEV_FEATURE); | |
314 | if (status & AM33XX_SGX_MASK) | |
315 | omap_features |= OMAP3_HAS_SGX; | |
316 | ||
317 | omap3_cpuinfo(); | |
318 | } | |
319 | ||
4de34f35 | 320 | void __init omap3xxx_check_revision(void) |
a8823143 | 321 | { |
f9d41eef | 322 | const char *cpu_rev; |
a8823143 TL |
323 | u32 cpuid, idcode; |
324 | u16 hawkeye; | |
325 | u8 rev; | |
a8823143 TL |
326 | |
327 | /* | |
328 | * We cannot access revision registers on ES1.0. | |
329 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
330 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
331 | */ | |
ac52e83f | 332 | cpuid = read_cpuid_id(); |
a8823143 | 333 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { |
84a34344 | 334 | omap_revision = OMAP3430_REV_ES1_0; |
50a01e64 | 335 | cpu_rev = "1.0"; |
048f4bd7 | 336 | return; |
a8823143 TL |
337 | } |
338 | ||
339 | /* | |
340 | * Detection for 34xx ES2.0 and above can be done with just | |
341 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
342 | * Note that rev does not map directly to our defined processor | |
343 | * revision numbers as ES1.0 uses value 0. | |
344 | */ | |
345 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
346 | hawkeye = (idcode >> 12) & 0xffff; | |
347 | rev = (idcode >> 28) & 0xff; | |
097c584c | 348 | |
2456a10f NM |
349 | switch (hawkeye) { |
350 | case 0xb7ae: | |
351 | /* Handle 34xx/35xx devices */ | |
a8823143 | 352 | switch (rev) { |
048f4bd7 SP |
353 | case 0: /* Take care of early samples */ |
354 | case 1: | |
84a34344 | 355 | omap_revision = OMAP3430_REV_ES2_0; |
50a01e64 | 356 | cpu_rev = "2.0"; |
a8823143 TL |
357 | break; |
358 | case 2: | |
84a34344 | 359 | omap_revision = OMAP3430_REV_ES2_1; |
50a01e64 | 360 | cpu_rev = "2.1"; |
a8823143 TL |
361 | break; |
362 | case 3: | |
84a34344 | 363 | omap_revision = OMAP3430_REV_ES3_0; |
50a01e64 | 364 | cpu_rev = "3.0"; |
a8823143 | 365 | break; |
187e688d | 366 | case 4: |
e9acb9b6 | 367 | omap_revision = OMAP3430_REV_ES3_1; |
50a01e64 | 368 | cpu_rev = "3.1"; |
e9acb9b6 TL |
369 | break; |
370 | case 7: | |
edeae658 | 371 | /* FALLTHROUGH */ |
a8823143 TL |
372 | default: |
373 | /* Use the latest known revision as default */ | |
e9acb9b6 | 374 | omap_revision = OMAP3430_REV_ES3_1_2; |
50a01e64 | 375 | cpu_rev = "3.1.2"; |
a8823143 | 376 | } |
2456a10f | 377 | break; |
4cac6018 | 378 | case 0xb868: |
1f1b0353 PW |
379 | /* |
380 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 381 | * |
1f1b0353 | 382 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
383 | * is identified later based on the features. |
384 | */ | |
9ed2ba7a PW |
385 | switch (rev) { |
386 | case 0: | |
68a88b98 | 387 | omap_revision = AM35XX_REV_ES1_0; |
50a01e64 | 388 | cpu_rev = "1.0"; |
9ed2ba7a PW |
389 | break; |
390 | case 1: | |
391 | /* FALLTHROUGH */ | |
392 | default: | |
68a88b98 | 393 | omap_revision = AM35XX_REV_ES1_1; |
50a01e64 | 394 | cpu_rev = "1.1"; |
9ed2ba7a | 395 | } |
4cac6018 | 396 | break; |
edeae658 | 397 | case 0xb891: |
b0a1a6ce | 398 | /* Handle 36xx devices */ |
b0a1a6ce AG |
399 | |
400 | switch(rev) { | |
401 | case 0: /* Take care of early samples */ | |
402 | omap_revision = OMAP3630_REV_ES1_0; | |
50a01e64 | 403 | cpu_rev = "1.0"; |
b0a1a6ce AG |
404 | break; |
405 | case 1: | |
406 | omap_revision = OMAP3630_REV_ES1_1; | |
50a01e64 | 407 | cpu_rev = "1.1"; |
b0a1a6ce AG |
408 | break; |
409 | case 2: | |
51ec811a | 410 | /* FALLTHROUGH */ |
b0a1a6ce | 411 | default: |
51ec811a | 412 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 413 | cpu_rev = "1.2"; |
b0a1a6ce | 414 | } |
77c0870c | 415 | break; |
01001712 | 416 | case 0xb81e: |
01001712 HP |
417 | switch (rev) { |
418 | case 0: | |
419 | omap_revision = TI8168_REV_ES1_0; | |
50a01e64 | 420 | cpu_rev = "1.0"; |
01001712 HP |
421 | break; |
422 | case 1: | |
51ec811a | 423 | omap_revision = TI8168_REV_ES1_1; |
50a01e64 | 424 | cpu_rev = "1.1"; |
3b32b7d6 | 425 | break; |
a5f93d9d AM |
426 | case 2: |
427 | omap_revision = TI8168_REV_ES2_0; | |
428 | cpu_rev = "2.0"; | |
429 | break; | |
430 | case 3: | |
431 | /* FALLTHROUGH */ | |
432 | default: | |
433 | omap_revision = TI8168_REV_ES2_1; | |
434 | cpu_rev = "2.1"; | |
01001712 HP |
435 | } |
436 | break; | |
1e6cb146 | 437 | case 0xb944: |
5af044f4 AC |
438 | switch (rev) { |
439 | case 0: | |
440 | omap_revision = AM335X_REV_ES1_0; | |
441 | cpu_rev = "1.0"; | |
442 | break; | |
443 | case 1: | |
5af044f4 AC |
444 | omap_revision = AM335X_REV_ES2_0; |
445 | cpu_rev = "2.0"; | |
446 | break; | |
d240ef30 VH |
447 | case 2: |
448 | /* FALLTHROUGH */ | |
449 | default: | |
450 | omap_revision = AM335X_REV_ES2_1; | |
451 | cpu_rev = "2.1"; | |
452 | break; | |
5af044f4 | 453 | } |
c2d13554 | 454 | break; |
c04bbaa4 AM |
455 | case 0xb98c: |
456 | omap_revision = AM437X_REV_ES1_0; | |
457 | cpu_rev = "1.0"; | |
458 | break; | |
4390f5b2 HP |
459 | case 0xb8f2: |
460 | switch (rev) { | |
461 | case 0: | |
462 | /* FALLTHROUGH */ | |
463 | case 1: | |
464 | omap_revision = TI8148_REV_ES1_0; | |
50a01e64 | 465 | cpu_rev = "1.0"; |
4390f5b2 HP |
466 | break; |
467 | case 2: | |
468 | omap_revision = TI8148_REV_ES2_0; | |
50a01e64 | 469 | cpu_rev = "2.0"; |
4390f5b2 HP |
470 | break; |
471 | case 3: | |
472 | /* FALLTHROUGH */ | |
473 | default: | |
474 | omap_revision = TI8148_REV_ES2_1; | |
50a01e64 | 475 | cpu_rev = "2.1"; |
4390f5b2 HP |
476 | break; |
477 | } | |
1e6cb146 | 478 | break; |
2456a10f | 479 | default: |
51ec811a | 480 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 481 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 482 | cpu_rev = "1.2"; |
51ec811a | 483 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
a8823143 | 484 | } |
f9d41eef | 485 | sprintf(soc_rev, "ES%s", cpu_rev); |
1dbae815 TL |
486 | } |
487 | ||
4de34f35 | 488 | void __init omap4xxx_check_revision(void) |
b570e0ec SS |
489 | { |
490 | u32 idcode; | |
491 | u16 hawkeye; | |
492 | u8 rev; | |
b570e0ec SS |
493 | |
494 | /* | |
495 | * The IC rev detection is done with hawkeye and rev. | |
496 | * Note that rev does not map directly to defined processor | |
497 | * revision numbers as ES1.0 uses value 0. | |
498 | */ | |
499 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
500 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 501 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 502 | |
ed6be0ba | 503 | /* |
fa54dccd | 504 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
505 | * Use ARM register to detect the correct ES version |
506 | */ | |
ec023e46 | 507 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ac52e83f | 508 | idcode = read_cpuid_id(); |
ed6be0ba SS |
509 | rev = (idcode & 0xf) - 1; |
510 | } | |
511 | ||
512 | switch (hawkeye) { | |
513 | case 0xb852: | |
514 | switch (rev) { | |
515 | case 0: | |
516 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
517 | break; |
518 | case 1: | |
e49c4d27 | 519 | default: |
ed6be0ba | 520 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
521 | } |
522 | break; | |
523 | case 0xb95c: | |
524 | switch (rev) { | |
525 | case 3: | |
526 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 527 | break; |
e49c4d27 | 528 | case 4: |
e49c4d27 | 529 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
530 | break; |
531 | case 6: | |
532 | default: | |
533 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
534 | } |
535 | break; | |
fa54dccd A |
536 | case 0xb94e: |
537 | switch (rev) { | |
538 | case 0: | |
fa54dccd | 539 | omap_revision = OMAP4460_REV_ES1_0; |
fa54dccd | 540 | break; |
33ee0db5 CL |
541 | case 2: |
542 | default: | |
543 | omap_revision = OMAP4460_REV_ES1_1; | |
544 | break; | |
fa54dccd A |
545 | } |
546 | break; | |
ec023e46 LI |
547 | case 0xb975: |
548 | switch (rev) { | |
549 | case 0: | |
550 | default: | |
551 | omap_revision = OMAP4470_REV_ES1_0; | |
552 | break; | |
553 | } | |
554 | break; | |
ed6be0ba | 555 | default: |
e49c4d27 | 556 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 557 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
558 | } |
559 | ||
f9d41eef RB |
560 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
561 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, | |
562 | (omap_rev() >> 8) & 0xf); | |
563 | pr_info("%s %s\n", soc_name, soc_rev); | |
b570e0ec SS |
564 | } |
565 | ||
b13e80a8 S |
566 | void __init omap5xxx_check_revision(void) |
567 | { | |
568 | u32 idcode; | |
569 | u16 hawkeye; | |
570 | u8 rev; | |
571 | ||
572 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
573 | hawkeye = (idcode >> 12) & 0xffff; | |
574 | rev = (idcode >> 28) & 0xff; | |
575 | switch (hawkeye) { | |
576 | case 0xb942: | |
577 | switch (rev) { | |
578 | case 0: | |
b13e80a8 | 579 | omap_revision = OMAP5430_REV_ES1_0; |
5a898a78 SS |
580 | break; |
581 | case 1: | |
582 | default: | |
583 | omap_revision = OMAP5430_REV_ES2_0; | |
b13e80a8 S |
584 | } |
585 | break; | |
586 | ||
587 | case 0xb998: | |
588 | switch (rev) { | |
589 | case 0: | |
b13e80a8 | 590 | omap_revision = OMAP5432_REV_ES1_0; |
5a898a78 SS |
591 | break; |
592 | case 1: | |
593 | default: | |
594 | omap_revision = OMAP5432_REV_ES2_0; | |
b13e80a8 S |
595 | } |
596 | break; | |
597 | ||
598 | default: | |
599 | /* Unknown default to latest silicon rev as default*/ | |
5a898a78 | 600 | omap_revision = OMAP5430_REV_ES2_0; |
b13e80a8 S |
601 | } |
602 | ||
f9d41eef RB |
603 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
604 | sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); | |
605 | ||
606 | pr_info("%s %s\n", soc_name, soc_rev); | |
b13e80a8 S |
607 | } |
608 | ||
a8823143 TL |
609 | /* |
610 | * Set up things for map_io and processor detection later on. Gets called | |
611 | * pretty much first thing from board init. For multi-omap, this gets | |
612 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
613 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
614 | * is done. | |
615 | */ | |
b6a4226c | 616 | void __init omap2_set_globals_tap(u32 class, void __iomem *tap) |
0e564848 | 617 | { |
b6a4226c PW |
618 | omap_revision = class; |
619 | tap_base = tap; | |
0e564848 | 620 | |
b6a4226c | 621 | /* XXX What is this intended to do? */ |
a8823143 | 622 | if (cpu_is_omap34xx()) |
0e564848 TL |
623 | tap_prod_id = 0x0210; |
624 | else | |
625 | tap_prod_id = 0x0208; | |
626 | } | |
6770b211 RB |
627 | |
628 | #ifdef CONFIG_SOC_BUS | |
629 | ||
630 | static const char const *omap_types[] = { | |
631 | [OMAP2_DEVICE_TYPE_TEST] = "TST", | |
632 | [OMAP2_DEVICE_TYPE_EMU] = "EMU", | |
633 | [OMAP2_DEVICE_TYPE_SEC] = "HS", | |
634 | [OMAP2_DEVICE_TYPE_GP] = "GP", | |
635 | [OMAP2_DEVICE_TYPE_BAD] = "BAD", | |
636 | }; | |
637 | ||
638 | static const char * __init omap_get_family(void) | |
639 | { | |
640 | if (cpu_is_omap24xx()) | |
641 | return kasprintf(GFP_KERNEL, "OMAP2"); | |
642 | else if (cpu_is_omap34xx()) | |
643 | return kasprintf(GFP_KERNEL, "OMAP3"); | |
644 | else if (cpu_is_omap44xx()) | |
645 | return kasprintf(GFP_KERNEL, "OMAP4"); | |
646 | else if (soc_is_omap54xx()) | |
647 | return kasprintf(GFP_KERNEL, "OMAP5"); | |
648 | else | |
649 | return kasprintf(GFP_KERNEL, "Unknown"); | |
650 | } | |
651 | ||
652 | static ssize_t omap_get_type(struct device *dev, | |
653 | struct device_attribute *attr, | |
654 | char *buf) | |
655 | { | |
656 | return sprintf(buf, "%s\n", omap_types[omap_type()]); | |
657 | } | |
658 | ||
659 | static struct device_attribute omap_soc_attr = | |
660 | __ATTR(type, S_IRUGO, omap_get_type, NULL); | |
661 | ||
662 | void __init omap_soc_device_init(void) | |
663 | { | |
664 | struct device *parent; | |
665 | struct soc_device *soc_dev; | |
666 | struct soc_device_attribute *soc_dev_attr; | |
667 | ||
668 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
669 | if (!soc_dev_attr) | |
670 | return; | |
671 | ||
672 | soc_dev_attr->machine = soc_name; | |
673 | soc_dev_attr->family = omap_get_family(); | |
674 | soc_dev_attr->revision = soc_rev; | |
675 | ||
676 | soc_dev = soc_device_register(soc_dev_attr); | |
b1dd11d6 | 677 | if (IS_ERR(soc_dev)) { |
6770b211 RB |
678 | kfree(soc_dev_attr); |
679 | return; | |
680 | } | |
681 | ||
682 | parent = soc_device_to_device(soc_dev); | |
b1dd11d6 | 683 | device_create_file(parent, &omap_soc_attr); |
6770b211 RB |
684 | } |
685 | #endif /* CONFIG_SOC_BUS */ |