[deliverable/linux.git] / arch / arm / mach-omap2 / id.c

/*
 * linux/arch/arm/mach-omap2/id.c
 *
 * OMAP2 CPU identification code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/cputype.h>

#include <plat/common.h>
#include <plat/control.h>
#include <plat/cpu.h>

static struct omap_chip_id omap_chip;
static unsigned int omap_revision;

u32 omap3_features;

unsigned int omap_rev(void)
{
	return omap_revision;
}
EXPORT_SYMBOL(omap_rev);

/**
 * omap_chip_is - test whether currently running OMAP matches a chip type
 * @oc: omap_chip_t to test against
 *
 * Test whether the currently-running OMAP chip matches the supplied
 * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
 */
int omap_chip_is(struct omap_chip_id oci)
{
	return (oci.oc & omap_chip.oc) ? 1 : 0;
}
EXPORT_SYMBOL(omap_chip_is);

int omap_type(void)
{
	u32 val = 0;

	if (cpu_is_omap24xx())
		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
	else if (cpu_is_omap34xx())
		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
	else {
		pr_err("Cannot detect omap type!\n");
		goto out;
	}

	val &= OMAP2_DEVICETYPE_MASK;
	val >>= 8;

out:
	return val;
}
EXPORT_SYMBOL(omap_type);


/*----------------------------------------------------------------------------*/

#define OMAP_TAP_IDCODE		0x0204
#define OMAP_TAP_DIE_ID_0	0x0218
#define OMAP_TAP_DIE_ID_1	0x021C
#define OMAP_TAP_DIE_ID_2	0x0220
#define OMAP_TAP_DIE_ID_3	0x0224

#define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))

struct omap_id {
	u16	hawkeye;	/* Silicon type (Hawkeye id) */
	u8	dev;		/* Device type from production_id reg */
	u32	type;		/* Combined type id copied to omap_revision */
};

/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
};

static void __iomem *tap_base;
static u16 tap_prod_id;

void __init omap24xx_check_revision(void)
{
	int i, j;
	u32 idcode, prod_id;
	u16 hawkeye;
	u8  dev_type, rev;

	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	prod_id = read_tap_reg(tap_prod_id);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0x0f;
	dev_type = (prod_id >> 16) & 0x0f;

	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
		 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_0));
	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_1),
		 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_2));
	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_3));
	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
		 prod_id, dev_type);

	/* Check hawkeye ids */
	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
		if (hawkeye == omap_ids[i].hawkeye)
			break;
	}

	if (i == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP CPU id\n");
		return;
	}

	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
		if (dev_type == omap_ids[j].dev)
			break;
	}

	if (j == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP device type. "
				"Handling it as OMAP%04x\n",
				omap_ids[i].type >> 16);
		j = i;
	}

	pr_info("OMAP%04x", omap_rev() >> 16);
	if ((omap_rev() >> 8) & 0x0f)
		pr_info("ES%x", (omap_rev() >> 12) & 0xf);
	pr_info("\n");
}

#define OMAP3_CHECK_FEATURE(status,feat)				\
	if (((status & OMAP3_ ##feat## _MASK) 				\
		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
		omap3_features |= OMAP3_HAS_ ##feat;			\
	}

void __init omap3_check_features(void)
{
	u32 status;

	omap3_features = 0;

	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);

	OMAP3_CHECK_FEATURE(status, L2CACHE);
	OMAP3_CHECK_FEATURE(status, IVA);
	OMAP3_CHECK_FEATURE(status, SGX);
	OMAP3_CHECK_FEATURE(status, NEON);
	OMAP3_CHECK_FEATURE(status, ISP);

	/*
	 * TODO: Get additional info (where applicable)
	 *       e.g. Size of L2 cache.
	 */
}

void __init omap3_check_revision(void)
{
	u32 cpuid, idcode;
	u16 hawkeye;
	u8 rev;
	char *rev_name = "ES1.0";

	/*
	 * We cannot access revision registers on ES1.0.
	 * If the processor type is Cortex-A8 and the revision is 0x0
	 * it means its Cortex r0p0 which is 3430 ES1.0.
	 */
	cpuid = read_cpuid(CPUID_ID);
	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
		omap_revision = OMAP3430_REV_ES1_0;
		goto out;
	}

	/*
	 * Detection for 34xx ES2.0 and above can be done with just
	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
	 * Note that rev does not map directly to our defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	if (hawkeye == 0xb7ae) {
		switch (rev) {
		case 0:
			omap_revision = OMAP3430_REV_ES2_0;
			rev_name = "ES2.0";
			break;
		case 2:
			omap_revision = OMAP3430_REV_ES2_1;
			rev_name = "ES2.1";
			break;
		case 3:
			omap_revision = OMAP3430_REV_ES3_0;
			rev_name = "ES3.0";
			break;
		case 4:
			omap_revision = OMAP3430_REV_ES3_1;
			rev_name = "ES3.1";
			break;
		default:
			/* Use the latest known revision as default */
			omap_revision = OMAP3430_REV_ES3_1;
			rev_name = "Unknown revision\n";
		}
	}

out:
	pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
}

#define OMAP3_SHOW_FEATURE(feat)		\
	if (omap3_has_ ##feat()) {		\
		pr_info (" - "#feat" : Y");	\
	} else {				\
		pr_info (" - "#feat" : N");	\
	}

void __init omap3_cpuinfo(void)
{
	OMAP3_SHOW_FEATURE(l2cache);
	OMAP3_SHOW_FEATURE(iva);
	OMAP3_SHOW_FEATURE(sgx);
	OMAP3_SHOW_FEATURE(neon);
	OMAP3_SHOW_FEATURE(isp);
}

/*
 * Try to detect the exact revision of the omap we're running on
 */
void __init omap2_check_revision(void)
{
	/*
	 * At this point we have an idea about the processor revision set
	 * earlier with omap2_set_globals_tap().
	 */
	if (cpu_is_omap24xx())
		omap24xx_check_revision();
	else if (cpu_is_omap34xx()) {
		omap3_check_features();
		omap3_check_revision();
		omap3_cpuinfo();
	}
	else if (cpu_is_omap44xx()) {
		printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
		return;
	} else
		pr_err("OMAP revision unknown, please fix!\n");

	/*
	 * OK, now we know the exact revision. Initialize omap_chip bits
	 * for powerdowmain and clockdomain code.
	 */
	if (cpu_is_omap243x()) {
		/* Currently only supports 2430ES2.1 and 2430-all */
		omap_chip.oc |= CHIP_IS_OMAP2430;
	} else if (cpu_is_omap242x()) {
		/* Currently only supports 2420ES2.1.1 and 2420-all */
		omap_chip.oc |= CHIP_IS_OMAP2420;
	} else if (cpu_is_omap343x()) {
		omap_chip.oc = CHIP_IS_OMAP3430;
		if (omap_rev() == OMAP3430_REV_ES1_0)
			omap_chip.oc |= CHIP_IS_OMAP3430ES1;
		else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
			 omap_rev() <= OMAP3430_REV_ES2_1)
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
		else if (omap_rev() == OMAP3430_REV_ES3_0)
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
		else if (omap_rev() == OMAP3430_REV_ES3_1)
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
	} else {
		pr_err("Uninitialized omap_chip, please fix!\n");
	}
}

/*
 * Set up things for map_io and processor detection later on. Gets called
 * pretty much first thing from board init. For multi-omap, this gets
 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 * detect the exact revision later on in omap2_detect_revision() once map_io
 * is done.
 */
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
{
	omap_revision = omap2_globals->class;
	tap_base = omap2_globals->tap;

	if (cpu_is_omap34xx())
		tap_prod_id = 0x0210;
	else
		tap_prod_id = 0x0208;
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/id.c
	3	*
	4	* OMAP2 CPU identification code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
44169075 SS	9	* Copyright (C) 2009 Texas Instruments
	10	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	11	*
1dbae815 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
1dbae815 TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
fced80c7	20	#include <linux/io.h>
1dbae815	21
0ba8b9b2	22	#include <asm/cputype.h>
1dbae815	23
ce491cf8 TL	24	#include <plat/common.h>
	25	#include <plat/control.h>
	26	#include <plat/cpu.h>
72d0f1c3	27
097c584c	28	static struct omap_chip_id omap_chip;
84a34344 LL	29	static unsigned int omap_revision;
84a34344 LL	30
8384ce07	31	u32 omap3_features;
84a34344 LL	32
	33	unsigned int omap_rev(void)
	34	{
	35	return omap_revision;
	36	}
	37	EXPORT_SYMBOL(omap_rev);
097c584c PW	38
	39	/**
	40	* omap_chip_is - test whether currently running OMAP matches a chip type
	41	* @oc: omap_chip_t to test against
	42	*
	43	* Test whether the currently-running OMAP chip matches the supplied
	44	* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
	45	*/
	46	int omap_chip_is(struct omap_chip_id oci)
	47	{
	48	return (oci.oc & omap_chip.oc) ? 1 : 0;
	49	}
	50	EXPORT_SYMBOL(omap_chip_is);
	51
8e25ad96 KH	52	int omap_type(void)
	53	{
	54	u32 val = 0;
	55
	56	if (cpu_is_omap24xx())
	57	val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
	58	else if (cpu_is_omap34xx())
	59	val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
	60	else {
	61	pr_err("Cannot detect omap type!\n");
	62	goto out;
	63	}
	64
	65	val &= OMAP2_DEVICETYPE_MASK;
	66	val >>= 8;
	67
	68	out:
	69	return val;
	70	}
	71	EXPORT_SYMBOL(omap_type);
	72
	73
a8823143	74	/----------------------------------------------------------------------------/
097c584c	75
a8823143 TL	76	#define OMAP_TAP_IDCODE 0x0204
	77	#define OMAP_TAP_DIE_ID_0 0x0218
	78	#define OMAP_TAP_DIE_ID_1 0x021C
	79	#define OMAP_TAP_DIE_ID_2 0x0220
	80	#define OMAP_TAP_DIE_ID_3 0x0224
097c584c	81
a8823143	82	#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
097c584c	83
a8823143 TL	84	struct omap_id {
	85	u16 hawkeye; /* Silicon type (Hawkeye id) */
	86	u8 dev; /* Device type from production_id reg */
84a34344	87	u32 type; /* Combined type id copied to omap_revision */
a8823143	88	};
097c584c	89
a8823143 TL	90	/* Register values to detect the OMAP version */
	91	static struct omap_id omap_ids[] __initdata = {
	92	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	93	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	94	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	95	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	96	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	97	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
	98	};
097c584c	99
a8823143 TL	100	static void __iomem *tap_base;
a8823143 TL	101	static u16 tap_prod_id;
1dbae815	102
5ba02dca	103	void __init omap24xx_check_revision(void)
1dbae815 TL	104	{
1dbae815 TL	105	int i, j;
a8823143	106	u32 idcode, prod_id;
1dbae815	107	u16 hawkeye;
a8823143	108	u8 dev_type, rev;
1dbae815 TL	109
1dbae815 TL	110	idcode = read_tap_reg(OMAP_TAP_IDCODE);
0e564848	111	prod_id = read_tap_reg(tap_prod_id);
1dbae815 TL	112	hawkeye = (idcode >> 12) & 0xffff;
	113	rev = (idcode >> 28) & 0x0f;
	114	dev_type = (prod_id >> 16) & 0x0f;
	115
097c584c PW	116	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
	117	idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	118	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
	119	read_tap_reg(OMAP_TAP_DIE_ID_0));
	120	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
	121	read_tap_reg(OMAP_TAP_DIE_ID_1),
	122	(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	123	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
	124	read_tap_reg(OMAP_TAP_DIE_ID_2));
	125	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
	126	read_tap_reg(OMAP_TAP_DIE_ID_3));
	127	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
	128	prod_id, dev_type);
	129
1dbae815 TL	130	/* Check hawkeye ids */
	131	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
	132	if (hawkeye == omap_ids[i].hawkeye)
	133	break;
	134	}
	135
	136	if (i == ARRAY_SIZE(omap_ids)) {
	137	printk(KERN_ERR "Unknown OMAP CPU id\n");
	138	return;
	139	}
	140
	141	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
	142	if (dev_type == omap_ids[j].dev)
	143	break;
	144	}
	145
	146	if (j == ARRAY_SIZE(omap_ids)) {
	147	printk(KERN_ERR "Unknown OMAP device type. "
	148	"Handling it as OMAP%04x\n",
	149	omap_ids[i].type >> 16);
	150	j = i;
	151	}
1dbae815	152
84a34344 LL	153	pr_info("OMAP%04x", omap_rev() >> 16);
	154	if ((omap_rev() >> 8) & 0x0f)
	155	pr_info("ES%x", (omap_rev() >> 12) & 0xf);
097c584c	156	pr_info("\n");
a8823143 TL	157	}
a8823143 TL	158
8384ce07 SP	159	#define OMAP3_CHECK_FEATURE(status,feat) \
	160	if (((status & OMAP3_ ##feat## _MASK) \
	161	>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
	162	omap3_features \|= OMAP3_HAS_ ##feat; \
	163	}
	164
	165	void __init omap3_check_features(void)
	166	{
	167	u32 status;
	168
	169	omap3_features = 0;
	170
	171	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
	172
	173	OMAP3_CHECK_FEATURE(status, L2CACHE);
	174	OMAP3_CHECK_FEATURE(status, IVA);
	175	OMAP3_CHECK_FEATURE(status, SGX);
	176	OMAP3_CHECK_FEATURE(status, NEON);
	177	OMAP3_CHECK_FEATURE(status, ISP);
	178
	179	/*
	180	* TODO: Get additional info (where applicable)
	181	* e.g. Size of L2 cache.
	182	*/
	183	}
	184
	185	void __init omap3_check_revision(void)
a8823143 TL	186	{
	187	u32 cpuid, idcode;
	188	u16 hawkeye;
	189	u8 rev;
	190	char *rev_name = "ES1.0";
	191
	192	/*
	193	* We cannot access revision registers on ES1.0.
	194	* If the processor type is Cortex-A8 and the revision is 0x0
	195	* it means its Cortex r0p0 which is 3430 ES1.0.
	196	*/
	197	cpuid = read_cpuid(CPUID_ID);
	198	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
84a34344	199	omap_revision = OMAP3430_REV_ES1_0;
a8823143 TL	200	goto out;
	201	}
	202
	203	/*
	204	* Detection for 34xx ES2.0 and above can be done with just
	205	* hawkeye and rev. See TRM 1.5.2 Device Identification.
	206	* Note that rev does not map directly to our defined processor
	207	* revision numbers as ES1.0 uses value 0.
	208	*/
	209	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	210	hawkeye = (idcode >> 12) & 0xffff;
	211	rev = (idcode >> 28) & 0xff;
097c584c	212
a8823143 TL	213	if (hawkeye == 0xb7ae) {
	214	switch (rev) {
	215	case 0:
84a34344	216	omap_revision = OMAP3430_REV_ES2_0;
a8823143 TL	217	rev_name = "ES2.0";
	218	break;
	219	case 2:
84a34344	220	omap_revision = OMAP3430_REV_ES2_1;
a8823143 TL	221	rev_name = "ES2.1";
	222	break;
	223	case 3:
84a34344	224	omap_revision = OMAP3430_REV_ES3_0;
a8823143 TL	225	rev_name = "ES3.0";
a8823143 TL	226	break;
187e688d TL	227	case 4:
	228	omap_revision = OMAP3430_REV_ES3_1;
	229	rev_name = "ES3.1";
	230	break;
a8823143 TL	231	default:
a8823143 TL	232	/* Use the latest known revision as default */
187e688d	233	omap_revision = OMAP3430_REV_ES3_1;
a8823143 TL	234	rev_name = "Unknown revision\n";
	235	}
	236	}
	237
	238	out:
84a34344	239	pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
1dbae815 TL	240	}
1dbae815 TL	241
8384ce07 SP	242	#define OMAP3_SHOW_FEATURE(feat) \
	243	if (omap3_has_ ##feat()) { \
	244	pr_info (" - "#feat" : Y"); \
	245	} else { \
	246	pr_info (" - "#feat" : N"); \
	247	}
	248
	249	void __init omap3_cpuinfo(void)
	250	{
	251	OMAP3_SHOW_FEATURE(l2cache);
	252	OMAP3_SHOW_FEATURE(iva);
	253	OMAP3_SHOW_FEATURE(sgx);
	254	OMAP3_SHOW_FEATURE(neon);
	255	OMAP3_SHOW_FEATURE(isp);
	256	}
	257
a8823143 TL	258	/*
	259	* Try to detect the exact revision of the omap we're running on
	260	*/
5ba02dca TL	261	void __init omap2_check_revision(void)
5ba02dca TL	262	{
a8823143 TL	263	/*
	264	* At this point we have an idea about the processor revision set
	265	* earlier with omap2_set_globals_tap().
	266	*/
	267	if (cpu_is_omap24xx())
	268	omap24xx_check_revision();
8384ce07 SP	269	else if (cpu_is_omap34xx()) {
	270	omap3_check_features();
	271	omap3_check_revision();
	272	omap3_cpuinfo();
	273	}
44169075 SS	274	else if (cpu_is_omap44xx()) {
	275	printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
	276	return;
	277	} else
a8823143 TL	278	pr_err("OMAP revision unknown, please fix!\n");
	279
	280	/*
	281	* OK, now we know the exact revision. Initialize omap_chip bits
	282	* for powerdowmain and clockdomain code.
	283	*/
	284	if (cpu_is_omap243x()) {
	285	/* Currently only supports 2430ES2.1 and 2430-all */
	286	omap_chip.oc \|= CHIP_IS_OMAP2430;
	287	} else if (cpu_is_omap242x()) {
	288	/* Currently only supports 2420ES2.1.1 and 2420-all */
	289	omap_chip.oc \|= CHIP_IS_OMAP2420;
	290	} else if (cpu_is_omap343x()) {
	291	omap_chip.oc = CHIP_IS_OMAP3430;
84a34344	292	if (omap_rev() == OMAP3430_REV_ES1_0)
a8823143	293	omap_chip.oc \|= CHIP_IS_OMAP3430ES1;
d41ad520 PW	294	else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
d41ad520 PW	295	omap_rev() <= OMAP3430_REV_ES2_1)
a8823143	296	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
d41ad520 PW	297	else if (omap_rev() == OMAP3430_REV_ES3_0)
	298	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_0;
	299	else if (omap_rev() == OMAP3430_REV_ES3_1)
	300	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
a8823143 TL	301	} else {
	302	pr_err("Uninitialized omap_chip, please fix!\n");
	303	}
5ba02dca TL	304	}
5ba02dca TL	305
a8823143 TL	306	/*
	307	* Set up things for map_io and processor detection later on. Gets called
	308	* pretty much first thing from board init. For multi-omap, this gets
	309	* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
	310	* detect the exact revision later on in omap2_detect_revision() once map_io
	311	* is done.
	312	*/
0e564848 TL	313	void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
0e564848 TL	314	{
84a34344	315	omap_revision = omap2_globals->class;
0e564848 TL	316	tap_base = omap2_globals->tap;
0e564848 TL	317
a8823143	318	if (cpu_is_omap34xx())
0e564848 TL	319	tap_prod_id = 0x0210;
	320	else
	321	tap_prod_id = 0x0208;
	322	}