Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
1dbae815 | 21 | |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
1dbae815 | 23 | |
4e65331c | 24 | #include "common.h" |
ce491cf8 | 25 | #include <plat/cpu.h> |
72d0f1c3 | 26 | |
2e130fc3 KRC |
27 | #include <mach/id.h> |
28 | ||
4814ced5 PW |
29 | #include "control.h" |
30 | ||
84a34344 LL |
31 | static unsigned int omap_revision; |
32 | ||
cc0170b2 | 33 | u32 omap_features; |
84a34344 LL |
34 | |
35 | unsigned int omap_rev(void) | |
36 | { | |
37 | return omap_revision; | |
38 | } | |
39 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 40 | |
8e25ad96 KH |
41 | int omap_type(void) |
42 | { | |
43 | u32 val = 0; | |
44 | ||
edeae658 | 45 | if (cpu_is_omap24xx()) { |
8e25ad96 | 46 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
edeae658 | 47 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 48 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 49 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 50 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
edeae658 | 51 | } else { |
8e25ad96 KH |
52 | pr_err("Cannot detect omap type!\n"); |
53 | goto out; | |
54 | } | |
55 | ||
56 | val &= OMAP2_DEVICETYPE_MASK; | |
57 | val >>= 8; | |
58 | ||
59 | out: | |
60 | return val; | |
61 | } | |
62 | EXPORT_SYMBOL(omap_type); | |
63 | ||
64 | ||
a8823143 | 65 | /*----------------------------------------------------------------------------*/ |
097c584c | 66 | |
a8823143 TL |
67 | #define OMAP_TAP_IDCODE 0x0204 |
68 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
69 | #define OMAP_TAP_DIE_ID_1 0x021C | |
70 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
71 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 72 | |
b235e007 AG |
73 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
74 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
75 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
76 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
77 | ||
a8823143 | 78 | #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) |
097c584c | 79 | |
a8823143 TL |
80 | struct omap_id { |
81 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
82 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 83 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 84 | }; |
097c584c | 85 | |
a8823143 TL |
86 | /* Register values to detect the OMAP version */ |
87 | static struct omap_id omap_ids[] __initdata = { | |
88 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
89 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
90 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
91 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
92 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
93 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
94 | }; | |
097c584c | 95 | |
a8823143 TL |
96 | static void __iomem *tap_base; |
97 | static u16 tap_prod_id; | |
1dbae815 | 98 | |
2e130fc3 KRC |
99 | void omap_get_die_id(struct omap_die_id *odi) |
100 | { | |
b235e007 AG |
101 | if (cpu_is_omap44xx()) { |
102 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); | |
103 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
104 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
105 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
106 | ||
107 | return; | |
108 | } | |
2e130fc3 KRC |
109 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
110 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
111 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
112 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
113 | } | |
114 | ||
5ebc0d52 | 115 | static void __init omap24xx_check_revision(void) |
1dbae815 TL |
116 | { |
117 | int i, j; | |
a8823143 | 118 | u32 idcode, prod_id; |
1dbae815 | 119 | u16 hawkeye; |
a8823143 | 120 | u8 dev_type, rev; |
c46732bb | 121 | struct omap_die_id odi; |
1dbae815 TL |
122 | |
123 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 124 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
125 | hawkeye = (idcode >> 12) & 0xffff; |
126 | rev = (idcode >> 28) & 0x0f; | |
127 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 128 | omap_get_die_id(&odi); |
1dbae815 | 129 | |
097c584c PW |
130 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
131 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 132 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 133 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
134 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
135 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
136 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
137 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
138 | prod_id, dev_type); | |
139 | ||
1dbae815 TL |
140 | /* Check hawkeye ids */ |
141 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
142 | if (hawkeye == omap_ids[i].hawkeye) | |
143 | break; | |
144 | } | |
145 | ||
146 | if (i == ARRAY_SIZE(omap_ids)) { | |
147 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
148 | return; | |
149 | } | |
150 | ||
151 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
152 | if (dev_type == omap_ids[j].dev) | |
153 | break; | |
154 | } | |
155 | ||
156 | if (j == ARRAY_SIZE(omap_ids)) { | |
157 | printk(KERN_ERR "Unknown OMAP device type. " | |
158 | "Handling it as OMAP%04x\n", | |
159 | omap_ids[i].type >> 16); | |
160 | j = i; | |
161 | } | |
1dbae815 | 162 | |
84a34344 LL |
163 | pr_info("OMAP%04x", omap_rev() >> 16); |
164 | if ((omap_rev() >> 8) & 0x0f) | |
165 | pr_info("ES%x", (omap_rev() >> 12) & 0xf); | |
097c584c | 166 | pr_info("\n"); |
a8823143 TL |
167 | } |
168 | ||
8384ce07 SP |
169 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
170 | if (((status & OMAP3_ ##feat## _MASK) \ | |
171 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 172 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
173 | } |
174 | ||
5ebc0d52 | 175 | static void __init omap3_check_features(void) |
8384ce07 SP |
176 | { |
177 | u32 status; | |
178 | ||
cc0170b2 | 179 | omap_features = 0; |
8384ce07 SP |
180 | |
181 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
182 | ||
183 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
184 | OMAP3_CHECK_FEATURE(status, IVA); | |
185 | OMAP3_CHECK_FEATURE(status, SGX); | |
186 | OMAP3_CHECK_FEATURE(status, NEON); | |
187 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 | 188 | if (cpu_is_omap3630()) |
cc0170b2 | 189 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
b02b9172 | 190 | if (cpu_is_omap3430() || cpu_is_omap3630()) |
cc0170b2 | 191 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
b02b9172 PW |
192 | if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
193 | omap_rev() == OMAP3430_REV_ES3_1_2) | |
194 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 195 | |
cc0170b2 | 196 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 197 | |
8384ce07 SP |
198 | /* |
199 | * TODO: Get additional info (where applicable) | |
200 | * e.g. Size of L2 cache. | |
201 | */ | |
202 | } | |
203 | ||
cc0170b2 A |
204 | static void __init omap4_check_features(void) |
205 | { | |
206 | u32 si_type; | |
207 | ||
208 | if (cpu_is_omap443x()) | |
209 | omap_features |= OMAP4_HAS_MPU_1GHZ; | |
210 | ||
211 | ||
212 | if (cpu_is_omap446x()) { | |
213 | si_type = | |
214 | read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1); | |
215 | switch ((si_type & (3 << 16)) >> 16) { | |
216 | case 2: | |
217 | /* High performance device */ | |
218 | omap_features |= OMAP4_HAS_MPU_1_5GHZ; | |
219 | break; | |
220 | case 1: | |
221 | default: | |
222 | /* Standard device */ | |
223 | omap_features |= OMAP4_HAS_MPU_1_2GHZ; | |
224 | break; | |
225 | } | |
226 | } | |
227 | } | |
228 | ||
a920360f | 229 | static void __init ti81xx_check_features(void) |
01001712 | 230 | { |
cc0170b2 | 231 | omap_features = OMAP3_HAS_NEON; |
01001712 HP |
232 | } |
233 | ||
3b32b7d6 | 234 | static void __init omap3_check_revision(const char **cpu_rev) |
a8823143 TL |
235 | { |
236 | u32 cpuid, idcode; | |
237 | u16 hawkeye; | |
238 | u8 rev; | |
a8823143 TL |
239 | |
240 | /* | |
241 | * We cannot access revision registers on ES1.0. | |
242 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
243 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
244 | */ | |
245 | cpuid = read_cpuid(CPUID_ID); | |
246 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { | |
84a34344 | 247 | omap_revision = OMAP3430_REV_ES1_0; |
3b32b7d6 | 248 | *cpu_rev = "1.0"; |
048f4bd7 | 249 | return; |
a8823143 TL |
250 | } |
251 | ||
252 | /* | |
253 | * Detection for 34xx ES2.0 and above can be done with just | |
254 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
255 | * Note that rev does not map directly to our defined processor | |
256 | * revision numbers as ES1.0 uses value 0. | |
257 | */ | |
258 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
259 | hawkeye = (idcode >> 12) & 0xffff; | |
260 | rev = (idcode >> 28) & 0xff; | |
097c584c | 261 | |
2456a10f NM |
262 | switch (hawkeye) { |
263 | case 0xb7ae: | |
264 | /* Handle 34xx/35xx devices */ | |
a8823143 | 265 | switch (rev) { |
048f4bd7 SP |
266 | case 0: /* Take care of early samples */ |
267 | case 1: | |
84a34344 | 268 | omap_revision = OMAP3430_REV_ES2_0; |
3b32b7d6 | 269 | *cpu_rev = "2.0"; |
a8823143 TL |
270 | break; |
271 | case 2: | |
84a34344 | 272 | omap_revision = OMAP3430_REV_ES2_1; |
3b32b7d6 | 273 | *cpu_rev = "2.1"; |
a8823143 TL |
274 | break; |
275 | case 3: | |
84a34344 | 276 | omap_revision = OMAP3430_REV_ES3_0; |
3b32b7d6 | 277 | *cpu_rev = "3.0"; |
a8823143 | 278 | break; |
187e688d | 279 | case 4: |
e9acb9b6 | 280 | omap_revision = OMAP3430_REV_ES3_1; |
3b32b7d6 | 281 | *cpu_rev = "3.1"; |
e9acb9b6 TL |
282 | break; |
283 | case 7: | |
edeae658 | 284 | /* FALLTHROUGH */ |
a8823143 TL |
285 | default: |
286 | /* Use the latest known revision as default */ | |
e9acb9b6 | 287 | omap_revision = OMAP3430_REV_ES3_1_2; |
3b32b7d6 | 288 | *cpu_rev = "3.1.2"; |
a8823143 | 289 | } |
2456a10f | 290 | break; |
4cac6018 | 291 | case 0xb868: |
1f1b0353 PW |
292 | /* |
293 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 294 | * |
1f1b0353 | 295 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
296 | * is identified later based on the features. |
297 | */ | |
9ed2ba7a PW |
298 | switch (rev) { |
299 | case 0: | |
300 | omap_revision = OMAP3517_REV_ES1_0; | |
3b32b7d6 | 301 | *cpu_rev = "1.0"; |
9ed2ba7a PW |
302 | break; |
303 | case 1: | |
304 | /* FALLTHROUGH */ | |
305 | default: | |
306 | omap_revision = OMAP3517_REV_ES1_1; | |
3b32b7d6 | 307 | *cpu_rev = "1.1"; |
9ed2ba7a | 308 | } |
4cac6018 | 309 | break; |
edeae658 | 310 | case 0xb891: |
b0a1a6ce | 311 | /* Handle 36xx devices */ |
b0a1a6ce AG |
312 | |
313 | switch(rev) { | |
314 | case 0: /* Take care of early samples */ | |
315 | omap_revision = OMAP3630_REV_ES1_0; | |
3b32b7d6 | 316 | *cpu_rev = "1.0"; |
b0a1a6ce AG |
317 | break; |
318 | case 1: | |
319 | omap_revision = OMAP3630_REV_ES1_1; | |
3b32b7d6 | 320 | *cpu_rev = "1.1"; |
b0a1a6ce AG |
321 | break; |
322 | case 2: | |
51ec811a | 323 | /* FALLTHROUGH */ |
b0a1a6ce | 324 | default: |
51ec811a | 325 | omap_revision = OMAP3630_REV_ES1_2; |
3b32b7d6 | 326 | *cpu_rev = "1.2"; |
b0a1a6ce | 327 | } |
77c0870c | 328 | break; |
01001712 | 329 | case 0xb81e: |
01001712 HP |
330 | switch (rev) { |
331 | case 0: | |
332 | omap_revision = TI8168_REV_ES1_0; | |
3b32b7d6 | 333 | *cpu_rev = "1.0"; |
01001712 HP |
334 | break; |
335 | case 1: | |
51ec811a | 336 | /* FALLTHROUGH */ |
01001712 | 337 | default: |
51ec811a | 338 | omap_revision = TI8168_REV_ES1_1; |
3b32b7d6 PW |
339 | *cpu_rev = "1.1"; |
340 | break; | |
01001712 HP |
341 | } |
342 | break; | |
1e6cb146 AM |
343 | case 0xb944: |
344 | omap_revision = AM335X_REV_ES1_0; | |
345 | *cpu_rev = "1.0"; | |
346 | break; | |
2456a10f | 347 | default: |
51ec811a | 348 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 349 | omap_revision = OMAP3630_REV_ES1_2; |
3b32b7d6 | 350 | *cpu_rev = "1.2"; |
51ec811a | 351 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
a8823143 | 352 | } |
1dbae815 TL |
353 | } |
354 | ||
5ebc0d52 | 355 | static void __init omap4_check_revision(void) |
b570e0ec SS |
356 | { |
357 | u32 idcode; | |
358 | u16 hawkeye; | |
359 | u8 rev; | |
b570e0ec SS |
360 | |
361 | /* | |
362 | * The IC rev detection is done with hawkeye and rev. | |
363 | * Note that rev does not map directly to defined processor | |
364 | * revision numbers as ES1.0 uses value 0. | |
365 | */ | |
366 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
367 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 368 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 369 | |
ed6be0ba | 370 | /* |
fa54dccd | 371 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
372 | * Use ARM register to detect the correct ES version |
373 | */ | |
ec023e46 | 374 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ed6be0ba SS |
375 | idcode = read_cpuid(CPUID_ID); |
376 | rev = (idcode & 0xf) - 1; | |
377 | } | |
378 | ||
379 | switch (hawkeye) { | |
380 | case 0xb852: | |
381 | switch (rev) { | |
382 | case 0: | |
383 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
384 | break; |
385 | case 1: | |
e49c4d27 | 386 | default: |
ed6be0ba | 387 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
388 | } |
389 | break; | |
390 | case 0xb95c: | |
391 | switch (rev) { | |
392 | case 3: | |
393 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 394 | break; |
e49c4d27 | 395 | case 4: |
e49c4d27 | 396 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
397 | break; |
398 | case 6: | |
399 | default: | |
400 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
401 | } |
402 | break; | |
fa54dccd A |
403 | case 0xb94e: |
404 | switch (rev) { | |
405 | case 0: | |
406 | default: | |
407 | omap_revision = OMAP4460_REV_ES1_0; | |
fa54dccd A |
408 | break; |
409 | } | |
410 | break; | |
ec023e46 LI |
411 | case 0xb975: |
412 | switch (rev) { | |
413 | case 0: | |
414 | default: | |
415 | omap_revision = OMAP4470_REV_ES1_0; | |
416 | break; | |
417 | } | |
418 | break; | |
ed6be0ba | 419 | default: |
e49c4d27 | 420 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 421 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
422 | } |
423 | ||
e49c4d27 NK |
424 | pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, |
425 | ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); | |
b570e0ec SS |
426 | } |
427 | ||
8384ce07 | 428 | #define OMAP3_SHOW_FEATURE(feat) \ |
cedf900d KH |
429 | if (omap3_has_ ##feat()) \ |
430 | printk(#feat" "); | |
8384ce07 | 431 | |
3b32b7d6 | 432 | static void __init omap3_cpuinfo(const char *cpu_rev) |
8384ce07 | 433 | { |
3b32b7d6 | 434 | const char *cpu_name; |
048f4bd7 | 435 | |
91d92d6c PW |
436 | /* |
437 | * OMAP3430 and OMAP3530 are assumed to be same. | |
048f4bd7 SP |
438 | * |
439 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
440 | * on available features. Upon detection, update the CPU id | |
441 | * and CPU class bits. | |
442 | */ | |
edeae658 | 443 | if (cpu_is_omap3630()) { |
91d92d6c | 444 | cpu_name = "OMAP3630"; |
1f1b0353 | 445 | } else if (cpu_is_omap3517()) { |
91d92d6c PW |
446 | /* AM35xx devices */ |
447 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; | |
01001712 | 448 | } else if (cpu_is_ti816x()) { |
91d92d6c | 449 | cpu_name = "TI816X"; |
1e6cb146 AM |
450 | } else if (cpu_is_am335x()) { |
451 | cpu_name = "AM335X"; | |
edeae658 FB |
452 | } else if (omap3_has_iva() && omap3_has_sgx()) { |
453 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
91d92d6c | 454 | cpu_name = "OMAP3430/3530"; |
0712fb39 | 455 | } else if (omap3_has_iva()) { |
91d92d6c | 456 | cpu_name = "OMAP3525"; |
0712fb39 | 457 | } else if (omap3_has_sgx()) { |
91d92d6c | 458 | cpu_name = "OMAP3515"; |
edeae658 | 459 | } else { |
91d92d6c | 460 | cpu_name = "OMAP3503"; |
048f4bd7 SP |
461 | } |
462 | ||
edeae658 | 463 | /* Print verbose information */ |
cedf900d | 464 | pr_info("%s ES%s (", cpu_name, cpu_rev); |
048f4bd7 | 465 | |
8384ce07 SP |
466 | OMAP3_SHOW_FEATURE(l2cache); |
467 | OMAP3_SHOW_FEATURE(iva); | |
468 | OMAP3_SHOW_FEATURE(sgx); | |
469 | OMAP3_SHOW_FEATURE(neon); | |
470 | OMAP3_SHOW_FEATURE(isp); | |
7356f0b2 | 471 | OMAP3_SHOW_FEATURE(192mhz_clk); |
cedf900d KH |
472 | |
473 | printk(")\n"); | |
8384ce07 SP |
474 | } |
475 | ||
a8823143 TL |
476 | /* |
477 | * Try to detect the exact revision of the omap we're running on | |
478 | */ | |
5ba02dca TL |
479 | void __init omap2_check_revision(void) |
480 | { | |
3b32b7d6 PW |
481 | const char *cpu_rev; |
482 | ||
a8823143 TL |
483 | /* |
484 | * At this point we have an idea about the processor revision set | |
485 | * earlier with omap2_set_globals_tap(). | |
486 | */ | |
edeae658 | 487 | if (cpu_is_omap24xx()) { |
a8823143 | 488 | omap24xx_check_revision(); |
edeae658 | 489 | } else if (cpu_is_omap34xx()) { |
3b32b7d6 | 490 | omap3_check_revision(&cpu_rev); |
01001712 | 491 | |
a920360f HP |
492 | /* TI81XX doesn't have feature register */ |
493 | if (!cpu_is_ti81xx()) | |
01001712 HP |
494 | omap3_check_features(); |
495 | else | |
a920360f | 496 | ti81xx_check_features(); |
01001712 | 497 | |
3b32b7d6 | 498 | omap3_cpuinfo(cpu_rev); |
e9acb9b6 | 499 | return; |
edeae658 | 500 | } else if (cpu_is_omap44xx()) { |
b570e0ec | 501 | omap4_check_revision(); |
cc0170b2 | 502 | omap4_check_features(); |
44169075 | 503 | return; |
edeae658 | 504 | } else { |
a8823143 | 505 | pr_err("OMAP revision unknown, please fix!\n"); |
edeae658 | 506 | } |
5ba02dca TL |
507 | } |
508 | ||
a8823143 TL |
509 | /* |
510 | * Set up things for map_io and processor detection later on. Gets called | |
511 | * pretty much first thing from board init. For multi-omap, this gets | |
512 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
513 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
514 | * is done. | |
515 | */ | |
0e564848 TL |
516 | void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) |
517 | { | |
84a34344 | 518 | omap_revision = omap2_globals->class; |
0e564848 TL |
519 | tap_base = omap2_globals->tap; |
520 | ||
a8823143 | 521 | if (cpu_is_omap34xx()) |
0e564848 TL |
522 | tap_prod_id = 0x0210; |
523 | else | |
524 | tap_prod_id = 0x0208; | |
525 | } |