Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
1dbae815 | 21 | |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
1dbae815 | 23 | |
4e65331c | 24 | #include "common.h" |
ce491cf8 | 25 | #include <plat/cpu.h> |
72d0f1c3 | 26 | |
2e130fc3 KRC |
27 | #include <mach/id.h> |
28 | ||
4814ced5 PW |
29 | #include "control.h" |
30 | ||
84a34344 | 31 | static unsigned int omap_revision; |
50a01e64 | 32 | static const char *cpu_rev; |
cc0170b2 | 33 | u32 omap_features; |
84a34344 LL |
34 | |
35 | unsigned int omap_rev(void) | |
36 | { | |
37 | return omap_revision; | |
38 | } | |
39 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 40 | |
8e25ad96 KH |
41 | int omap_type(void) |
42 | { | |
43 | u32 val = 0; | |
44 | ||
edeae658 | 45 | if (cpu_is_omap24xx()) { |
8e25ad96 | 46 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
fb3cfb1f AM |
47 | } else if (cpu_is_am33xx()) { |
48 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); | |
edeae658 | 49 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 50 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 51 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 52 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
edeae658 | 53 | } else { |
8e25ad96 KH |
54 | pr_err("Cannot detect omap type!\n"); |
55 | goto out; | |
56 | } | |
57 | ||
58 | val &= OMAP2_DEVICETYPE_MASK; | |
59 | val >>= 8; | |
60 | ||
61 | out: | |
62 | return val; | |
63 | } | |
64 | EXPORT_SYMBOL(omap_type); | |
65 | ||
66 | ||
a8823143 | 67 | /*----------------------------------------------------------------------------*/ |
097c584c | 68 | |
a8823143 TL |
69 | #define OMAP_TAP_IDCODE 0x0204 |
70 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
71 | #define OMAP_TAP_DIE_ID_1 0x021C | |
72 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
73 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 74 | |
b235e007 AG |
75 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
76 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
77 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
78 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
79 | ||
a8823143 | 80 | #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) |
097c584c | 81 | |
a8823143 TL |
82 | struct omap_id { |
83 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
84 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 85 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 86 | }; |
097c584c | 87 | |
a8823143 TL |
88 | /* Register values to detect the OMAP version */ |
89 | static struct omap_id omap_ids[] __initdata = { | |
90 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
91 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
92 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
93 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
94 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
95 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
96 | }; | |
097c584c | 97 | |
a8823143 TL |
98 | static void __iomem *tap_base; |
99 | static u16 tap_prod_id; | |
1dbae815 | 100 | |
2e130fc3 KRC |
101 | void omap_get_die_id(struct omap_die_id *odi) |
102 | { | |
b235e007 AG |
103 | if (cpu_is_omap44xx()) { |
104 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); | |
105 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
106 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
107 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
108 | ||
109 | return; | |
110 | } | |
2e130fc3 KRC |
111 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
112 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
113 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
114 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
115 | } | |
116 | ||
4de34f35 | 117 | void __init omap2xxx_check_revision(void) |
1dbae815 TL |
118 | { |
119 | int i, j; | |
a8823143 | 120 | u32 idcode, prod_id; |
1dbae815 | 121 | u16 hawkeye; |
a8823143 | 122 | u8 dev_type, rev; |
c46732bb | 123 | struct omap_die_id odi; |
1dbae815 TL |
124 | |
125 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 126 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
127 | hawkeye = (idcode >> 12) & 0xffff; |
128 | rev = (idcode >> 28) & 0x0f; | |
129 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 130 | omap_get_die_id(&odi); |
1dbae815 | 131 | |
097c584c PW |
132 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
133 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 134 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 135 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
136 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
137 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
138 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
139 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
140 | prod_id, dev_type); | |
141 | ||
1dbae815 TL |
142 | /* Check hawkeye ids */ |
143 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
144 | if (hawkeye == omap_ids[i].hawkeye) | |
145 | break; | |
146 | } | |
147 | ||
148 | if (i == ARRAY_SIZE(omap_ids)) { | |
149 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
150 | return; | |
151 | } | |
152 | ||
153 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
154 | if (dev_type == omap_ids[j].dev) | |
155 | break; | |
156 | } | |
157 | ||
158 | if (j == ARRAY_SIZE(omap_ids)) { | |
159 | printk(KERN_ERR "Unknown OMAP device type. " | |
160 | "Handling it as OMAP%04x\n", | |
161 | omap_ids[i].type >> 16); | |
162 | j = i; | |
163 | } | |
1dbae815 | 164 | |
84a34344 LL |
165 | pr_info("OMAP%04x", omap_rev() >> 16); |
166 | if ((omap_rev() >> 8) & 0x0f) | |
167 | pr_info("ES%x", (omap_rev() >> 12) & 0xf); | |
097c584c | 168 | pr_info("\n"); |
a8823143 TL |
169 | } |
170 | ||
50a01e64 VH |
171 | #define OMAP3_SHOW_FEATURE(feat) \ |
172 | if (omap3_has_ ##feat()) \ | |
173 | printk(#feat" "); | |
174 | ||
175 | static void __init omap3_cpuinfo(void) | |
176 | { | |
177 | const char *cpu_name; | |
178 | ||
179 | /* | |
180 | * OMAP3430 and OMAP3530 are assumed to be same. | |
181 | * | |
182 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
183 | * on available features. Upon detection, update the CPU id | |
184 | * and CPU class bits. | |
185 | */ | |
186 | if (cpu_is_omap3630()) { | |
187 | cpu_name = "OMAP3630"; | |
68a88b98 | 188 | } else if (soc_is_am35xx()) { |
50a01e64 VH |
189 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; |
190 | } else if (cpu_is_ti816x()) { | |
191 | cpu_name = "TI816X"; | |
192 | } else if (cpu_is_am335x()) { | |
193 | cpu_name = "AM335X"; | |
194 | } else if (cpu_is_ti814x()) { | |
195 | cpu_name = "TI814X"; | |
196 | } else if (omap3_has_iva() && omap3_has_sgx()) { | |
197 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
198 | cpu_name = "OMAP3430/3530"; | |
199 | } else if (omap3_has_iva()) { | |
200 | cpu_name = "OMAP3525"; | |
201 | } else if (omap3_has_sgx()) { | |
202 | cpu_name = "OMAP3515"; | |
203 | } else { | |
204 | cpu_name = "OMAP3503"; | |
205 | } | |
206 | ||
207 | /* Print verbose information */ | |
208 | pr_info("%s ES%s (", cpu_name, cpu_rev); | |
209 | ||
210 | OMAP3_SHOW_FEATURE(l2cache); | |
211 | OMAP3_SHOW_FEATURE(iva); | |
212 | OMAP3_SHOW_FEATURE(sgx); | |
213 | OMAP3_SHOW_FEATURE(neon); | |
214 | OMAP3_SHOW_FEATURE(isp); | |
215 | OMAP3_SHOW_FEATURE(192mhz_clk); | |
216 | ||
217 | printk(")\n"); | |
218 | } | |
219 | ||
8384ce07 SP |
220 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
221 | if (((status & OMAP3_ ##feat## _MASK) \ | |
222 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 223 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
224 | } |
225 | ||
4de34f35 | 226 | void __init omap3xxx_check_features(void) |
8384ce07 SP |
227 | { |
228 | u32 status; | |
229 | ||
cc0170b2 | 230 | omap_features = 0; |
8384ce07 SP |
231 | |
232 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
233 | ||
234 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
235 | OMAP3_CHECK_FEATURE(status, IVA); | |
236 | OMAP3_CHECK_FEATURE(status, SGX); | |
237 | OMAP3_CHECK_FEATURE(status, NEON); | |
238 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 | 239 | if (cpu_is_omap3630()) |
cc0170b2 | 240 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
b02b9172 | 241 | if (cpu_is_omap3430() || cpu_is_omap3630()) |
cc0170b2 | 242 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
b02b9172 PW |
243 | if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
244 | omap_rev() == OMAP3430_REV_ES3_1_2) | |
245 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 246 | |
cc0170b2 | 247 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 248 | |
1ce02996 MG |
249 | /* |
250 | * am35x fixups: | |
251 | * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as | |
252 | * reserved and therefore return 0 when read. Unfortunately, | |
253 | * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to | |
254 | * mean that a feature is present even though it isn't so clear | |
255 | * the incorrectly set feature bits. | |
256 | */ | |
257 | if (soc_is_am35xx()) | |
258 | omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); | |
259 | ||
8384ce07 SP |
260 | /* |
261 | * TODO: Get additional info (where applicable) | |
262 | * e.g. Size of L2 cache. | |
263 | */ | |
4de34f35 VH |
264 | |
265 | omap3_cpuinfo(); | |
8384ce07 SP |
266 | } |
267 | ||
4de34f35 | 268 | void __init omap4xxx_check_features(void) |
cc0170b2 A |
269 | { |
270 | u32 si_type; | |
271 | ||
272 | if (cpu_is_omap443x()) | |
273 | omap_features |= OMAP4_HAS_MPU_1GHZ; | |
274 | ||
275 | ||
276 | if (cpu_is_omap446x()) { | |
277 | si_type = | |
278 | read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1); | |
279 | switch ((si_type & (3 << 16)) >> 16) { | |
280 | case 2: | |
281 | /* High performance device */ | |
282 | omap_features |= OMAP4_HAS_MPU_1_5GHZ; | |
283 | break; | |
284 | case 1: | |
285 | default: | |
286 | /* Standard device */ | |
287 | omap_features |= OMAP4_HAS_MPU_1_2GHZ; | |
288 | break; | |
289 | } | |
290 | } | |
291 | } | |
292 | ||
4de34f35 | 293 | void __init ti81xx_check_features(void) |
01001712 | 294 | { |
cc0170b2 | 295 | omap_features = OMAP3_HAS_NEON; |
4de34f35 | 296 | omap3_cpuinfo(); |
01001712 HP |
297 | } |
298 | ||
4de34f35 | 299 | void __init omap3xxx_check_revision(void) |
a8823143 TL |
300 | { |
301 | u32 cpuid, idcode; | |
302 | u16 hawkeye; | |
303 | u8 rev; | |
a8823143 TL |
304 | |
305 | /* | |
306 | * We cannot access revision registers on ES1.0. | |
307 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
308 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
309 | */ | |
310 | cpuid = read_cpuid(CPUID_ID); | |
311 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { | |
84a34344 | 312 | omap_revision = OMAP3430_REV_ES1_0; |
50a01e64 | 313 | cpu_rev = "1.0"; |
048f4bd7 | 314 | return; |
a8823143 TL |
315 | } |
316 | ||
317 | /* | |
318 | * Detection for 34xx ES2.0 and above can be done with just | |
319 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
320 | * Note that rev does not map directly to our defined processor | |
321 | * revision numbers as ES1.0 uses value 0. | |
322 | */ | |
323 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
324 | hawkeye = (idcode >> 12) & 0xffff; | |
325 | rev = (idcode >> 28) & 0xff; | |
097c584c | 326 | |
2456a10f NM |
327 | switch (hawkeye) { |
328 | case 0xb7ae: | |
329 | /* Handle 34xx/35xx devices */ | |
a8823143 | 330 | switch (rev) { |
048f4bd7 SP |
331 | case 0: /* Take care of early samples */ |
332 | case 1: | |
84a34344 | 333 | omap_revision = OMAP3430_REV_ES2_0; |
50a01e64 | 334 | cpu_rev = "2.0"; |
a8823143 TL |
335 | break; |
336 | case 2: | |
84a34344 | 337 | omap_revision = OMAP3430_REV_ES2_1; |
50a01e64 | 338 | cpu_rev = "2.1"; |
a8823143 TL |
339 | break; |
340 | case 3: | |
84a34344 | 341 | omap_revision = OMAP3430_REV_ES3_0; |
50a01e64 | 342 | cpu_rev = "3.0"; |
a8823143 | 343 | break; |
187e688d | 344 | case 4: |
e9acb9b6 | 345 | omap_revision = OMAP3430_REV_ES3_1; |
50a01e64 | 346 | cpu_rev = "3.1"; |
e9acb9b6 TL |
347 | break; |
348 | case 7: | |
edeae658 | 349 | /* FALLTHROUGH */ |
a8823143 TL |
350 | default: |
351 | /* Use the latest known revision as default */ | |
e9acb9b6 | 352 | omap_revision = OMAP3430_REV_ES3_1_2; |
50a01e64 | 353 | cpu_rev = "3.1.2"; |
a8823143 | 354 | } |
2456a10f | 355 | break; |
4cac6018 | 356 | case 0xb868: |
1f1b0353 PW |
357 | /* |
358 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 359 | * |
1f1b0353 | 360 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
361 | * is identified later based on the features. |
362 | */ | |
9ed2ba7a PW |
363 | switch (rev) { |
364 | case 0: | |
68a88b98 | 365 | omap_revision = AM35XX_REV_ES1_0; |
50a01e64 | 366 | cpu_rev = "1.0"; |
9ed2ba7a PW |
367 | break; |
368 | case 1: | |
369 | /* FALLTHROUGH */ | |
370 | default: | |
68a88b98 | 371 | omap_revision = AM35XX_REV_ES1_1; |
50a01e64 | 372 | cpu_rev = "1.1"; |
9ed2ba7a | 373 | } |
4cac6018 | 374 | break; |
edeae658 | 375 | case 0xb891: |
b0a1a6ce | 376 | /* Handle 36xx devices */ |
b0a1a6ce AG |
377 | |
378 | switch(rev) { | |
379 | case 0: /* Take care of early samples */ | |
380 | omap_revision = OMAP3630_REV_ES1_0; | |
50a01e64 | 381 | cpu_rev = "1.0"; |
b0a1a6ce AG |
382 | break; |
383 | case 1: | |
384 | omap_revision = OMAP3630_REV_ES1_1; | |
50a01e64 | 385 | cpu_rev = "1.1"; |
b0a1a6ce AG |
386 | break; |
387 | case 2: | |
51ec811a | 388 | /* FALLTHROUGH */ |
b0a1a6ce | 389 | default: |
51ec811a | 390 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 391 | cpu_rev = "1.2"; |
b0a1a6ce | 392 | } |
77c0870c | 393 | break; |
01001712 | 394 | case 0xb81e: |
01001712 HP |
395 | switch (rev) { |
396 | case 0: | |
397 | omap_revision = TI8168_REV_ES1_0; | |
50a01e64 | 398 | cpu_rev = "1.0"; |
01001712 HP |
399 | break; |
400 | case 1: | |
51ec811a | 401 | /* FALLTHROUGH */ |
01001712 | 402 | default: |
51ec811a | 403 | omap_revision = TI8168_REV_ES1_1; |
50a01e64 | 404 | cpu_rev = "1.1"; |
3b32b7d6 | 405 | break; |
01001712 HP |
406 | } |
407 | break; | |
1e6cb146 AM |
408 | case 0xb944: |
409 | omap_revision = AM335X_REV_ES1_0; | |
50a01e64 | 410 | cpu_rev = "1.0"; |
c2d13554 | 411 | break; |
4390f5b2 HP |
412 | case 0xb8f2: |
413 | switch (rev) { | |
414 | case 0: | |
415 | /* FALLTHROUGH */ | |
416 | case 1: | |
417 | omap_revision = TI8148_REV_ES1_0; | |
50a01e64 | 418 | cpu_rev = "1.0"; |
4390f5b2 HP |
419 | break; |
420 | case 2: | |
421 | omap_revision = TI8148_REV_ES2_0; | |
50a01e64 | 422 | cpu_rev = "2.0"; |
4390f5b2 HP |
423 | break; |
424 | case 3: | |
425 | /* FALLTHROUGH */ | |
426 | default: | |
427 | omap_revision = TI8148_REV_ES2_1; | |
50a01e64 | 428 | cpu_rev = "2.1"; |
4390f5b2 HP |
429 | break; |
430 | } | |
1e6cb146 | 431 | break; |
2456a10f | 432 | default: |
51ec811a | 433 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 434 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 435 | cpu_rev = "1.2"; |
51ec811a | 436 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
a8823143 | 437 | } |
1dbae815 TL |
438 | } |
439 | ||
4de34f35 | 440 | void __init omap4xxx_check_revision(void) |
b570e0ec SS |
441 | { |
442 | u32 idcode; | |
443 | u16 hawkeye; | |
444 | u8 rev; | |
b570e0ec SS |
445 | |
446 | /* | |
447 | * The IC rev detection is done with hawkeye and rev. | |
448 | * Note that rev does not map directly to defined processor | |
449 | * revision numbers as ES1.0 uses value 0. | |
450 | */ | |
451 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
452 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 453 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 454 | |
ed6be0ba | 455 | /* |
fa54dccd | 456 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
457 | * Use ARM register to detect the correct ES version |
458 | */ | |
ec023e46 | 459 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ed6be0ba SS |
460 | idcode = read_cpuid(CPUID_ID); |
461 | rev = (idcode & 0xf) - 1; | |
462 | } | |
463 | ||
464 | switch (hawkeye) { | |
465 | case 0xb852: | |
466 | switch (rev) { | |
467 | case 0: | |
468 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
469 | break; |
470 | case 1: | |
e49c4d27 | 471 | default: |
ed6be0ba | 472 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
473 | } |
474 | break; | |
475 | case 0xb95c: | |
476 | switch (rev) { | |
477 | case 3: | |
478 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 479 | break; |
e49c4d27 | 480 | case 4: |
e49c4d27 | 481 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
482 | break; |
483 | case 6: | |
484 | default: | |
485 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
486 | } |
487 | break; | |
fa54dccd A |
488 | case 0xb94e: |
489 | switch (rev) { | |
490 | case 0: | |
fa54dccd | 491 | omap_revision = OMAP4460_REV_ES1_0; |
fa54dccd | 492 | break; |
33ee0db5 CL |
493 | case 2: |
494 | default: | |
495 | omap_revision = OMAP4460_REV_ES1_1; | |
496 | break; | |
fa54dccd A |
497 | } |
498 | break; | |
ec023e46 LI |
499 | case 0xb975: |
500 | switch (rev) { | |
501 | case 0: | |
502 | default: | |
503 | omap_revision = OMAP4470_REV_ES1_0; | |
504 | break; | |
505 | } | |
506 | break; | |
ed6be0ba | 507 | default: |
e49c4d27 | 508 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 509 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
510 | } |
511 | ||
e49c4d27 NK |
512 | pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, |
513 | ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); | |
b570e0ec SS |
514 | } |
515 | ||
a8823143 TL |
516 | /* |
517 | * Set up things for map_io and processor detection later on. Gets called | |
518 | * pretty much first thing from board init. For multi-omap, this gets | |
519 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
520 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
521 | * is done. | |
522 | */ | |
0e564848 TL |
523 | void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) |
524 | { | |
84a34344 | 525 | omap_revision = omap2_globals->class; |
0e564848 TL |
526 | tap_base = omap2_globals->tap; |
527 | ||
a8823143 | 528 | if (cpu_is_omap34xx()) |
0e564848 TL |
529 | tap_prod_id = 0x0210; |
530 | else | |
531 | tap_prod_id = 0x0208; | |
532 | } |