[deliverable/linux.git] / arch / arm / mach-omap2 / id.c

/*
 * linux/arch/arm/mach-omap2/id.c
 *
 * OMAP2 CPU identification code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009-11 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/cputype.h>

#include "common.h"
#include <plat/cpu.h>

#include <mach/id.h>

#include "control.h"

static unsigned int omap_revision;
static const char *cpu_rev;
u32 omap_features;

unsigned int omap_rev(void)
{
	return omap_revision;
}
EXPORT_SYMBOL(omap_rev);

int omap_type(void)
{
	u32 val = 0;

	if (cpu_is_omap24xx()) {
		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
	} else if (cpu_is_am33xx()) {
		val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
	} else if (cpu_is_omap34xx()) {
		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
	} else if (cpu_is_omap44xx()) {
		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
	} else {
		pr_err("Cannot detect omap type!\n");
		goto out;
	}

	val &= OMAP2_DEVICETYPE_MASK;
	val >>= 8;

out:
	return val;
}
EXPORT_SYMBOL(omap_type);


/*----------------------------------------------------------------------------*/

#define OMAP_TAP_IDCODE		0x0204
#define OMAP_TAP_DIE_ID_0	0x0218
#define OMAP_TAP_DIE_ID_1	0x021C
#define OMAP_TAP_DIE_ID_2	0x0220
#define OMAP_TAP_DIE_ID_3	0x0224

#define OMAP_TAP_DIE_ID_44XX_0	0x0200
#define OMAP_TAP_DIE_ID_44XX_1	0x0208
#define OMAP_TAP_DIE_ID_44XX_2	0x020c
#define OMAP_TAP_DIE_ID_44XX_3	0x0210

#define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))

struct omap_id {
	u16	hawkeye;	/* Silicon type (Hawkeye id) */
	u8	dev;		/* Device type from production_id reg */
	u32	type;		/* Combined type id copied to omap_revision */
};

/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
};

static void __iomem *tap_base;
static u16 tap_prod_id;

void omap_get_die_id(struct omap_die_id *odi)
{
	if (cpu_is_omap44xx()) {
		odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
		odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
		odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
		odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);

		return;
	}
	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
}

void __init omap2xxx_check_revision(void)
{
	int i, j;
	u32 idcode, prod_id;
	u16 hawkeye;
	u8  dev_type, rev;
	struct omap_die_id odi;

	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	prod_id = read_tap_reg(tap_prod_id);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0x0f;
	dev_type = (prod_id >> 16) & 0x0f;
	omap_get_die_id(&odi);

	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
		 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
		 odi.id_1, (odi.id_1 >> 28) & 0xf);
	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
		 prod_id, dev_type);

	/* Check hawkeye ids */
	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
		if (hawkeye == omap_ids[i].hawkeye)
			break;
	}

	if (i == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP CPU id\n");
		return;
	}

	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
		if (dev_type == omap_ids[j].dev)
			break;
	}

	if (j == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP device type. "
				"Handling it as OMAP%04x\n",
				omap_ids[i].type >> 16);
		j = i;
	}

	pr_info("OMAP%04x", omap_rev() >> 16);
	if ((omap_rev() >> 8) & 0x0f)
		pr_info("ES%x", (omap_rev() >> 12) & 0xf);
	pr_info("\n");
}

#define OMAP3_SHOW_FEATURE(feat)		\
	if (omap3_has_ ##feat())		\
		printk(#feat" ");

static void __init omap3_cpuinfo(void)
{
	const char *cpu_name;

	/*
	 * OMAP3430 and OMAP3530 are assumed to be same.
	 *
	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	 * on available features. Upon detection, update the CPU id
	 * and CPU class bits.
	 */
	if (cpu_is_omap3630()) {
		cpu_name = "OMAP3630";
	} else if (cpu_is_omap3517()) {
		/* AM35xx devices */
		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
	} else if (cpu_is_ti816x()) {
		cpu_name = "TI816X";
	} else if (cpu_is_am335x()) {
		cpu_name =  "AM335X";
	} else if (cpu_is_ti814x()) {
		cpu_name = "TI814X";
	} else if (omap3_has_iva() && omap3_has_sgx()) {
		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
		cpu_name = "OMAP3430/3530";
	} else if (omap3_has_iva()) {
		cpu_name = "OMAP3525";
	} else if (omap3_has_sgx()) {
		cpu_name = "OMAP3515";
	} else {
		cpu_name = "OMAP3503";
	}

	/* Print verbose information */
	pr_info("%s ES%s (", cpu_name, cpu_rev);

	OMAP3_SHOW_FEATURE(l2cache);
	OMAP3_SHOW_FEATURE(iva);
	OMAP3_SHOW_FEATURE(sgx);
	OMAP3_SHOW_FEATURE(neon);
	OMAP3_SHOW_FEATURE(isp);
	OMAP3_SHOW_FEATURE(192mhz_clk);

	printk(")\n");
}

#define OMAP3_CHECK_FEATURE(status,feat)				\
	if (((status & OMAP3_ ##feat## _MASK) 				\
		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
		omap_features |= OMAP3_HAS_ ##feat;			\
	}

void __init omap3xxx_check_features(void)
{
	u32 status;

	omap_features = 0;

	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);

	OMAP3_CHECK_FEATURE(status, L2CACHE);
	OMAP3_CHECK_FEATURE(status, IVA);
	OMAP3_CHECK_FEATURE(status, SGX);
	OMAP3_CHECK_FEATURE(status, NEON);
	OMAP3_CHECK_FEATURE(status, ISP);
	if (cpu_is_omap3630())
		omap_features |= OMAP3_HAS_192MHZ_CLK;
	if (cpu_is_omap3430() || cpu_is_omap3630())
		omap_features |= OMAP3_HAS_IO_WAKEUP;
	if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
	    omap_rev() == OMAP3430_REV_ES3_1_2)
		omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;

	omap_features |= OMAP3_HAS_SDRC;

	/*
	 * TODO: Get additional info (where applicable)
	 *       e.g. Size of L2 cache.
	 */

	omap3_cpuinfo();
}

void __init omap4xxx_check_features(void)
{
	u32 si_type;

	if (cpu_is_omap443x())
		omap_features |= OMAP4_HAS_MPU_1GHZ;


	if (cpu_is_omap446x()) {
		si_type =
			read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
		switch ((si_type & (3 << 16)) >> 16) {
		case 2:
			/* High performance device */
			omap_features |= OMAP4_HAS_MPU_1_5GHZ;
			break;
		case 1:
		default:
			/* Standard device */
			omap_features |= OMAP4_HAS_MPU_1_2GHZ;
			break;
		}
	}
}

void __init ti81xx_check_features(void)
{
	omap_features = OMAP3_HAS_NEON;
	omap3_cpuinfo();
}

void __init omap3xxx_check_revision(void)
{
	u32 cpuid, idcode;
	u16 hawkeye;
	u8 rev;

	/*
	 * We cannot access revision registers on ES1.0.
	 * If the processor type is Cortex-A8 and the revision is 0x0
	 * it means its Cortex r0p0 which is 3430 ES1.0.
	 */
	cpuid = read_cpuid(CPUID_ID);
	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
		omap_revision = OMAP3430_REV_ES1_0;
		cpu_rev = "1.0";
		return;
	}

	/*
	 * Detection for 34xx ES2.0 and above can be done with just
	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
	 * Note that rev does not map directly to our defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	switch (hawkeye) {
	case 0xb7ae:
		/* Handle 34xx/35xx devices */
		switch (rev) {
		case 0: /* Take care of early samples */
		case 1:
			omap_revision = OMAP3430_REV_ES2_0;
			cpu_rev = "2.0";
			break;
		case 2:
			omap_revision = OMAP3430_REV_ES2_1;
			cpu_rev = "2.1";
			break;
		case 3:
			omap_revision = OMAP3430_REV_ES3_0;
			cpu_rev = "3.0";
			break;
		case 4:
			omap_revision = OMAP3430_REV_ES3_1;
			cpu_rev = "3.1";
			break;
		case 7:
		/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			omap_revision = OMAP3430_REV_ES3_1_2;
			cpu_rev = "3.1.2";
		}
		break;
	case 0xb868:
		/*
		 * Handle OMAP/AM 3505/3517 devices
		 *
		 * Set the device to be OMAP3517 here. Actual device
		 * is identified later based on the features.
		 */
		switch (rev) {
		case 0:
			omap_revision = OMAP3517_REV_ES1_0;
			cpu_rev = "1.0";
			break;
		case 1:
		/* FALLTHROUGH */
		default:
			omap_revision = OMAP3517_REV_ES1_1;
			cpu_rev = "1.1";
		}
		break;
	case 0xb891:
		/* Handle 36xx devices */

		switch(rev) {
		case 0: /* Take care of early samples */
			omap_revision = OMAP3630_REV_ES1_0;
			cpu_rev = "1.0";
			break;
		case 1:
			omap_revision = OMAP3630_REV_ES1_1;
			cpu_rev = "1.1";
			break;
		case 2:
		/* FALLTHROUGH */
		default:
			omap_revision = OMAP3630_REV_ES1_2;
			cpu_rev = "1.2";
		}
		break;
	case 0xb81e:
		switch (rev) {
		case 0:
			omap_revision = TI8168_REV_ES1_0;
			cpu_rev = "1.0";
			break;
		case 1:
		/* FALLTHROUGH */
		default:
			omap_revision = TI8168_REV_ES1_1;
			cpu_rev = "1.1";
			break;
		}
		break;
	case 0xb944:
		omap_revision = AM335X_REV_ES1_0;
		cpu_rev = "1.0";
		break;
	case 0xb8f2:
		switch (rev) {
		case 0:
		/* FALLTHROUGH */
		case 1:
			omap_revision = TI8148_REV_ES1_0;
			cpu_rev = "1.0";
			break;
		case 2:
			omap_revision = TI8148_REV_ES2_0;
			cpu_rev = "2.0";
			break;
		case 3:
		/* FALLTHROUGH */
		default:
			omap_revision = TI8148_REV_ES2_1;
			cpu_rev = "2.1";
			break;
		}
		break;
	default:
		/* Unknown default to latest silicon rev as default */
		omap_revision = OMAP3630_REV_ES1_2;
		cpu_rev = "1.2";
		pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
	}
}

void __init omap4xxx_check_revision(void)
{
	u32 idcode;
	u16 hawkeye;
	u8 rev;

	/*
	 * The IC rev detection is done with hawkeye and rev.
	 * Note that rev does not map directly to defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xf;

	/*
	 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
	 * Use ARM register to detect the correct ES version
	 */
	if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
		idcode = read_cpuid(CPUID_ID);
		rev = (idcode & 0xf) - 1;
	}

	switch (hawkeye) {
	case 0xb852:
		switch (rev) {
		case 0:
			omap_revision = OMAP4430_REV_ES1_0;
			break;
		case 1:
		default:
			omap_revision = OMAP4430_REV_ES2_0;
		}
		break;
	case 0xb95c:
		switch (rev) {
		case 3:
			omap_revision = OMAP4430_REV_ES2_1;
			break;
		case 4:
			omap_revision = OMAP4430_REV_ES2_2;
			break;
		case 6:
		default:
			omap_revision = OMAP4430_REV_ES2_3;
		}
		break;
	case 0xb94e:
		switch (rev) {
		case 0:
		default:
			omap_revision = OMAP4460_REV_ES1_0;
			break;
		}
		break;
	case 0xb975:
		switch (rev) {
		case 0:
		default:
			omap_revision = OMAP4470_REV_ES1_0;
			break;
		}
		break;
	default:
		/* Unknown default to latest silicon rev as default */
		omap_revision = OMAP4430_REV_ES2_3;
	}

	pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
		((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
}

/*
 * Set up things for map_io and processor detection later on. Gets called
 * pretty much first thing from board init. For multi-omap, this gets
 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 * detect the exact revision later on in omap2_detect_revision() once map_io
 * is done.
 */
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
{
	omap_revision = omap2_globals->class;
	tap_base = omap2_globals->tap;

	if (cpu_is_omap34xx())
		tap_prod_id = 0x0210;
	else
		tap_prod_id = 0x0208;
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/id.c
	3	*
	4	* OMAP2 CPU identification code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
e49c4d27	9	* Copyright (C) 2009-11 Texas Instruments
44169075 SS	10	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
44169075 SS	11	*
1dbae815 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
1dbae815 TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
fced80c7	20	#include <linux/io.h>
1dbae815	21
0ba8b9b2	22	#include <asm/cputype.h>
1dbae815	23
4e65331c	24	#include "common.h"
ce491cf8	25	#include <plat/cpu.h>
72d0f1c3	26
2e130fc3 KRC	27	#include <mach/id.h>
2e130fc3 KRC	28
4814ced5 PW	29	#include "control.h"
4814ced5 PW	30
84a34344	31	static unsigned int omap_revision;
50a01e64	32	static const char *cpu_rev;
cc0170b2	33	u32 omap_features;
84a34344 LL	34
	35	unsigned int omap_rev(void)
	36	{
	37	return omap_revision;
	38	}
	39	EXPORT_SYMBOL(omap_rev);
097c584c	40
8e25ad96 KH	41	int omap_type(void)
	42	{
	43	u32 val = 0;
	44
edeae658	45	if (cpu_is_omap24xx()) {
8e25ad96	46	val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
fb3cfb1f AM	47	} else if (cpu_is_am33xx()) {
fb3cfb1f AM	48	val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
edeae658	49	} else if (cpu_is_omap34xx()) {
8e25ad96	50	val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
737daa03	51	} else if (cpu_is_omap44xx()) {
dcf5ef3f	52	val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
edeae658	53	} else {
8e25ad96 KH	54	pr_err("Cannot detect omap type!\n");
	55	goto out;
	56	}
	57
	58	val &= OMAP2_DEVICETYPE_MASK;
	59	val >>= 8;
	60
	61	out:
	62	return val;
	63	}
	64	EXPORT_SYMBOL(omap_type);
	65
	66
a8823143	67	/----------------------------------------------------------------------------/
097c584c	68
a8823143 TL	69	#define OMAP_TAP_IDCODE 0x0204
	70	#define OMAP_TAP_DIE_ID_0 0x0218
	71	#define OMAP_TAP_DIE_ID_1 0x021C
	72	#define OMAP_TAP_DIE_ID_2 0x0220
	73	#define OMAP_TAP_DIE_ID_3 0x0224
097c584c	74
b235e007 AG	75	#define OMAP_TAP_DIE_ID_44XX_0 0x0200
	76	#define OMAP_TAP_DIE_ID_44XX_1 0x0208
	77	#define OMAP_TAP_DIE_ID_44XX_2 0x020c
	78	#define OMAP_TAP_DIE_ID_44XX_3 0x0210
	79
a8823143	80	#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
097c584c	81
a8823143 TL	82	struct omap_id {
	83	u16 hawkeye; /* Silicon type (Hawkeye id) */
	84	u8 dev; /* Device type from production_id reg */
84a34344	85	u32 type; /* Combined type id copied to omap_revision */
a8823143	86	};
097c584c	87
a8823143 TL	88	/* Register values to detect the OMAP version */
	89	static struct omap_id omap_ids[] __initdata = {
	90	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	91	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	92	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	93	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	94	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	95	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
	96	};
097c584c	97
a8823143 TL	98	static void __iomem *tap_base;
a8823143 TL	99	static u16 tap_prod_id;
1dbae815	100
2e130fc3 KRC	101	void omap_get_die_id(struct omap_die_id *odi)
2e130fc3 KRC	102	{
b235e007 AG	103	if (cpu_is_omap44xx()) {
	104	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
	105	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
	106	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
	107	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
	108
	109	return;
	110	}
2e130fc3 KRC	111	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
	112	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
	113	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
	114	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
	115	}
	116
4de34f35	117	void __init omap2xxx_check_revision(void)
1dbae815 TL	118	{
1dbae815 TL	119	int i, j;
a8823143	120	u32 idcode, prod_id;
1dbae815	121	u16 hawkeye;
a8823143	122	u8 dev_type, rev;
c46732bb	123	struct omap_die_id odi;
1dbae815 TL	124
1dbae815 TL	125	idcode = read_tap_reg(OMAP_TAP_IDCODE);
0e564848	126	prod_id = read_tap_reg(tap_prod_id);
1dbae815 TL	127	hawkeye = (idcode >> 12) & 0xffff;
	128	rev = (idcode >> 28) & 0x0f;
	129	dev_type = (prod_id >> 16) & 0x0f;
c46732bb	130	omap_get_die_id(&odi);
1dbae815	131
097c584c PW	132	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
097c584c PW	133	idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
c46732bb	134	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
097c584c	135	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
c46732bb KRC	136	odi.id_1, (odi.id_1 >> 28) & 0xf);
	137	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
	138	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
097c584c PW	139	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
	140	prod_id, dev_type);
	141
1dbae815 TL	142	/* Check hawkeye ids */
	143	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
	144	if (hawkeye == omap_ids[i].hawkeye)
	145	break;
	146	}
	147
	148	if (i == ARRAY_SIZE(omap_ids)) {
	149	printk(KERN_ERR "Unknown OMAP CPU id\n");
	150	return;
	151	}
	152
	153	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
	154	if (dev_type == omap_ids[j].dev)
	155	break;
	156	}
	157
	158	if (j == ARRAY_SIZE(omap_ids)) {
	159	printk(KERN_ERR "Unknown OMAP device type. "
	160	"Handling it as OMAP%04x\n",
	161	omap_ids[i].type >> 16);
	162	j = i;
	163	}
1dbae815	164
84a34344 LL	165	pr_info("OMAP%04x", omap_rev() >> 16);
	166	if ((omap_rev() >> 8) & 0x0f)
	167	pr_info("ES%x", (omap_rev() >> 12) & 0xf);
097c584c	168	pr_info("\n");
a8823143 TL	169	}
a8823143 TL	170
50a01e64 VH	171	#define OMAP3_SHOW_FEATURE(feat) \
	172	if (omap3_has_ ##feat()) \
	173	printk(#feat" ");
	174
	175	static void __init omap3_cpuinfo(void)
	176	{
	177	const char *cpu_name;
	178
	179	/*
	180	* OMAP3430 and OMAP3530 are assumed to be same.
	181	*
	182	* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	183	* on available features. Upon detection, update the CPU id
	184	* and CPU class bits.
	185	*/
	186	if (cpu_is_omap3630()) {
	187	cpu_name = "OMAP3630";
	188	} else if (cpu_is_omap3517()) {
	189	/* AM35xx devices */
	190	cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
	191	} else if (cpu_is_ti816x()) {
	192	cpu_name = "TI816X";
	193	} else if (cpu_is_am335x()) {
	194	cpu_name = "AM335X";
	195	} else if (cpu_is_ti814x()) {
	196	cpu_name = "TI814X";
	197	} else if (omap3_has_iva() && omap3_has_sgx()) {
	198	/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
	199	cpu_name = "OMAP3430/3530";
	200	} else if (omap3_has_iva()) {
	201	cpu_name = "OMAP3525";
	202	} else if (omap3_has_sgx()) {
	203	cpu_name = "OMAP3515";
	204	} else {
	205	cpu_name = "OMAP3503";
	206	}
	207
	208	/* Print verbose information */
	209	pr_info("%s ES%s (", cpu_name, cpu_rev);
	210
	211	OMAP3_SHOW_FEATURE(l2cache);
	212	OMAP3_SHOW_FEATURE(iva);
	213	OMAP3_SHOW_FEATURE(sgx);
	214	OMAP3_SHOW_FEATURE(neon);
	215	OMAP3_SHOW_FEATURE(isp);
	216	OMAP3_SHOW_FEATURE(192mhz_clk);
	217
	218	printk(")\n");
	219	}
	220
8384ce07 SP	221	#define OMAP3_CHECK_FEATURE(status,feat) \
	222	if (((status & OMAP3_ ##feat## _MASK) \
	223	>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
cc0170b2	224	omap_features \|= OMAP3_HAS_ ##feat; \
8384ce07 SP	225	}
8384ce07 SP	226
4de34f35	227	void __init omap3xxx_check_features(void)
8384ce07 SP	228	{
	229	u32 status;
	230
cc0170b2	231	omap_features = 0;
8384ce07 SP	232
	233	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
	234
	235	OMAP3_CHECK_FEATURE(status, L2CACHE);
	236	OMAP3_CHECK_FEATURE(status, IVA);
	237	OMAP3_CHECK_FEATURE(status, SGX);
	238	OMAP3_CHECK_FEATURE(status, NEON);
	239	OMAP3_CHECK_FEATURE(status, ISP);
7356f0b2	240	if (cpu_is_omap3630())
cc0170b2	241	omap_features \|= OMAP3_HAS_192MHZ_CLK;
b02b9172	242	if (cpu_is_omap3430() \|\| cpu_is_omap3630())
cc0170b2	243	omap_features \|= OMAP3_HAS_IO_WAKEUP;
b02b9172 PW	244	if (cpu_is_omap3630() \|\| omap_rev() == OMAP3430_REV_ES3_1 \|\|
	245	omap_rev() == OMAP3430_REV_ES3_1_2)
	246	omap_features \|= OMAP3_HAS_IO_CHAIN_CTRL;
8384ce07	247
cc0170b2	248	omap_features \|= OMAP3_HAS_SDRC;
01001712	249
8384ce07 SP	250	/*
	251	* TODO: Get additional info (where applicable)
	252	* e.g. Size of L2 cache.
	253	*/
4de34f35 VH	254
4de34f35 VH	255	omap3_cpuinfo();
8384ce07 SP	256	}
8384ce07 SP	257
4de34f35	258	void __init omap4xxx_check_features(void)
cc0170b2 A	259	{
	260	u32 si_type;
	261
	262	if (cpu_is_omap443x())
	263	omap_features \|= OMAP4_HAS_MPU_1GHZ;
	264
	265
	266	if (cpu_is_omap446x()) {
	267	si_type =
	268	read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
	269	switch ((si_type & (3 << 16)) >> 16) {
	270	case 2:
	271	/* High performance device */
	272	omap_features \|= OMAP4_HAS_MPU_1_5GHZ;
	273	break;
	274	case 1:
	275	default:
	276	/* Standard device */
	277	omap_features \|= OMAP4_HAS_MPU_1_2GHZ;
	278	break;
	279	}
	280	}
	281	}
	282
4de34f35	283	void __init ti81xx_check_features(void)
01001712	284	{
cc0170b2	285	omap_features = OMAP3_HAS_NEON;
4de34f35	286	omap3_cpuinfo();
01001712 HP	287	}
01001712 HP	288
4de34f35	289	void __init omap3xxx_check_revision(void)
a8823143 TL	290	{
	291	u32 cpuid, idcode;
	292	u16 hawkeye;
	293	u8 rev;
a8823143 TL	294
	295	/*
	296	* We cannot access revision registers on ES1.0.
	297	* If the processor type is Cortex-A8 and the revision is 0x0
	298	* it means its Cortex r0p0 which is 3430 ES1.0.
	299	*/
	300	cpuid = read_cpuid(CPUID_ID);
	301	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
84a34344	302	omap_revision = OMAP3430_REV_ES1_0;
50a01e64	303	cpu_rev = "1.0";
048f4bd7	304	return;
a8823143 TL	305	}
	306
	307	/*
	308	* Detection for 34xx ES2.0 and above can be done with just
	309	* hawkeye and rev. See TRM 1.5.2 Device Identification.
	310	* Note that rev does not map directly to our defined processor
	311	* revision numbers as ES1.0 uses value 0.
	312	*/
	313	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	314	hawkeye = (idcode >> 12) & 0xffff;
	315	rev = (idcode >> 28) & 0xff;
097c584c	316
2456a10f NM	317	switch (hawkeye) {
	318	case 0xb7ae:
	319	/* Handle 34xx/35xx devices */
a8823143	320	switch (rev) {
048f4bd7 SP	321	case 0: /* Take care of early samples */
048f4bd7 SP	322	case 1:
84a34344	323	omap_revision = OMAP3430_REV_ES2_0;
50a01e64	324	cpu_rev = "2.0";
a8823143 TL	325	break;
a8823143 TL	326	case 2:
84a34344	327	omap_revision = OMAP3430_REV_ES2_1;
50a01e64	328	cpu_rev = "2.1";
a8823143 TL	329	break;
a8823143 TL	330	case 3:
84a34344	331	omap_revision = OMAP3430_REV_ES3_0;
50a01e64	332	cpu_rev = "3.0";
a8823143	333	break;
187e688d	334	case 4:
e9acb9b6	335	omap_revision = OMAP3430_REV_ES3_1;
50a01e64	336	cpu_rev = "3.1";
e9acb9b6 TL	337	break;
e9acb9b6 TL	338	case 7:
edeae658	339	/* FALLTHROUGH */
a8823143 TL	340	default:
a8823143 TL	341	/* Use the latest known revision as default */
e9acb9b6	342	omap_revision = OMAP3430_REV_ES3_1_2;
50a01e64	343	cpu_rev = "3.1.2";
a8823143	344	}
2456a10f	345	break;
4cac6018	346	case 0xb868:
1f1b0353 PW	347	/*
1f1b0353 PW	348	* Handle OMAP/AM 3505/3517 devices
4cac6018	349	*
1f1b0353	350	* Set the device to be OMAP3517 here. Actual device
4cac6018 SP	351	* is identified later based on the features.
4cac6018 SP	352	*/
9ed2ba7a PW	353	switch (rev) {
	354	case 0:
	355	omap_revision = OMAP3517_REV_ES1_0;
50a01e64	356	cpu_rev = "1.0";
9ed2ba7a PW	357	break;
	358	case 1:
	359	/* FALLTHROUGH */
	360	default:
	361	omap_revision = OMAP3517_REV_ES1_1;
50a01e64	362	cpu_rev = "1.1";
9ed2ba7a	363	}
4cac6018	364	break;
edeae658	365	case 0xb891:
b0a1a6ce	366	/* Handle 36xx devices */
b0a1a6ce AG	367
	368	switch(rev) {
	369	case 0: /* Take care of early samples */
	370	omap_revision = OMAP3630_REV_ES1_0;
50a01e64	371	cpu_rev = "1.0";
b0a1a6ce AG	372	break;
	373	case 1:
	374	omap_revision = OMAP3630_REV_ES1_1;
50a01e64	375	cpu_rev = "1.1";
b0a1a6ce AG	376	break;
b0a1a6ce AG	377	case 2:
51ec811a	378	/* FALLTHROUGH */
b0a1a6ce	379	default:
51ec811a	380	omap_revision = OMAP3630_REV_ES1_2;
50a01e64	381	cpu_rev = "1.2";
b0a1a6ce	382	}
77c0870c	383	break;
01001712	384	case 0xb81e:
01001712 HP	385	switch (rev) {
	386	case 0:
	387	omap_revision = TI8168_REV_ES1_0;
50a01e64	388	cpu_rev = "1.0";
01001712 HP	389	break;
01001712 HP	390	case 1:
51ec811a	391	/* FALLTHROUGH */
01001712	392	default:
51ec811a	393	omap_revision = TI8168_REV_ES1_1;
50a01e64	394	cpu_rev = "1.1";
3b32b7d6	395	break;
01001712 HP	396	}
01001712 HP	397	break;
1e6cb146 AM	398	case 0xb944:
1e6cb146 AM	399	omap_revision = AM335X_REV_ES1_0;
50a01e64	400	cpu_rev = "1.0";
c2d13554	401	break;
4390f5b2 HP	402	case 0xb8f2:
	403	switch (rev) {
	404	case 0:
	405	/* FALLTHROUGH */
	406	case 1:
	407	omap_revision = TI8148_REV_ES1_0;
50a01e64	408	cpu_rev = "1.0";
4390f5b2 HP	409	break;
	410	case 2:
	411	omap_revision = TI8148_REV_ES2_0;
50a01e64	412	cpu_rev = "2.0";
4390f5b2 HP	413	break;
	414	case 3:
	415	/* FALLTHROUGH */
	416	default:
	417	omap_revision = TI8148_REV_ES2_1;
50a01e64	418	cpu_rev = "2.1";
4390f5b2 HP	419	break;
4390f5b2 HP	420	}
1e6cb146	421	break;
2456a10f	422	default:
51ec811a	423	/* Unknown default to latest silicon rev as default */
3b32b7d6	424	omap_revision = OMAP3630_REV_ES1_2;
50a01e64	425	cpu_rev = "1.2";
51ec811a	426	pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
a8823143	427	}
1dbae815 TL	428	}
1dbae815 TL	429
4de34f35	430	void __init omap4xxx_check_revision(void)
b570e0ec SS	431	{
	432	u32 idcode;
	433	u16 hawkeye;
	434	u8 rev;
b570e0ec SS	435
	436	/*
	437	* The IC rev detection is done with hawkeye and rev.
	438	* Note that rev does not map directly to defined processor
	439	* revision numbers as ES1.0 uses value 0.
	440	*/
	441	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	442	hawkeye = (idcode >> 12) & 0xffff;
e49c4d27	443	rev = (idcode >> 28) & 0xf;
b570e0ec	444
ed6be0ba	445	/*
fa54dccd	446	* Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
ed6be0ba SS	447	* Use ARM register to detect the correct ES version
ed6be0ba SS	448	*/
ec023e46	449	if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
ed6be0ba SS	450	idcode = read_cpuid(CPUID_ID);
	451	rev = (idcode & 0xf) - 1;
	452	}
	453
	454	switch (hawkeye) {
	455	case 0xb852:
	456	switch (rev) {
	457	case 0:
	458	omap_revision = OMAP4430_REV_ES1_0;
ed6be0ba SS	459	break;
ed6be0ba SS	460	case 1:
e49c4d27	461	default:
ed6be0ba	462	omap_revision = OMAP4430_REV_ES2_0;
e49c4d27 NK	463	}
	464	break;
	465	case 0xb95c:
	466	switch (rev) {
	467	case 3:
	468	omap_revision = OMAP4430_REV_ES2_1;
ed6be0ba	469	break;
e49c4d27	470	case 4:
e49c4d27	471	omap_revision = OMAP4430_REV_ES2_2;
55035c15 DA	472	break;
	473	case 6:
	474	default:
	475	omap_revision = OMAP4430_REV_ES2_3;
e49c4d27 NK	476	}
e49c4d27 NK	477	break;
fa54dccd A	478	case 0xb94e:
	479	switch (rev) {
	480	case 0:
	481	default:
	482	omap_revision = OMAP4460_REV_ES1_0;
fa54dccd A	483	break;
	484	}
	485	break;
ec023e46 LI	486	case 0xb975:
	487	switch (rev) {
	488	case 0:
	489	default:
	490	omap_revision = OMAP4470_REV_ES1_0;
	491	break;
	492	}
	493	break;
ed6be0ba	494	default:
e49c4d27	495	/* Unknown default to latest silicon rev as default */
55035c15	496	omap_revision = OMAP4430_REV_ES2_3;
b570e0ec SS	497	}
b570e0ec SS	498
e49c4d27 NK	499	pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
e49c4d27 NK	500	((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
b570e0ec SS	501	}
b570e0ec SS	502
a8823143 TL	503	/*
	504	* Set up things for map_io and processor detection later on. Gets called
	505	* pretty much first thing from board init. For multi-omap, this gets
	506	* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
	507	* detect the exact revision later on in omap2_detect_revision() once map_io
	508	* is done.
	509	*/
0e564848 TL	510	void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
0e564848 TL	511	{
84a34344	512	omap_revision = omap2_globals->class;
0e564848 TL	513	tap_base = omap2_globals->tap;
0e564848 TL	514
a8823143	515	if (cpu_is_omap34xx())
0e564848 TL	516	tap_prod_id = 0x0210;
	517	else
	518	tap_prod_id = 0x0208;
	519	}