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Merge tag 'v4.5-rc5' into asoc-mtk
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
45c3eb7d 28#include <linux/omap-dma.h>
ee0839c2 29
dc843280 30#include "omap_hwmod.h"
dbc04161 31#include "soc.h"
ee0839c2 32#include "iomap.h"
81a60482 33#include "voltage.h"
72e06d08 34#include "powerdomain.h"
1540f214 35#include "clockdomain.h"
4e65331c 36#include "common.h"
e30384ab 37#include "clock.h"
ee0839c2
TL		 38#include "clock2xxx.h"
39#include "clock3xxx.h"
1d5aef49 40#include "omap-pm.h"
3e6ece13 41#include "sdrc.h"
b6a4226c 42#include "control.h"
3d82cbbb 43#include "serial.h"
bf027ca1 44#include "sram.h"
c4ceedcb
PW		 45#include "cm2xxx.h"
46#include "cm3xxx.h"
7632a02f 47#include "cm33xx.h"
ab6c9bbf 48#include "cm44xx.h"
d9a16f9a
PW		 49#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
63a293e0
PW		 53#include "prm2xxx.h"
54#include "prm3xxx.h"
d9bbe84f 55#include "prm33xx.h"
63a293e0 56#include "prm44xx.h"
69a1e7a1 57#include "opp2xxx.h"
02bfc030 58
ff931c82 59/*
cfa9667d 60 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 61 * clock initializations
62 */
cfa9667d 63static int (*omap_clk_soc_init)(void);
ff931c82 64
1dbae815
TL		 65/*
66 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
cc26b3b0 69
e48f814e 70#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 71static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 72 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
09f21ed4 78 {
cc26b3b0
SMK		 79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
82 .type = MT_DEVICE
09f21ed4 83 },
cc26b3b0
SMK		 84};
85
59b479e0 86#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 87static struct map_desc omap242x_io_desc[] __initdata = {
88 {
7adb9987
PW		 89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 92 .type = MT_DEVICE
93 },
94 {
7adb9987
PW		 95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
cc26b3b0 98 .type = MT_DEVICE
09f21ed4 99 },
cc26b3b0 100 {
7adb9987
PW		 101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 104 .type = MT_DEVICE
105 },
106};
107
108#endif
109
59b479e0 110#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 111static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
cc26b3b0
SMK		 124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136};
72d0f1c3 137#endif
72d0f1c3 138#endif
cc26b3b0 139
a8eb7ca0 140#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 141static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 142 {
cc26b3b0
SMK		 143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
c40fae95
TL		 146 .type = MT_DEVICE
147 },
148 {
cc26b3b0
SMK		 149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
c40fae95
TL		 152 .type = MT_DEVICE
153 },
cc26b3b0
SMK		 154 {
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
1dbae815 158 .type = MT_DEVICE
cc26b3b0
SMK		 159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
1dbae815 170 .type = MT_DEVICE
cc26b3b0
SMK		 171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
1dbae815 184};
cc26b3b0 185#endif
01001712 186
33959553 187#ifdef CONFIG_SOC_TI81XX
a920360f 188static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 }
195};
196#endif
197
addb154a 198#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 199static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
1e6cb146
AM		 206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
01001712
HP		 212};
213#endif
214
44169075
SS		 215#ifdef CONFIG_ARCH_OMAP4
216static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
44169075
SS		 229 {
230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
44169075
SS		 235};
236#endif
1dbae815 237
ea827ad5 238#ifdef CONFIG_SOC_OMAP5
05e152c7
S		 239static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264};
265#endif
266
ea827ad5
NM		 267#ifdef CONFIG_SOC_DRA7XX
268static struct map_desc dra7xx_io_desc[] __initdata = {
269 {
270 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
272 .length = L4_CFG_MPU_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
278 .length = L3_MAIN_SN_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER1_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
284 .length = L4_PER1_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER2_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
290 .length = L4_PER2_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_PER3_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
296 .length = L4_PER3_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_CFG_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
302 .length = L4_CFG_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305 {
306 .virtual = L4_WKUP_DRA7XX_VIRT,
307 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
308 .length = L4_WKUP_DRA7XX_SIZE,
309 .type = MT_DEVICE,
310 },
311};
312#endif
313
59b479e0 314#ifdef CONFIG_SOC_OMAP2420
b6a4226c 315void __init omap242x_map_io(void)
1dbae815 316{
cc26b3b0
SMK		 317 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
318 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 319}
cc26b3b0
SMK		 320#endif
321
59b479e0 322#ifdef CONFIG_SOC_OMAP2430
b6a4226c 323void __init omap243x_map_io(void)
6fbd55d0 324{
cc26b3b0
SMK		 325 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
326 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 327}
cc26b3b0
SMK		 328#endif
329
a8eb7ca0 330#ifdef CONFIG_ARCH_OMAP3
b6a4226c 331void __init omap3_map_io(void)
6fbd55d0 332{
cc26b3b0 333 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 334}
cc26b3b0 335#endif
120db2cb 336
33959553 337#ifdef CONFIG_SOC_TI81XX
b6a4226c 338void __init ti81xx_map_io(void)
01001712 339{
a920360f 340 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 341}
342#endif
343
addb154a 344#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 345void __init am33xx_map_io(void)
01001712 346{
1e6cb146 347 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 348}
349#endif
350
6fbd55d0 351#ifdef CONFIG_ARCH_OMAP4
b6a4226c 352void __init omap4_map_io(void)
6fbd55d0 353{
44169075 354 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
f746929f 355 omap_barriers_init();
120db2cb 356}
6fbd55d0 357#endif
120db2cb 358
ea827ad5 359#ifdef CONFIG_SOC_OMAP5
b6a4226c 360void __init omap5_map_io(void)
05e152c7
S		 361{
362 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
f746929f 363 omap_barriers_init();
05e152c7
S		 364}
365#endif
ea827ad5
NM		 366
367#ifdef CONFIG_SOC_DRA7XX
368void __init dra7xx_map_io(void)
369{
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
371}
372#endif
2f135eaf
PW		 373/*
374 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
375 *
376 * Sets the CORE DPLL3 M2 divider to the same value that it's at
377 * currently. This has the effect of setting the SDRC SDRAM AC timing
378 * registers to the values currently defined by the kernel. Currently
379 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
380 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
381 * or passes along the return value of clk_set_rate().
382 */
383static int __init _omap2_init_reprogram_sdrc(void)
384{
385 struct clk *dpll3_m2_ck;
386 int v = -EINVAL;
387 long rate;
388
389 if (!cpu_is_omap34xx())
390 return 0;
391
392 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 393 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 394 return -EINVAL;
395
396 rate = clk_get_rate(dpll3_m2_ck);
397 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
398 v = clk_set_rate(dpll3_m2_ck, rate);
399 if (v)
400 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
401
402 clk_put(dpll3_m2_ck);
403
404 return v;
405}
406
2092e5cc
PW		 407static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
408{
409 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
410}
411
7b250aff
TL		 412static void __init omap_hwmod_init_postsetup(void)
413{
414 u8 postsetup_state;
2092e5cc
PW		 415
416 /* Set the default postsetup state for all hwmods */
bf7c5449 417#ifdef CONFIG_PM
2092e5cc
PW		 418 postsetup_state = _HWMOD_STATE_IDLE;
419#else
420 postsetup_state = _HWMOD_STATE_ENABLED;
421#endif
422 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 423
53da4ce2 424 omap_pm_if_early_init();
4805734b
PW		 425}
426
069d0a78 427static void __init __maybe_unused omap_common_late_init(void)
4ed12be0
RB		 428{
429 omap_mux_late_init();
430 omap2_common_pm_late_init();
6770b211 431 omap_soc_device_init();
4ed12be0
RB		 432}
433
16110798 434#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 435void __init omap2420_init_early(void)
436{
b6a4226c
PW		 437 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
438 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
439 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
2208bf11 440 omap2_control_base_init();
4de34f35 441 omap2xxx_check_revision();
ab7b2ffc 442 omap2_prcm_base_init();
7b250aff
TL		 443 omap2xxx_voltagedomains_init();
444 omap242x_powerdomains_init();
445 omap242x_clockdomains_init();
446 omap2420_hwmod_init();
447 omap_hwmod_init_postsetup();
6a194a6e
TK		 448 omap_clk_soc_init = omap2420_dt_clk_init;
449 rate_table = omap2420_rate_table;
8f5b5a41 450}
bbd707ac
SG		 451
452void __init omap2420_init_late(void)
453{
4ed12be0 454 omap_common_late_init();
bbd707ac 455 omap2_pm_init();
23fb8ba3 456 omap2_clk_enable_autoidle_all();
bbd707ac 457}
16110798 458#endif
8f5b5a41 459
16110798 460#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 461void __init omap2430_init_early(void)
462{
b6a4226c
PW		 463 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
464 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
465 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
2208bf11 466 omap2_control_base_init();
4de34f35 467 omap2xxx_check_revision();
ab7b2ffc 468 omap2_prcm_base_init();
7b250aff
TL		 469 omap2xxx_voltagedomains_init();
470 omap243x_powerdomains_init();
471 omap243x_clockdomains_init();
472 omap2430_hwmod_init();
473 omap_hwmod_init_postsetup();
6a194a6e
TK		 474 omap_clk_soc_init = omap2430_dt_clk_init;
475 rate_table = omap2430_rate_table;
7b250aff 476}
bbd707ac
SG		 477
478void __init omap2430_init_late(void)
479{
4ed12be0 480 omap_common_late_init();
bbd707ac 481 omap2_pm_init();
23fb8ba3 482 omap2_clk_enable_autoidle_all();
bbd707ac 483}
c4e2d245 484#endif
7b250aff
TL		 485
486/*
487 * Currently only board-omap3beagle.c should call this because of the
488 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
489 */
c4e2d245 490#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 491void __init omap3_init_early(void)
492{
b6a4226c
PW		 493 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
494 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
495 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
2208bf11
TK		 496 /* XXX: remove these once OMAP3 is DT only */
497 if (!of_have_populated_dt()) {
498 omap2_set_globals_control(
efde2346 499 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
2208bf11
TK		 500 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
501 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
502 NULL);
503 }
504 omap2_control_base_init();
4de34f35
VH		 505 omap3xxx_check_revision();
506 omap3xxx_check_features();
ab7b2ffc 507 omap2_prcm_base_init();
425dc8b2
TK		 508 /* XXX: remove these once OMAP3 is DT only */
509 if (!of_have_populated_dt()) {
510 omap3xxx_prm_init(NULL);
511 omap3xxx_cm_init(NULL);
512 }
7b250aff
TL		 513 omap3xxx_voltagedomains_init();
514 omap3xxx_powerdomains_init();
515 omap3xxx_clockdomains_init();
516 omap3xxx_hwmod_init();
517 omap_hwmod_init_postsetup();
eded36fe 518 if (!of_have_populated_dt()) {
2208bf11 519 omap3_control_legacy_iomap_init();
eded36fe
TK		 520 if (soc_is_am35xx())
521 omap_clk_soc_init = am35xx_clk_legacy_init;
522 else if (cpu_is_omap3630())
523 omap_clk_soc_init = omap36xx_clk_legacy_init;
524 else if (omap_rev() == OMAP3430_REV_ES1_0)
525 omap_clk_soc_init = omap3430es1_clk_legacy_init;
526 else
527 omap_clk_soc_init = omap3430_clk_legacy_init;
528 }
8f5b5a41
TL		 529}
530
531void __init omap3430_init_early(void)
532{
7b250aff 533 omap3_init_early();
3e049157
TK		 534 if (of_have_populated_dt())
535 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 536}
537
538void __init omap35xx_init_early(void)
539{
7b250aff 540 omap3_init_early();
3e049157
TK		 541 if (of_have_populated_dt())
542 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 543}
544
545void __init omap3630_init_early(void)
546{
7b250aff 547 omap3_init_early();
3e049157
TK		 548 if (of_have_populated_dt())
549 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 550}
551
552void __init am35xx_init_early(void)
553{
7b250aff 554 omap3_init_early();
3e049157
TK		 555 if (of_have_populated_dt())
556 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 557}
558
bbd707ac
SG		 559void __init omap3_init_late(void)
560{
4ed12be0 561 omap_common_late_init();
bbd707ac 562 omap3_pm_init();
23fb8ba3 563 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 564}
565
566void __init omap3430_init_late(void)
567{
4ed12be0 568 omap_common_late_init();
bbd707ac 569 omap3_pm_init();
23fb8ba3 570 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 571}
572
573void __init omap35xx_init_late(void)
574{
4ed12be0 575 omap_common_late_init();
bbd707ac 576 omap3_pm_init();
23fb8ba3 577 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 578}
579
580void __init omap3630_init_late(void)
581{
4ed12be0 582 omap_common_late_init();
bbd707ac 583 omap3_pm_init();
23fb8ba3 584 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 585}
586
587void __init am35xx_init_late(void)
588{
4ed12be0 589 omap_common_late_init();
bbd707ac 590 omap3_pm_init();
23fb8ba3 591 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 592}
593
594void __init ti81xx_init_late(void)
595{
4ed12be0 596 omap_common_late_init();
23fb8ba3 597 omap2_clk_enable_autoidle_all();
bbd707ac 598}
c4e2d245 599#endif
8f5b5a41 600
a64459c4
AM		 601#ifdef CONFIG_SOC_TI81XX
602void __init ti814x_init_early(void)
603{
604 omap2_set_globals_tap(TI814X_CLASS,
605 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 606 omap2_control_base_init();
a64459c4
AM		 607 omap3xxx_check_revision();
608 ti81xx_check_features();
ab7b2ffc 609 omap2_prcm_base_init();
a64459c4
AM		 610 omap3xxx_voltagedomains_init();
611 omap3xxx_powerdomains_init();
185fde6d 612 ti814x_clockdomains_init();
0f3ccb24 613 dm814x_hwmod_init();
a64459c4 614 omap_hwmod_init_postsetup();
d893656e 615 omap_clk_soc_init = dm814x_dt_clk_init;
a64459c4
AM		 616}
617
618void __init ti816x_init_early(void)
619{
620 omap2_set_globals_tap(TI816X_CLASS,
621 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 622 omap2_control_base_init();
a64459c4
AM		 623 omap3xxx_check_revision();
624 ti81xx_check_features();
ab7b2ffc 625 omap2_prcm_base_init();
a64459c4
AM		 626 omap3xxx_voltagedomains_init();
627 omap3xxx_powerdomains_init();
185fde6d 628 ti816x_clockdomains_init();
0f3ccb24 629 dm816x_hwmod_init();
a64459c4
AM		 630 omap_hwmod_init_postsetup();
631 if (of_have_populated_dt())
9cf705de 632 omap_clk_soc_init = dm816x_dt_clk_init;
a64459c4
AM		 633}
634#endif
635
08f30989
AM		 636#ifdef CONFIG_SOC_AM33XX
637void __init am33xx_init_early(void)
638{
b6a4226c
PW		 639 omap2_set_globals_tap(AM335X_CLASS,
640 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 641 omap2_control_base_init();
08f30989 642 omap3xxx_check_revision();
7bcad170 643 am33xx_check_features();
ab7b2ffc 644 omap2_prcm_base_init();
3f0ea764 645 am33xx_powerdomains_init();
9c80f3aa 646 am33xx_clockdomains_init();
a2cfc509
VH		 647 am33xx_hwmod_init();
648 omap_hwmod_init_postsetup();
149c09d3 649 omap_clk_soc_init = am33xx_dt_clk_init;
08f30989 650}
765e7a06
NM		 651
652void __init am33xx_init_late(void)
653{
654 omap_common_late_init();
655}
08f30989
AM		 656#endif
657
c5107027
AM		 658#ifdef CONFIG_SOC_AM43XX
659void __init am43xx_init_early(void)
660{
661 omap2_set_globals_tap(AM335X_CLASS,
662 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 663 omap2_control_base_init();
c5107027 664 omap3xxx_check_revision();
7a2e0513 665 am33xx_check_features();
ab7b2ffc 666 omap2_prcm_base_init();
8835cf6e
A		 667 am43xx_powerdomains_init();
668 am43xx_clockdomains_init();
669 am43xx_hwmod_init();
670 omap_hwmod_init_postsetup();
d941f86f 671 omap_l2_cache_init();
d22031e2 672 omap_clk_soc_init = am43xx_dt_clk_init;
c5107027 673}
765e7a06
NM		 674
675void __init am43xx_init_late(void)
676{
677 omap_common_late_init();
08224a7d 678 omap2_clk_enable_autoidle_all();
765e7a06 679}
c5107027
AM		 680#endif
681
c4e2d245 682#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 683void __init omap4430_init_early(void)
684{
b6a4226c
PW		 685 omap2_set_globals_tap(OMAP443X_CLASS,
686 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
d9a16f9a 687 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
ca125b5e 688 omap2_control_base_init();
4de34f35
VH		 689 omap4xxx_check_revision();
690 omap4xxx_check_features();
ab7b2ffc 691 omap2_prcm_base_init();
de70af49 692 omap4_pm_init_early();
7b250aff
TL		 693 omap44xx_voltagedomains_init();
694 omap44xx_powerdomains_init();
695 omap44xx_clockdomains_init();
696 omap44xx_hwmod_init();
697 omap_hwmod_init_postsetup();
b39b14e6 698 omap_l2_cache_init();
c8c88d85 699 omap_clk_soc_init = omap4xxx_dt_clk_init;
8f5b5a41 700}
bbd707ac
SG		 701
702void __init omap4430_init_late(void)
703{
4ed12be0 704 omap_common_late_init();
bbd707ac 705 omap4_pm_init();
23fb8ba3 706 omap2_clk_enable_autoidle_all();
bbd707ac 707}
c4e2d245 708#endif
8f5b5a41 709
05e152c7
S		 710#ifdef CONFIG_SOC_OMAP5
711void __init omap5_init_early(void)
712{
b6a4226c
PW		 713 omap2_set_globals_tap(OMAP54XX_CLASS,
714 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
d9a16f9a 715 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 716 omap2_control_base_init();
628ed471 717 omap4_pm_init_early();
ab7b2ffc 718 omap2_prcm_base_init();
05e152c7 719 omap5xxx_check_revision();
e4020aa9
SS		 720 omap54xx_voltagedomains_init();
721 omap54xx_powerdomains_init();
722 omap54xx_clockdomains_init();
723 omap54xx_hwmod_init();
724 omap_hwmod_init_postsetup();
cfa9667d 725 omap_clk_soc_init = omap5xxx_dt_clk_init;
05e152c7 726}
765e7a06
NM		 727
728void __init omap5_init_late(void)
729{
730 omap_common_late_init();
628ed471
SS		 731 omap4_pm_init();
732 omap2_clk_enable_autoidle_all();
765e7a06 733}
05e152c7
S		 734#endif
735
a3a9384a
S		 736#ifdef CONFIG_SOC_DRA7XX
737void __init dra7xx_init_early(void)
738{
739 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
a3a9384a 740 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 741 omap2_control_base_init();
6af16a1d 742 omap4_pm_init_early();
ab7b2ffc 743 omap2_prcm_base_init();
733d20ee 744 dra7xxx_check_revision();
7de516a6
A		 745 dra7xx_powerdomains_init();
746 dra7xx_clockdomains_init();
747 dra7xx_hwmod_init();
748 omap_hwmod_init_postsetup();
f1cf498e 749 omap_clk_soc_init = dra7xx_dt_clk_init;
a3a9384a 750}
765e7a06
NM		 751
752void __init dra7xx_init_late(void)
753{
754 omap_common_late_init();
6af16a1d
RN		 755 omap4_pm_init();
756 omap2_clk_enable_autoidle_all();
765e7a06 757}
a3a9384a
S		 758#endif
759
760
a4ca9dbe 761void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 762 struct omap_sdrc_params *sdrc_cs1)
763{
a66cb345
TL		 764 omap_sram_init();
765
01001712 766 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 767 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
768 _omap2_init_reprogram_sdrc();
769 }
1dbae815 770}
cfa9667d
TK		 771
772int __init omap_clk_init(void)
773{
774 int ret = 0;
775
776 if (!omap_clk_soc_init)
777 return 0;
778
8111e010
TK		 779 ti_clk_init_features();
780
e9e63088
TK		 781 omap2_clk_setup_ll_ops();
782
eded36fe 783 if (of_have_populated_dt()) {
fe87414f
TK		 784 ret = omap_control_init();
785 if (ret)
786 return ret;
787
3a1a388e 788 ret = omap_prcm_init();
eded36fe
TK		 789 if (ret)
790 return ret;
c08ee14c 791
eded36fe 792 of_clk_init(NULL);
c08ee14c 793
eded36fe 794 ti_dt_clk_init_retry_clks();
c08ee14c 795
eded36fe
TK		 796 ti_dt_clockdomains_setup();
797 }
c08ee14c
TK		 798
799 ret = omap_clk_soc_init();
cfa9667d
TK		 800
801 return ret;
802}
Linux kernel - Deliverables
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