Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
45c3eb7d | 28 | #include <linux/omap-dma.h> |
ee0839c2 | 29 | |
dc843280 | 30 | #include "omap_hwmod.h" |
dbc04161 | 31 | #include "soc.h" |
ee0839c2 | 32 | #include "iomap.h" |
81a60482 | 33 | #include "voltage.h" |
72e06d08 | 34 | #include "powerdomain.h" |
1540f214 | 35 | #include "clockdomain.h" |
4e65331c | 36 | #include "common.h" |
e30384ab | 37 | #include "clock.h" |
ee0839c2 TL |
38 | #include "clock2xxx.h" |
39 | #include "clock3xxx.h" | |
40 | #include "clock44xx.h" | |
1d5aef49 | 41 | #include "omap-pm.h" |
3e6ece13 | 42 | #include "sdrc.h" |
b6a4226c | 43 | #include "control.h" |
3d82cbbb | 44 | #include "serial.h" |
bf027ca1 | 45 | #include "sram.h" |
c4ceedcb PW |
46 | #include "cm2xxx.h" |
47 | #include "cm3xxx.h" | |
d9a16f9a PW |
48 | #include "prm.h" |
49 | #include "cm.h" | |
50 | #include "prcm_mpu44xx.h" | |
51 | #include "prminst44xx.h" | |
52 | #include "cminst44xx.h" | |
63a293e0 PW |
53 | #include "prm2xxx.h" |
54 | #include "prm3xxx.h" | |
55 | #include "prm44xx.h" | |
02bfc030 | 56 | |
ff931c82 RN |
57 | /* |
58 | * omap_clk_init: points to a function that does the SoC-specific | |
59 | * clock initializations | |
60 | */ | |
61 | int (*omap_clk_init)(void); | |
62 | ||
1dbae815 TL |
63 | /* |
64 | * The machine specific code may provide the extra mapping besides the | |
65 | * default mapping provided here. | |
66 | */ | |
cc26b3b0 | 67 | |
e48f814e | 68 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 69 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
70 | { |
71 | .virtual = L3_24XX_VIRT, | |
72 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
73 | .length = L3_24XX_SIZE, | |
74 | .type = MT_DEVICE | |
75 | }, | |
09f21ed4 | 76 | { |
cc26b3b0 SMK |
77 | .virtual = L4_24XX_VIRT, |
78 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
79 | .length = L4_24XX_SIZE, | |
80 | .type = MT_DEVICE | |
09f21ed4 | 81 | }, |
cc26b3b0 SMK |
82 | }; |
83 | ||
59b479e0 | 84 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
85 | static struct map_desc omap242x_io_desc[] __initdata = { |
86 | { | |
7adb9987 PW |
87 | .virtual = DSP_MEM_2420_VIRT, |
88 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
89 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
90 | .type = MT_DEVICE |
91 | }, | |
92 | { | |
7adb9987 PW |
93 | .virtual = DSP_IPI_2420_VIRT, |
94 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
95 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 96 | .type = MT_DEVICE |
09f21ed4 | 97 | }, |
cc26b3b0 | 98 | { |
7adb9987 PW |
99 | .virtual = DSP_MMU_2420_VIRT, |
100 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
101 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
102 | .type = MT_DEVICE |
103 | }, | |
104 | }; | |
105 | ||
106 | #endif | |
107 | ||
59b479e0 | 108 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 109 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
110 | { |
111 | .virtual = L4_WK_243X_VIRT, | |
112 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
113 | .length = L4_WK_243X_SIZE, | |
114 | .type = MT_DEVICE | |
115 | }, | |
116 | { | |
117 | .virtual = OMAP243X_GPMC_VIRT, | |
118 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
119 | .length = OMAP243X_GPMC_SIZE, | |
120 | .type = MT_DEVICE | |
121 | }, | |
cc26b3b0 SMK |
122 | { |
123 | .virtual = OMAP243X_SDRC_VIRT, | |
124 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
125 | .length = OMAP243X_SDRC_SIZE, | |
126 | .type = MT_DEVICE | |
127 | }, | |
128 | { | |
129 | .virtual = OMAP243X_SMS_VIRT, | |
130 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
131 | .length = OMAP243X_SMS_SIZE, | |
132 | .type = MT_DEVICE | |
133 | }, | |
134 | }; | |
72d0f1c3 | 135 | #endif |
72d0f1c3 | 136 | #endif |
cc26b3b0 | 137 | |
a8eb7ca0 | 138 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 139 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 140 | { |
cc26b3b0 SMK |
141 | .virtual = L3_34XX_VIRT, |
142 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
143 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
144 | .type = MT_DEVICE |
145 | }, | |
146 | { | |
cc26b3b0 SMK |
147 | .virtual = L4_34XX_VIRT, |
148 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
149 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
150 | .type = MT_DEVICE |
151 | }, | |
cc26b3b0 SMK |
152 | { |
153 | .virtual = OMAP34XX_GPMC_VIRT, | |
154 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
155 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 156 | .type = MT_DEVICE |
cc26b3b0 SMK |
157 | }, |
158 | { | |
159 | .virtual = OMAP343X_SMS_VIRT, | |
160 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
161 | .length = OMAP343X_SMS_SIZE, | |
162 | .type = MT_DEVICE | |
163 | }, | |
164 | { | |
165 | .virtual = OMAP343X_SDRC_VIRT, | |
166 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
167 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 168 | .type = MT_DEVICE |
cc26b3b0 SMK |
169 | }, |
170 | { | |
171 | .virtual = L4_PER_34XX_VIRT, | |
172 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
173 | .length = L4_PER_34XX_SIZE, | |
174 | .type = MT_DEVICE | |
175 | }, | |
176 | { | |
177 | .virtual = L4_EMU_34XX_VIRT, | |
178 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
179 | .length = L4_EMU_34XX_SIZE, | |
180 | .type = MT_DEVICE | |
181 | }, | |
a4f57b81 TL |
182 | #if defined(CONFIG_DEBUG_LL) && \ |
183 | (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) | |
184 | { | |
185 | .virtual = ZOOM_UART_VIRT, | |
186 | .pfn = __phys_to_pfn(ZOOM_UART_BASE), | |
187 | .length = SZ_1M, | |
188 | .type = MT_DEVICE | |
189 | }, | |
190 | #endif | |
1dbae815 | 191 | }; |
cc26b3b0 | 192 | #endif |
01001712 | 193 | |
33959553 | 194 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 195 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
196 | { |
197 | .virtual = L4_34XX_VIRT, | |
198 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
199 | .length = L4_34XX_SIZE, | |
200 | .type = MT_DEVICE | |
201 | } | |
202 | }; | |
203 | #endif | |
204 | ||
bb6abcf4 | 205 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 | 206 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
207 | { |
208 | .virtual = L4_34XX_VIRT, | |
209 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
210 | .length = L4_34XX_SIZE, | |
211 | .type = MT_DEVICE | |
212 | }, | |
1e6cb146 AM |
213 | { |
214 | .virtual = L4_WK_AM33XX_VIRT, | |
215 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
216 | .length = L4_WK_AM33XX_SIZE, | |
217 | .type = MT_DEVICE | |
218 | } | |
01001712 HP |
219 | }; |
220 | #endif | |
221 | ||
44169075 SS |
222 | #ifdef CONFIG_ARCH_OMAP4 |
223 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
224 | { | |
225 | .virtual = L3_44XX_VIRT, | |
226 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
227 | .length = L3_44XX_SIZE, | |
228 | .type = MT_DEVICE, | |
229 | }, | |
230 | { | |
231 | .virtual = L4_44XX_VIRT, | |
232 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
233 | .length = L4_44XX_SIZE, | |
234 | .type = MT_DEVICE, | |
235 | }, | |
44169075 SS |
236 | { |
237 | .virtual = L4_PER_44XX_VIRT, | |
238 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
239 | .length = L4_PER_44XX_SIZE, | |
240 | .type = MT_DEVICE, | |
241 | }, | |
137d105d SS |
242 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
243 | { | |
244 | .virtual = OMAP4_SRAM_VA, | |
245 | .pfn = __phys_to_pfn(OMAP4_SRAM_PA), | |
246 | .length = PAGE_SIZE, | |
247 | .type = MT_MEMORY_SO, | |
248 | }, | |
249 | #endif | |
250 | ||
44169075 SS |
251 | }; |
252 | #endif | |
1dbae815 | 253 | |
05e152c7 S |
254 | #ifdef CONFIG_SOC_OMAP5 |
255 | static struct map_desc omap54xx_io_desc[] __initdata = { | |
256 | { | |
257 | .virtual = L3_54XX_VIRT, | |
258 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
259 | .length = L3_54XX_SIZE, | |
260 | .type = MT_DEVICE, | |
261 | }, | |
262 | { | |
263 | .virtual = L4_54XX_VIRT, | |
264 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
265 | .length = L4_54XX_SIZE, | |
266 | .type = MT_DEVICE, | |
267 | }, | |
268 | { | |
269 | .virtual = L4_WK_54XX_VIRT, | |
270 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
271 | .length = L4_WK_54XX_SIZE, | |
272 | .type = MT_DEVICE, | |
273 | }, | |
274 | { | |
275 | .virtual = L4_PER_54XX_VIRT, | |
276 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
277 | .length = L4_PER_54XX_SIZE, | |
278 | .type = MT_DEVICE, | |
279 | }, | |
280 | }; | |
281 | #endif | |
282 | ||
59b479e0 | 283 | #ifdef CONFIG_SOC_OMAP2420 |
b6a4226c | 284 | void __init omap242x_map_io(void) |
1dbae815 | 285 | { |
cc26b3b0 SMK |
286 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
287 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 288 | } |
cc26b3b0 SMK |
289 | #endif |
290 | ||
59b479e0 | 291 | #ifdef CONFIG_SOC_OMAP2430 |
b6a4226c | 292 | void __init omap243x_map_io(void) |
6fbd55d0 | 293 | { |
cc26b3b0 SMK |
294 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
295 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 296 | } |
cc26b3b0 SMK |
297 | #endif |
298 | ||
a8eb7ca0 | 299 | #ifdef CONFIG_ARCH_OMAP3 |
b6a4226c | 300 | void __init omap3_map_io(void) |
6fbd55d0 | 301 | { |
cc26b3b0 | 302 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 303 | } |
cc26b3b0 | 304 | #endif |
120db2cb | 305 | |
33959553 | 306 | #ifdef CONFIG_SOC_TI81XX |
b6a4226c | 307 | void __init ti81xx_map_io(void) |
01001712 | 308 | { |
a920360f | 309 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
310 | } |
311 | #endif | |
312 | ||
bb6abcf4 | 313 | #ifdef CONFIG_SOC_AM33XX |
b6a4226c | 314 | void __init am33xx_map_io(void) |
01001712 | 315 | { |
1e6cb146 | 316 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
317 | } |
318 | #endif | |
319 | ||
6fbd55d0 | 320 | #ifdef CONFIG_ARCH_OMAP4 |
b6a4226c | 321 | void __init omap4_map_io(void) |
6fbd55d0 | 322 | { |
44169075 | 323 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
2ec1fc4e | 324 | omap_barriers_init(); |
120db2cb | 325 | } |
6fbd55d0 | 326 | #endif |
120db2cb | 327 | |
05e152c7 | 328 | #ifdef CONFIG_SOC_OMAP5 |
b6a4226c | 329 | void __init omap5_map_io(void) |
05e152c7 S |
330 | { |
331 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
332 | } | |
333 | #endif | |
2f135eaf PW |
334 | /* |
335 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
336 | * | |
337 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
338 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
339 | * registers to the values currently defined by the kernel. Currently | |
340 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
341 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
342 | * or passes along the return value of clk_set_rate(). | |
343 | */ | |
344 | static int __init _omap2_init_reprogram_sdrc(void) | |
345 | { | |
346 | struct clk *dpll3_m2_ck; | |
347 | int v = -EINVAL; | |
348 | long rate; | |
349 | ||
350 | if (!cpu_is_omap34xx()) | |
351 | return 0; | |
352 | ||
353 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 354 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
355 | return -EINVAL; |
356 | ||
357 | rate = clk_get_rate(dpll3_m2_ck); | |
358 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
359 | v = clk_set_rate(dpll3_m2_ck, rate); | |
360 | if (v) | |
361 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
362 | ||
363 | clk_put(dpll3_m2_ck); | |
364 | ||
365 | return v; | |
366 | } | |
367 | ||
2092e5cc PW |
368 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
369 | { | |
370 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
371 | } | |
372 | ||
7b250aff TL |
373 | static void __init omap_hwmod_init_postsetup(void) |
374 | { | |
375 | u8 postsetup_state; | |
2092e5cc PW |
376 | |
377 | /* Set the default postsetup state for all hwmods */ | |
378 | #ifdef CONFIG_PM_RUNTIME | |
379 | postsetup_state = _HWMOD_STATE_IDLE; | |
380 | #else | |
381 | postsetup_state = _HWMOD_STATE_ENABLED; | |
382 | #endif | |
383 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 384 | |
53da4ce2 | 385 | omap_pm_if_early_init(); |
4805734b PW |
386 | } |
387 | ||
16110798 | 388 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
389 | void __init omap2420_init_early(void) |
390 | { | |
b6a4226c PW |
391 | omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); |
392 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | |
393 | OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); | |
394 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), | |
395 | NULL); | |
d9a16f9a PW |
396 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); |
397 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); | |
4de34f35 | 398 | omap2xxx_check_revision(); |
63a293e0 | 399 | omap2xxx_prm_init(); |
c4ceedcb | 400 | omap2xxx_cm_init(); |
7b250aff TL |
401 | omap2xxx_voltagedomains_init(); |
402 | omap242x_powerdomains_init(); | |
403 | omap242x_clockdomains_init(); | |
404 | omap2420_hwmod_init(); | |
405 | omap_hwmod_init_postsetup(); | |
ff931c82 | 406 | omap_clk_init = omap2420_clk_init; |
8f5b5a41 | 407 | } |
bbd707ac SG |
408 | |
409 | void __init omap2420_init_late(void) | |
410 | { | |
411 | omap_mux_late_init(); | |
412 | omap2_common_pm_late_init(); | |
413 | omap2_pm_init(); | |
23fb8ba3 | 414 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 415 | } |
16110798 | 416 | #endif |
8f5b5a41 | 417 | |
16110798 | 418 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
419 | void __init omap2430_init_early(void) |
420 | { | |
b6a4226c PW |
421 | omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); |
422 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | |
423 | OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); | |
424 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), | |
425 | NULL); | |
d9a16f9a PW |
426 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); |
427 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); | |
4de34f35 | 428 | omap2xxx_check_revision(); |
63a293e0 | 429 | omap2xxx_prm_init(); |
c4ceedcb | 430 | omap2xxx_cm_init(); |
7b250aff TL |
431 | omap2xxx_voltagedomains_init(); |
432 | omap243x_powerdomains_init(); | |
433 | omap243x_clockdomains_init(); | |
434 | omap2430_hwmod_init(); | |
435 | omap_hwmod_init_postsetup(); | |
ff931c82 | 436 | omap_clk_init = omap2430_clk_init; |
7b250aff | 437 | } |
bbd707ac SG |
438 | |
439 | void __init omap2430_init_late(void) | |
440 | { | |
441 | omap_mux_late_init(); | |
442 | omap2_common_pm_late_init(); | |
443 | omap2_pm_init(); | |
23fb8ba3 | 444 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 445 | } |
c4e2d245 | 446 | #endif |
7b250aff TL |
447 | |
448 | /* | |
449 | * Currently only board-omap3beagle.c should call this because of the | |
450 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
451 | */ | |
c4e2d245 | 452 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
453 | void __init omap3_init_early(void) |
454 | { | |
b6a4226c PW |
455 | omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); |
456 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | |
457 | OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); | |
458 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), | |
459 | NULL); | |
d9a16f9a PW |
460 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); |
461 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); | |
4de34f35 VH |
462 | omap3xxx_check_revision(); |
463 | omap3xxx_check_features(); | |
63a293e0 | 464 | omap3xxx_prm_init(); |
c4ceedcb | 465 | omap3xxx_cm_init(); |
7b250aff TL |
466 | omap3xxx_voltagedomains_init(); |
467 | omap3xxx_powerdomains_init(); | |
468 | omap3xxx_clockdomains_init(); | |
469 | omap3xxx_hwmod_init(); | |
470 | omap_hwmod_init_postsetup(); | |
ff931c82 | 471 | omap_clk_init = omap3xxx_clk_init; |
8f5b5a41 TL |
472 | } |
473 | ||
474 | void __init omap3430_init_early(void) | |
475 | { | |
7b250aff | 476 | omap3_init_early(); |
8f5b5a41 TL |
477 | } |
478 | ||
479 | void __init omap35xx_init_early(void) | |
480 | { | |
7b250aff | 481 | omap3_init_early(); |
8f5b5a41 TL |
482 | } |
483 | ||
484 | void __init omap3630_init_early(void) | |
485 | { | |
7b250aff | 486 | omap3_init_early(); |
8f5b5a41 TL |
487 | } |
488 | ||
489 | void __init am35xx_init_early(void) | |
490 | { | |
7b250aff | 491 | omap3_init_early(); |
8f5b5a41 TL |
492 | } |
493 | ||
a920360f | 494 | void __init ti81xx_init_early(void) |
8f5b5a41 | 495 | { |
b6a4226c PW |
496 | omap2_set_globals_tap(OMAP343X_CLASS, |
497 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
498 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), | |
499 | NULL); | |
d9a16f9a PW |
500 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); |
501 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); | |
4de34f35 VH |
502 | omap3xxx_check_revision(); |
503 | ti81xx_check_features(); | |
4c3cf901 TL |
504 | omap3xxx_voltagedomains_init(); |
505 | omap3xxx_powerdomains_init(); | |
506 | omap3xxx_clockdomains_init(); | |
507 | omap3xxx_hwmod_init(); | |
508 | omap_hwmod_init_postsetup(); | |
ff931c82 | 509 | omap_clk_init = omap3xxx_clk_init; |
8f5b5a41 | 510 | } |
bbd707ac SG |
511 | |
512 | void __init omap3_init_late(void) | |
513 | { | |
514 | omap_mux_late_init(); | |
515 | omap2_common_pm_late_init(); | |
516 | omap3_pm_init(); | |
23fb8ba3 | 517 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
518 | } |
519 | ||
520 | void __init omap3430_init_late(void) | |
521 | { | |
522 | omap_mux_late_init(); | |
523 | omap2_common_pm_late_init(); | |
524 | omap3_pm_init(); | |
23fb8ba3 | 525 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
526 | } |
527 | ||
528 | void __init omap35xx_init_late(void) | |
529 | { | |
530 | omap_mux_late_init(); | |
531 | omap2_common_pm_late_init(); | |
532 | omap3_pm_init(); | |
23fb8ba3 | 533 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
534 | } |
535 | ||
536 | void __init omap3630_init_late(void) | |
537 | { | |
538 | omap_mux_late_init(); | |
539 | omap2_common_pm_late_init(); | |
540 | omap3_pm_init(); | |
23fb8ba3 | 541 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
542 | } |
543 | ||
544 | void __init am35xx_init_late(void) | |
545 | { | |
546 | omap_mux_late_init(); | |
547 | omap2_common_pm_late_init(); | |
548 | omap3_pm_init(); | |
23fb8ba3 | 549 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
550 | } |
551 | ||
552 | void __init ti81xx_init_late(void) | |
553 | { | |
554 | omap_mux_late_init(); | |
555 | omap2_common_pm_late_init(); | |
556 | omap3_pm_init(); | |
23fb8ba3 | 557 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 558 | } |
c4e2d245 | 559 | #endif |
8f5b5a41 | 560 | |
08f30989 AM |
561 | #ifdef CONFIG_SOC_AM33XX |
562 | void __init am33xx_init_early(void) | |
563 | { | |
b6a4226c PW |
564 | omap2_set_globals_tap(AM335X_CLASS, |
565 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
566 | omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), | |
567 | NULL); | |
d9a16f9a PW |
568 | omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); |
569 | omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); | |
08f30989 AM |
570 | omap3xxx_check_revision(); |
571 | ti81xx_check_features(); | |
ce3fc89a | 572 | am33xx_voltagedomains_init(); |
3f0ea764 | 573 | am33xx_powerdomains_init(); |
9c80f3aa | 574 | am33xx_clockdomains_init(); |
a2cfc509 VH |
575 | am33xx_hwmod_init(); |
576 | omap_hwmod_init_postsetup(); | |
ff931c82 | 577 | omap_clk_init = am33xx_clk_init; |
08f30989 AM |
578 | } |
579 | #endif | |
580 | ||
c4e2d245 | 581 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
582 | void __init omap4430_init_early(void) |
583 | { | |
b6a4226c PW |
584 | omap2_set_globals_tap(OMAP443X_CLASS, |
585 | OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); | |
586 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), | |
587 | OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); | |
d9a16f9a PW |
588 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); |
589 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), | |
590 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); | |
591 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); | |
592 | omap_prm_base_init(); | |
593 | omap_cm_base_init(); | |
4de34f35 VH |
594 | omap4xxx_check_revision(); |
595 | omap4xxx_check_features(); | |
63a293e0 | 596 | omap44xx_prm_init(); |
7b250aff TL |
597 | omap44xx_voltagedomains_init(); |
598 | omap44xx_powerdomains_init(); | |
599 | omap44xx_clockdomains_init(); | |
600 | omap44xx_hwmod_init(); | |
601 | omap_hwmod_init_postsetup(); | |
ff931c82 | 602 | omap_clk_init = omap4xxx_clk_init; |
8f5b5a41 | 603 | } |
bbd707ac SG |
604 | |
605 | void __init omap4430_init_late(void) | |
606 | { | |
607 | omap_mux_late_init(); | |
608 | omap2_common_pm_late_init(); | |
609 | omap4_pm_init(); | |
23fb8ba3 | 610 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 611 | } |
c4e2d245 | 612 | #endif |
8f5b5a41 | 613 | |
05e152c7 S |
614 | #ifdef CONFIG_SOC_OMAP5 |
615 | void __init omap5_init_early(void) | |
616 | { | |
b6a4226c PW |
617 | omap2_set_globals_tap(OMAP54XX_CLASS, |
618 | OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); | |
619 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), | |
620 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); | |
d9a16f9a PW |
621 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); |
622 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), | |
623 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); | |
624 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); | |
625 | omap_prm_base_init(); | |
626 | omap_cm_base_init(); | |
05e152c7 | 627 | omap5xxx_check_revision(); |
05e152c7 S |
628 | } |
629 | #endif | |
630 | ||
a4ca9dbe | 631 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
632 | struct omap_sdrc_params *sdrc_cs1) |
633 | { | |
a66cb345 TL |
634 | omap_sram_init(); |
635 | ||
01001712 | 636 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
637 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
638 | _omap2_init_reprogram_sdrc(); | |
639 | } | |
1dbae815 | 640 | } |