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Merge branch 'next/cross-platform' of git://git.linaro.org/people/arnd/arm-soc
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
91773a00 24#include <linux/omapfb.h>
1dbae815 25
120db2cb 26#include <asm/tlb.h>
120db2cb
TL		 27
28#include <asm/mach/map.h>
29
ce491cf8
TL		 30#include <plat/sram.h>
31#include <plat/sdrc.h>
ce491cf8 32#include <plat/serial.h>
646e3ed1 33
e80a9729 34#include "clock2xxx.h"
657ebfad 35#include "clock3xxx.h"
e80a9729 36#include "clock44xx.h"
b0a330dc 37#include "io.h"
1dbae815 38
ce491cf8 39#include <plat/omap-pm.h>
81a60482 40#include "voltage.h"
72e06d08 41#include "powerdomain.h"
1dbae815 42
1540f214 43#include "clockdomain.h"
ce491cf8 44#include <plat/omap_hwmod.h>
5d190c40 45#include <plat/multi.h>
02bfc030 46
1dbae815
TL		 47/*
48 * The machine specific code may provide the extra mapping besides the
49 * default mapping provided here.
50 */
cc26b3b0 51
088ef950 52#ifdef CONFIG_ARCH_OMAP2
cc26b3b0 53static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 54 {
55 .virtual = L3_24XX_VIRT,
56 .pfn = __phys_to_pfn(L3_24XX_PHYS),
57 .length = L3_24XX_SIZE,
58 .type = MT_DEVICE
59 },
09f21ed4 60 {
cc26b3b0
SMK		 61 .virtual = L4_24XX_VIRT,
62 .pfn = __phys_to_pfn(L4_24XX_PHYS),
63 .length = L4_24XX_SIZE,
64 .type = MT_DEVICE
09f21ed4 65 },
cc26b3b0
SMK		 66};
67
59b479e0 68#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 69static struct map_desc omap242x_io_desc[] __initdata = {
70 {
7adb9987
PW		 71 .virtual = DSP_MEM_2420_VIRT,
72 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
73 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 74 .type = MT_DEVICE
75 },
76 {
7adb9987
PW		 77 .virtual = DSP_IPI_2420_VIRT,
78 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
79 .length = DSP_IPI_2420_SIZE,
cc26b3b0 80 .type = MT_DEVICE
09f21ed4 81 },
cc26b3b0 82 {
7adb9987
PW		 83 .virtual = DSP_MMU_2420_VIRT,
84 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
85 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 86 .type = MT_DEVICE
87 },
88};
89
90#endif
91
59b479e0 92#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 93static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 94 {
95 .virtual = L4_WK_243X_VIRT,
96 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
97 .length = L4_WK_243X_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = OMAP243X_GPMC_VIRT,
102 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
103 .length = OMAP243X_GPMC_SIZE,
104 .type = MT_DEVICE
105 },
cc26b3b0
SMK		 106 {
107 .virtual = OMAP243X_SDRC_VIRT,
108 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
109 .length = OMAP243X_SDRC_SIZE,
110 .type = MT_DEVICE
111 },
112 {
113 .virtual = OMAP243X_SMS_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
115 .length = OMAP243X_SMS_SIZE,
116 .type = MT_DEVICE
117 },
118};
72d0f1c3 119#endif
72d0f1c3 120#endif
cc26b3b0 121
a8eb7ca0 122#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 123static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 124 {
cc26b3b0
SMK		 125 .virtual = L3_34XX_VIRT,
126 .pfn = __phys_to_pfn(L3_34XX_PHYS),
127 .length = L3_34XX_SIZE,
c40fae95
TL		 128 .type = MT_DEVICE
129 },
130 {
cc26b3b0
SMK		 131 .virtual = L4_34XX_VIRT,
132 .pfn = __phys_to_pfn(L4_34XX_PHYS),
133 .length = L4_34XX_SIZE,
c40fae95
TL		 134 .type = MT_DEVICE
135 },
cc26b3b0
SMK		 136 {
137 .virtual = OMAP34XX_GPMC_VIRT,
138 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
139 .length = OMAP34XX_GPMC_SIZE,
1dbae815 140 .type = MT_DEVICE
cc26b3b0
SMK		 141 },
142 {
143 .virtual = OMAP343X_SMS_VIRT,
144 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
145 .length = OMAP343X_SMS_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = OMAP343X_SDRC_VIRT,
150 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
151 .length = OMAP343X_SDRC_SIZE,
1dbae815 152 .type = MT_DEVICE
cc26b3b0
SMK		 153 },
154 {
155 .virtual = L4_PER_34XX_VIRT,
156 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
157 .length = L4_PER_34XX_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = L4_EMU_34XX_VIRT,
162 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
163 .length = L4_EMU_34XX_SIZE,
164 .type = MT_DEVICE
165 },
a4f57b81
TL		 166#if defined(CONFIG_DEBUG_LL) && \
167 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
168 {
169 .virtual = ZOOM_UART_VIRT,
170 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
171 .length = SZ_1M,
172 .type = MT_DEVICE
173 },
174#endif
1dbae815 175};
cc26b3b0 176#endif
01001712
HP		 177
178#ifdef CONFIG_SOC_OMAPTI816X
179static struct map_desc omapti816x_io_desc[] __initdata = {
180 {
181 .virtual = L4_34XX_VIRT,
182 .pfn = __phys_to_pfn(L4_34XX_PHYS),
183 .length = L4_34XX_SIZE,
184 .type = MT_DEVICE
185 },
186};
187#endif
188
44169075
SS		 189#ifdef CONFIG_ARCH_OMAP4
190static struct map_desc omap44xx_io_desc[] __initdata = {
191 {
192 .virtual = L3_44XX_VIRT,
193 .pfn = __phys_to_pfn(L3_44XX_PHYS),
194 .length = L3_44XX_SIZE,
195 .type = MT_DEVICE,
196 },
197 {
198 .virtual = L4_44XX_VIRT,
199 .pfn = __phys_to_pfn(L4_44XX_PHYS),
200 .length = L4_44XX_SIZE,
201 .type = MT_DEVICE,
202 },
44169075
SS		 203 {
204 .virtual = OMAP44XX_GPMC_VIRT,
205 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
206 .length = OMAP44XX_GPMC_SIZE,
207 .type = MT_DEVICE,
208 },
f5d2d659
SS		 209 {
210 .virtual = OMAP44XX_EMIF1_VIRT,
211 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
212 .length = OMAP44XX_EMIF1_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = OMAP44XX_EMIF2_VIRT,
217 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
218 .length = OMAP44XX_EMIF2_SIZE,
219 .type = MT_DEVICE,
220 },
221 {
222 .virtual = OMAP44XX_DMM_VIRT,
223 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
224 .length = OMAP44XX_DMM_SIZE,
225 .type = MT_DEVICE,
226 },
44169075
SS		 227 {
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
233 {
234 .virtual = L4_EMU_44XX_VIRT,
235 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
236 .length = L4_EMU_44XX_SIZE,
237 .type = MT_DEVICE,
238 },
239};
240#endif
1dbae815 241
6fbd55d0
TL		 242static void __init _omap2_map_common_io(void)
243{
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
247 */
248 local_flush_tlb_all();
249 flush_cache_all();
250
251 omap2_check_revision();
252 omap_sram_init();
009426a0 253 omap_init_consistent_dma_size();
6fbd55d0
TL		 254}
255
59b479e0 256#ifdef CONFIG_SOC_OMAP2420
8185e468 257void __init omap242x_map_common_io(void)
1dbae815 258{
cc26b3b0
SMK		 259 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
260 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0
TL		 261 _omap2_map_common_io();
262}
cc26b3b0
SMK		 263#endif
264
59b479e0 265#ifdef CONFIG_SOC_OMAP2430
8185e468 266void __init omap243x_map_common_io(void)
6fbd55d0 267{
cc26b3b0
SMK		 268 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
269 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0
TL		 270 _omap2_map_common_io();
271}
cc26b3b0
SMK		 272#endif
273
a8eb7ca0 274#ifdef CONFIG_ARCH_OMAP3
8185e468 275void __init omap34xx_map_common_io(void)
6fbd55d0 276{
cc26b3b0 277 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0
TL		 278 _omap2_map_common_io();
279}
cc26b3b0 280#endif
120db2cb 281
01001712
HP		 282#ifdef CONFIG_SOC_OMAPTI816X
283void __init omapti816x_map_common_io(void)
284{
285 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
286 _omap2_map_common_io();
287}
288#endif
289
6fbd55d0 290#ifdef CONFIG_ARCH_OMAP4
8185e468 291void __init omap44xx_map_common_io(void)
6fbd55d0 292{
44169075 293 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
6fbd55d0 294 _omap2_map_common_io();
120db2cb 295}
6fbd55d0 296#endif
120db2cb 297
2f135eaf
PW		 298/*
299 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
300 *
301 * Sets the CORE DPLL3 M2 divider to the same value that it's at
302 * currently. This has the effect of setting the SDRC SDRAM AC timing
303 * registers to the values currently defined by the kernel. Currently
304 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
305 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
306 * or passes along the return value of clk_set_rate().
307 */
308static int __init _omap2_init_reprogram_sdrc(void)
309{
310 struct clk *dpll3_m2_ck;
311 int v = -EINVAL;
312 long rate;
313
314 if (!cpu_is_omap34xx())
315 return 0;
316
317 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 318 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 319 return -EINVAL;
320
321 rate = clk_get_rate(dpll3_m2_ck);
322 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
323 v = clk_set_rate(dpll3_m2_ck, rate);
324 if (v)
325 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
326
327 clk_put(dpll3_m2_ck);
328
329 return v;
330}
331
2092e5cc
PW		 332static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
333{
334 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
335}
336
741e3a89 337/* See irq.c, omap4-common.c and entry-macro.S */
9f9605c2
RK		 338void __iomem *omap_irq_base;
339
4805734b 340void __init omap2_init_common_infrastructure(void)
120db2cb 341{
2092e5cc
PW		 342 u8 postsetup_state;
343
6e01478a 344 if (cpu_is_omap242x()) {
aae030fa 345 omap2xxx_voltagedomains_init();
8179488a 346 omap242x_powerdomains_init();
a5ffef6a 347 omap242x_clockdomains_init();
7359154e 348 omap2420_hwmod_init();
6e01478a 349 } else if (cpu_is_omap243x()) {
aae030fa 350 omap2xxx_voltagedomains_init();
8179488a 351 omap243x_powerdomains_init();
a5ffef6a 352 omap243x_clockdomains_init();
7359154e 353 omap2430_hwmod_init();
6e01478a 354 } else if (cpu_is_omap34xx()) {
81a60482 355 omap3xxx_voltagedomains_init();
6e01478a 356 omap3xxx_powerdomains_init();
4aef7a2a 357 omap3xxx_clockdomains_init();
7359154e 358 omap3xxx_hwmod_init();
6e01478a 359 } else if (cpu_is_omap44xx()) {
81a60482 360 omap44xx_voltagedomains_init();
6e01478a 361 omap44xx_powerdomains_init();
dc0b3a70 362 omap44xx_clockdomains_init();
55d2cb08 363 omap44xx_hwmod_init();
6e01478a 364 } else {
2092e5cc 365 pr_err("Could not init hwmod data - unknown SoC\n");
6e01478a 366 }
2092e5cc
PW		 367
368 /* Set the default postsetup state for all hwmods */
369#ifdef CONFIG_PM_RUNTIME
370 postsetup_state = _HWMOD_STATE_IDLE;
371#else
372 postsetup_state = _HWMOD_STATE_ENABLED;
373#endif
374 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 375
ff2516fb
PW		 376 /*
377 * Set the default postsetup state for unusual modules (like
378 * MPU WDT).
379 *
380 * The postsetup_state is not actually used until
381 * omap_hwmod_late_init(), so boards that desire full watchdog
382 * coverage of kernel initialization can reprogram the
383 * postsetup_state between the calls to
a4ca9dbe 384 * omap2_init_common_infra() and omap_sdrc_init().
ff2516fb
PW		 385 *
386 * XXX ideally we could detect whether the MPU WDT was currently
387 * enabled here and make this conditional
388 */
389 postsetup_state = _HWMOD_STATE_DISABLED;
390 omap_hwmod_for_each_by_class("wd_timer",
391 _set_hwmod_postsetup_state,
392 &postsetup_state);
393
53da4ce2 394 omap_pm_if_early_init();
e80a9729 395
81b34fbe
PW		 396 if (cpu_is_omap2420())
397 omap2420_clk_init();
398 else if (cpu_is_omap2430())
399 omap2430_clk_init();
e80a9729
PW		 400 else if (cpu_is_omap34xx())
401 omap3xxx_clk_init();
402 else if (cpu_is_omap44xx())
403 omap4xxx_clk_init();
404 else
2092e5cc 405 pr_err("Could not init clock framework - unknown SoC\n");
4805734b
PW		 406}
407
8f5b5a41
TL		 408void __init omap2420_init_early(void)
409{
410 omap2_init_common_infrastructure();
411}
412
413void __init omap2430_init_early(void)
414{
415 omap2_init_common_infrastructure();
416}
417
418void __init omap3430_init_early(void)
419{
420 omap2_init_common_infrastructure();
421}
422
423void __init omap35xx_init_early(void)
424{
425 omap2_init_common_infrastructure();
426}
427
428void __init omap3630_init_early(void)
429{
430 omap2_init_common_infrastructure();
431}
432
433void __init am35xx_init_early(void)
434{
435 omap2_init_common_infrastructure();
436}
437
438void __init ti816x_init_early(void)
439{
440 omap2_init_common_infrastructure();
441}
442
443void __init omap4430_init_early(void)
444{
445 omap2_init_common_infrastructure();
446}
447
a4ca9dbe 448void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 449 struct omap_sdrc_params *sdrc_cs1)
450{
01001712 451 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 452 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
453 _omap2_init_reprogram_sdrc();
454 }
5d190c40 455
1dbae815 456}
df1e9d1c
TL		 457
458/*
459 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
460 */
461
462u8 omap_readb(u32 pa)
463{
464 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
465}
466EXPORT_SYMBOL(omap_readb);
467
468u16 omap_readw(u32 pa)
469{
470 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
471}
472EXPORT_SYMBOL(omap_readw);
473
474u32 omap_readl(u32 pa)
475{
476 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
477}
478EXPORT_SYMBOL(omap_readl);
479
480void omap_writeb(u8 v, u32 pa)
481{
482 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
483}
484EXPORT_SYMBOL(omap_writeb);
485
486void omap_writew(u16 v, u32 pa)
487{
488 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
489}
490EXPORT_SYMBOL(omap_writew);
491
492void omap_writel(u32 v, u32 pa)
493{
494 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
495}
496EXPORT_SYMBOL(omap_writel);
Linux kernel - Deliverables
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