Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
ce491cf8 TL |
28 | #include <plat/sram.h> |
29 | #include <plat/sdrc.h> | |
ce491cf8 | 30 | #include <plat/serial.h> |
ce491cf8 | 31 | #include <plat/omap-pm.h> |
ee0839c2 TL |
32 | #include <plat/omap_hwmod.h> |
33 | #include <plat/multi.h> | |
e2ed89fc | 34 | #include <plat/dma.h> |
ee0839c2 TL |
35 | |
36 | #include "iomap.h" | |
81a60482 | 37 | #include "voltage.h" |
72e06d08 | 38 | #include "powerdomain.h" |
1540f214 | 39 | #include "clockdomain.h" |
4e65331c | 40 | #include "common.h" |
e30384ab | 41 | #include "clock.h" |
ee0839c2 TL |
42 | #include "clock2xxx.h" |
43 | #include "clock3xxx.h" | |
44 | #include "clock44xx.h" | |
02bfc030 | 45 | |
1dbae815 TL |
46 | /* |
47 | * The machine specific code may provide the extra mapping besides the | |
48 | * default mapping provided here. | |
49 | */ | |
cc26b3b0 | 50 | |
e48f814e | 51 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 52 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
53 | { |
54 | .virtual = L3_24XX_VIRT, | |
55 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
56 | .length = L3_24XX_SIZE, | |
57 | .type = MT_DEVICE | |
58 | }, | |
09f21ed4 | 59 | { |
cc26b3b0 SMK |
60 | .virtual = L4_24XX_VIRT, |
61 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
62 | .length = L4_24XX_SIZE, | |
63 | .type = MT_DEVICE | |
09f21ed4 | 64 | }, |
cc26b3b0 SMK |
65 | }; |
66 | ||
59b479e0 | 67 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
68 | static struct map_desc omap242x_io_desc[] __initdata = { |
69 | { | |
7adb9987 PW |
70 | .virtual = DSP_MEM_2420_VIRT, |
71 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
72 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
73 | .type = MT_DEVICE |
74 | }, | |
75 | { | |
7adb9987 PW |
76 | .virtual = DSP_IPI_2420_VIRT, |
77 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
78 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 79 | .type = MT_DEVICE |
09f21ed4 | 80 | }, |
cc26b3b0 | 81 | { |
7adb9987 PW |
82 | .virtual = DSP_MMU_2420_VIRT, |
83 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
84 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
85 | .type = MT_DEVICE |
86 | }, | |
87 | }; | |
88 | ||
89 | #endif | |
90 | ||
59b479e0 | 91 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 92 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
93 | { |
94 | .virtual = L4_WK_243X_VIRT, | |
95 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
96 | .length = L4_WK_243X_SIZE, | |
97 | .type = MT_DEVICE | |
98 | }, | |
99 | { | |
100 | .virtual = OMAP243X_GPMC_VIRT, | |
101 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
102 | .length = OMAP243X_GPMC_SIZE, | |
103 | .type = MT_DEVICE | |
104 | }, | |
cc26b3b0 SMK |
105 | { |
106 | .virtual = OMAP243X_SDRC_VIRT, | |
107 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
108 | .length = OMAP243X_SDRC_SIZE, | |
109 | .type = MT_DEVICE | |
110 | }, | |
111 | { | |
112 | .virtual = OMAP243X_SMS_VIRT, | |
113 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
114 | .length = OMAP243X_SMS_SIZE, | |
115 | .type = MT_DEVICE | |
116 | }, | |
117 | }; | |
72d0f1c3 | 118 | #endif |
72d0f1c3 | 119 | #endif |
cc26b3b0 | 120 | |
a8eb7ca0 | 121 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 122 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 123 | { |
cc26b3b0 SMK |
124 | .virtual = L3_34XX_VIRT, |
125 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
126 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
127 | .type = MT_DEVICE |
128 | }, | |
129 | { | |
cc26b3b0 SMK |
130 | .virtual = L4_34XX_VIRT, |
131 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
132 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
133 | .type = MT_DEVICE |
134 | }, | |
cc26b3b0 SMK |
135 | { |
136 | .virtual = OMAP34XX_GPMC_VIRT, | |
137 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
138 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 139 | .type = MT_DEVICE |
cc26b3b0 SMK |
140 | }, |
141 | { | |
142 | .virtual = OMAP343X_SMS_VIRT, | |
143 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
144 | .length = OMAP343X_SMS_SIZE, | |
145 | .type = MT_DEVICE | |
146 | }, | |
147 | { | |
148 | .virtual = OMAP343X_SDRC_VIRT, | |
149 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
150 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 151 | .type = MT_DEVICE |
cc26b3b0 SMK |
152 | }, |
153 | { | |
154 | .virtual = L4_PER_34XX_VIRT, | |
155 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
156 | .length = L4_PER_34XX_SIZE, | |
157 | .type = MT_DEVICE | |
158 | }, | |
159 | { | |
160 | .virtual = L4_EMU_34XX_VIRT, | |
161 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
162 | .length = L4_EMU_34XX_SIZE, | |
163 | .type = MT_DEVICE | |
164 | }, | |
a4f57b81 TL |
165 | #if defined(CONFIG_DEBUG_LL) && \ |
166 | (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) | |
167 | { | |
168 | .virtual = ZOOM_UART_VIRT, | |
169 | .pfn = __phys_to_pfn(ZOOM_UART_BASE), | |
170 | .length = SZ_1M, | |
171 | .type = MT_DEVICE | |
172 | }, | |
173 | #endif | |
1dbae815 | 174 | }; |
cc26b3b0 | 175 | #endif |
01001712 | 176 | |
33959553 | 177 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 178 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
179 | { |
180 | .virtual = L4_34XX_VIRT, | |
181 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
182 | .length = L4_34XX_SIZE, | |
183 | .type = MT_DEVICE | |
184 | } | |
185 | }; | |
186 | #endif | |
187 | ||
bb6abcf4 | 188 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 | 189 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
190 | { |
191 | .virtual = L4_34XX_VIRT, | |
192 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
193 | .length = L4_34XX_SIZE, | |
194 | .type = MT_DEVICE | |
195 | }, | |
1e6cb146 AM |
196 | { |
197 | .virtual = L4_WK_AM33XX_VIRT, | |
198 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
199 | .length = L4_WK_AM33XX_SIZE, | |
200 | .type = MT_DEVICE | |
201 | } | |
01001712 HP |
202 | }; |
203 | #endif | |
204 | ||
44169075 SS |
205 | #ifdef CONFIG_ARCH_OMAP4 |
206 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
207 | { | |
208 | .virtual = L3_44XX_VIRT, | |
209 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
210 | .length = L3_44XX_SIZE, | |
211 | .type = MT_DEVICE, | |
212 | }, | |
213 | { | |
214 | .virtual = L4_44XX_VIRT, | |
215 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
216 | .length = L4_44XX_SIZE, | |
217 | .type = MT_DEVICE, | |
218 | }, | |
44169075 SS |
219 | { |
220 | .virtual = L4_PER_44XX_VIRT, | |
221 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
222 | .length = L4_PER_44XX_SIZE, | |
223 | .type = MT_DEVICE, | |
224 | }, | |
137d105d SS |
225 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
226 | { | |
227 | .virtual = OMAP4_SRAM_VA, | |
228 | .pfn = __phys_to_pfn(OMAP4_SRAM_PA), | |
229 | .length = PAGE_SIZE, | |
230 | .type = MT_MEMORY_SO, | |
231 | }, | |
232 | #endif | |
233 | ||
44169075 SS |
234 | }; |
235 | #endif | |
1dbae815 | 236 | |
05e152c7 S |
237 | #ifdef CONFIG_SOC_OMAP5 |
238 | static struct map_desc omap54xx_io_desc[] __initdata = { | |
239 | { | |
240 | .virtual = L3_54XX_VIRT, | |
241 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
242 | .length = L3_54XX_SIZE, | |
243 | .type = MT_DEVICE, | |
244 | }, | |
245 | { | |
246 | .virtual = L4_54XX_VIRT, | |
247 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
248 | .length = L4_54XX_SIZE, | |
249 | .type = MT_DEVICE, | |
250 | }, | |
251 | { | |
252 | .virtual = L4_WK_54XX_VIRT, | |
253 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
254 | .length = L4_WK_54XX_SIZE, | |
255 | .type = MT_DEVICE, | |
256 | }, | |
257 | { | |
258 | .virtual = L4_PER_54XX_VIRT, | |
259 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
260 | .length = L4_PER_54XX_SIZE, | |
261 | .type = MT_DEVICE, | |
262 | }, | |
263 | }; | |
264 | #endif | |
265 | ||
59b479e0 | 266 | #ifdef CONFIG_SOC_OMAP2420 |
8185e468 | 267 | void __init omap242x_map_common_io(void) |
1dbae815 | 268 | { |
cc26b3b0 SMK |
269 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
270 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 271 | } |
cc26b3b0 SMK |
272 | #endif |
273 | ||
59b479e0 | 274 | #ifdef CONFIG_SOC_OMAP2430 |
8185e468 | 275 | void __init omap243x_map_common_io(void) |
6fbd55d0 | 276 | { |
cc26b3b0 SMK |
277 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
278 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 279 | } |
cc26b3b0 SMK |
280 | #endif |
281 | ||
a8eb7ca0 | 282 | #ifdef CONFIG_ARCH_OMAP3 |
8185e468 | 283 | void __init omap34xx_map_common_io(void) |
6fbd55d0 | 284 | { |
cc26b3b0 | 285 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 286 | } |
cc26b3b0 | 287 | #endif |
120db2cb | 288 | |
33959553 | 289 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 290 | void __init omapti81xx_map_common_io(void) |
01001712 | 291 | { |
a920360f | 292 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
293 | } |
294 | #endif | |
295 | ||
bb6abcf4 | 296 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 | 297 | void __init omapam33xx_map_common_io(void) |
01001712 | 298 | { |
1e6cb146 | 299 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
300 | } |
301 | #endif | |
302 | ||
6fbd55d0 | 303 | #ifdef CONFIG_ARCH_OMAP4 |
8185e468 | 304 | void __init omap44xx_map_common_io(void) |
6fbd55d0 | 305 | { |
44169075 | 306 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
2ec1fc4e | 307 | omap_barriers_init(); |
120db2cb | 308 | } |
6fbd55d0 | 309 | #endif |
120db2cb | 310 | |
05e152c7 S |
311 | #ifdef CONFIG_SOC_OMAP5 |
312 | void __init omap5_map_common_io(void) | |
313 | { | |
314 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
315 | } | |
316 | #endif | |
2f135eaf PW |
317 | /* |
318 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
319 | * | |
320 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
321 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
322 | * registers to the values currently defined by the kernel. Currently | |
323 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
324 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
325 | * or passes along the return value of clk_set_rate(). | |
326 | */ | |
327 | static int __init _omap2_init_reprogram_sdrc(void) | |
328 | { | |
329 | struct clk *dpll3_m2_ck; | |
330 | int v = -EINVAL; | |
331 | long rate; | |
332 | ||
333 | if (!cpu_is_omap34xx()) | |
334 | return 0; | |
335 | ||
336 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 337 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
338 | return -EINVAL; |
339 | ||
340 | rate = clk_get_rate(dpll3_m2_ck); | |
341 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
342 | v = clk_set_rate(dpll3_m2_ck, rate); | |
343 | if (v) | |
344 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
345 | ||
346 | clk_put(dpll3_m2_ck); | |
347 | ||
348 | return v; | |
349 | } | |
350 | ||
2092e5cc PW |
351 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
352 | { | |
353 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
354 | } | |
355 | ||
7b250aff | 356 | static void __init omap_common_init_early(void) |
120db2cb | 357 | { |
df80442d | 358 | omap_init_consistent_dma_size(); |
7b250aff | 359 | } |
2092e5cc | 360 | |
7b250aff TL |
361 | static void __init omap_hwmod_init_postsetup(void) |
362 | { | |
363 | u8 postsetup_state; | |
2092e5cc PW |
364 | |
365 | /* Set the default postsetup state for all hwmods */ | |
366 | #ifdef CONFIG_PM_RUNTIME | |
367 | postsetup_state = _HWMOD_STATE_IDLE; | |
368 | #else | |
369 | postsetup_state = _HWMOD_STATE_ENABLED; | |
370 | #endif | |
371 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 372 | |
53da4ce2 | 373 | omap_pm_if_early_init(); |
4805734b PW |
374 | } |
375 | ||
16110798 | 376 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
377 | void __init omap2420_init_early(void) |
378 | { | |
4c3cf901 | 379 | omap2_set_globals_242x(); |
4de34f35 | 380 | omap2xxx_check_revision(); |
7b250aff TL |
381 | omap_common_init_early(); |
382 | omap2xxx_voltagedomains_init(); | |
383 | omap242x_powerdomains_init(); | |
384 | omap242x_clockdomains_init(); | |
385 | omap2420_hwmod_init(); | |
386 | omap_hwmod_init_postsetup(); | |
387 | omap2420_clk_init(); | |
8f5b5a41 | 388 | } |
bbd707ac SG |
389 | |
390 | void __init omap2420_init_late(void) | |
391 | { | |
392 | omap_mux_late_init(); | |
393 | omap2_common_pm_late_init(); | |
394 | omap2_pm_init(); | |
395 | } | |
16110798 | 396 | #endif |
8f5b5a41 | 397 | |
16110798 | 398 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
399 | void __init omap2430_init_early(void) |
400 | { | |
4c3cf901 | 401 | omap2_set_globals_243x(); |
4de34f35 | 402 | omap2xxx_check_revision(); |
7b250aff TL |
403 | omap_common_init_early(); |
404 | omap2xxx_voltagedomains_init(); | |
405 | omap243x_powerdomains_init(); | |
406 | omap243x_clockdomains_init(); | |
407 | omap2430_hwmod_init(); | |
408 | omap_hwmod_init_postsetup(); | |
409 | omap2430_clk_init(); | |
410 | } | |
bbd707ac SG |
411 | |
412 | void __init omap2430_init_late(void) | |
413 | { | |
414 | omap_mux_late_init(); | |
415 | omap2_common_pm_late_init(); | |
416 | omap2_pm_init(); | |
417 | } | |
c4e2d245 | 418 | #endif |
7b250aff TL |
419 | |
420 | /* | |
421 | * Currently only board-omap3beagle.c should call this because of the | |
422 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
423 | */ | |
c4e2d245 | 424 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
425 | void __init omap3_init_early(void) |
426 | { | |
4c3cf901 | 427 | omap2_set_globals_3xxx(); |
4de34f35 VH |
428 | omap3xxx_check_revision(); |
429 | omap3xxx_check_features(); | |
7b250aff TL |
430 | omap_common_init_early(); |
431 | omap3xxx_voltagedomains_init(); | |
432 | omap3xxx_powerdomains_init(); | |
433 | omap3xxx_clockdomains_init(); | |
434 | omap3xxx_hwmod_init(); | |
435 | omap_hwmod_init_postsetup(); | |
436 | omap3xxx_clk_init(); | |
8f5b5a41 TL |
437 | } |
438 | ||
439 | void __init omap3430_init_early(void) | |
440 | { | |
7b250aff | 441 | omap3_init_early(); |
8f5b5a41 TL |
442 | } |
443 | ||
444 | void __init omap35xx_init_early(void) | |
445 | { | |
7b250aff | 446 | omap3_init_early(); |
8f5b5a41 TL |
447 | } |
448 | ||
449 | void __init omap3630_init_early(void) | |
450 | { | |
7b250aff | 451 | omap3_init_early(); |
8f5b5a41 TL |
452 | } |
453 | ||
454 | void __init am35xx_init_early(void) | |
455 | { | |
7b250aff | 456 | omap3_init_early(); |
8f5b5a41 TL |
457 | } |
458 | ||
a920360f | 459 | void __init ti81xx_init_early(void) |
8f5b5a41 | 460 | { |
a920360f | 461 | omap2_set_globals_ti81xx(); |
4de34f35 VH |
462 | omap3xxx_check_revision(); |
463 | ti81xx_check_features(); | |
4c3cf901 TL |
464 | omap_common_init_early(); |
465 | omap3xxx_voltagedomains_init(); | |
466 | omap3xxx_powerdomains_init(); | |
467 | omap3xxx_clockdomains_init(); | |
468 | omap3xxx_hwmod_init(); | |
469 | omap_hwmod_init_postsetup(); | |
470 | omap3xxx_clk_init(); | |
8f5b5a41 | 471 | } |
bbd707ac SG |
472 | |
473 | void __init omap3_init_late(void) | |
474 | { | |
475 | omap_mux_late_init(); | |
476 | omap2_common_pm_late_init(); | |
477 | omap3_pm_init(); | |
478 | } | |
479 | ||
480 | void __init omap3430_init_late(void) | |
481 | { | |
482 | omap_mux_late_init(); | |
483 | omap2_common_pm_late_init(); | |
484 | omap3_pm_init(); | |
485 | } | |
486 | ||
487 | void __init omap35xx_init_late(void) | |
488 | { | |
489 | omap_mux_late_init(); | |
490 | omap2_common_pm_late_init(); | |
491 | omap3_pm_init(); | |
492 | } | |
493 | ||
494 | void __init omap3630_init_late(void) | |
495 | { | |
496 | omap_mux_late_init(); | |
497 | omap2_common_pm_late_init(); | |
498 | omap3_pm_init(); | |
499 | } | |
500 | ||
501 | void __init am35xx_init_late(void) | |
502 | { | |
503 | omap_mux_late_init(); | |
504 | omap2_common_pm_late_init(); | |
505 | omap3_pm_init(); | |
506 | } | |
507 | ||
508 | void __init ti81xx_init_late(void) | |
509 | { | |
510 | omap_mux_late_init(); | |
511 | omap2_common_pm_late_init(); | |
512 | omap3_pm_init(); | |
513 | } | |
c4e2d245 | 514 | #endif |
8f5b5a41 | 515 | |
08f30989 AM |
516 | #ifdef CONFIG_SOC_AM33XX |
517 | void __init am33xx_init_early(void) | |
518 | { | |
519 | omap2_set_globals_am33xx(); | |
520 | omap3xxx_check_revision(); | |
521 | ti81xx_check_features(); | |
522 | omap_common_init_early(); | |
ce3fc89a | 523 | am33xx_voltagedomains_init(); |
3f0ea764 | 524 | am33xx_powerdomains_init(); |
9c80f3aa | 525 | am33xx_clockdomains_init(); |
e30384ab | 526 | am33xx_clk_init(); |
08f30989 AM |
527 | } |
528 | #endif | |
529 | ||
c4e2d245 | 530 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
531 | void __init omap4430_init_early(void) |
532 | { | |
4c3cf901 | 533 | omap2_set_globals_443x(); |
4de34f35 VH |
534 | omap4xxx_check_revision(); |
535 | omap4xxx_check_features(); | |
7b250aff TL |
536 | omap_common_init_early(); |
537 | omap44xx_voltagedomains_init(); | |
538 | omap44xx_powerdomains_init(); | |
539 | omap44xx_clockdomains_init(); | |
540 | omap44xx_hwmod_init(); | |
541 | omap_hwmod_init_postsetup(); | |
542 | omap4xxx_clk_init(); | |
8f5b5a41 | 543 | } |
bbd707ac SG |
544 | |
545 | void __init omap4430_init_late(void) | |
546 | { | |
547 | omap_mux_late_init(); | |
548 | omap2_common_pm_late_init(); | |
549 | omap4_pm_init(); | |
550 | } | |
c4e2d245 | 551 | #endif |
8f5b5a41 | 552 | |
05e152c7 S |
553 | #ifdef CONFIG_SOC_OMAP5 |
554 | void __init omap5_init_early(void) | |
555 | { | |
556 | omap2_set_globals_5xxx(); | |
557 | omap5xxx_check_revision(); | |
558 | omap_common_init_early(); | |
559 | } | |
560 | #endif | |
561 | ||
a4ca9dbe | 562 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
563 | struct omap_sdrc_params *sdrc_cs1) |
564 | { | |
a66cb345 TL |
565 | omap_sram_init(); |
566 | ||
01001712 | 567 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
568 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
569 | _omap2_init_reprogram_sdrc(); | |
570 | } | |
1dbae815 | 571 | } |