Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
ce491cf8 | 28 | #include <plat/serial.h> |
ce491cf8 | 29 | #include <plat/omap-pm.h> |
2a296c8f | 30 | #include "omap_hwmod.h" |
ee0839c2 | 31 | #include <plat/multi.h> |
2b6c4e73 | 32 | #include <plat-omap/dma-omap.h> |
ee0839c2 | 33 | |
622297fd TL |
34 | #include "../plat-omap/sram.h" |
35 | ||
dbc04161 | 36 | #include "soc.h" |
ee0839c2 | 37 | #include "iomap.h" |
81a60482 | 38 | #include "voltage.h" |
72e06d08 | 39 | #include "powerdomain.h" |
1540f214 | 40 | #include "clockdomain.h" |
4e65331c | 41 | #include "common.h" |
e30384ab | 42 | #include "clock.h" |
ee0839c2 TL |
43 | #include "clock2xxx.h" |
44 | #include "clock3xxx.h" | |
45 | #include "clock44xx.h" | |
3e6ece13 | 46 | #include "sdrc.h" |
02bfc030 | 47 | |
1dbae815 TL |
48 | /* |
49 | * The machine specific code may provide the extra mapping besides the | |
50 | * default mapping provided here. | |
51 | */ | |
cc26b3b0 | 52 | |
e48f814e | 53 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 54 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
55 | { |
56 | .virtual = L3_24XX_VIRT, | |
57 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
58 | .length = L3_24XX_SIZE, | |
59 | .type = MT_DEVICE | |
60 | }, | |
09f21ed4 | 61 | { |
cc26b3b0 SMK |
62 | .virtual = L4_24XX_VIRT, |
63 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
64 | .length = L4_24XX_SIZE, | |
65 | .type = MT_DEVICE | |
09f21ed4 | 66 | }, |
cc26b3b0 SMK |
67 | }; |
68 | ||
59b479e0 | 69 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
70 | static struct map_desc omap242x_io_desc[] __initdata = { |
71 | { | |
7adb9987 PW |
72 | .virtual = DSP_MEM_2420_VIRT, |
73 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
74 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
75 | .type = MT_DEVICE |
76 | }, | |
77 | { | |
7adb9987 PW |
78 | .virtual = DSP_IPI_2420_VIRT, |
79 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
80 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 81 | .type = MT_DEVICE |
09f21ed4 | 82 | }, |
cc26b3b0 | 83 | { |
7adb9987 PW |
84 | .virtual = DSP_MMU_2420_VIRT, |
85 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
86 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
87 | .type = MT_DEVICE |
88 | }, | |
89 | }; | |
90 | ||
91 | #endif | |
92 | ||
59b479e0 | 93 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 94 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
95 | { |
96 | .virtual = L4_WK_243X_VIRT, | |
97 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
98 | .length = L4_WK_243X_SIZE, | |
99 | .type = MT_DEVICE | |
100 | }, | |
101 | { | |
102 | .virtual = OMAP243X_GPMC_VIRT, | |
103 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
104 | .length = OMAP243X_GPMC_SIZE, | |
105 | .type = MT_DEVICE | |
106 | }, | |
cc26b3b0 SMK |
107 | { |
108 | .virtual = OMAP243X_SDRC_VIRT, | |
109 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
110 | .length = OMAP243X_SDRC_SIZE, | |
111 | .type = MT_DEVICE | |
112 | }, | |
113 | { | |
114 | .virtual = OMAP243X_SMS_VIRT, | |
115 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
116 | .length = OMAP243X_SMS_SIZE, | |
117 | .type = MT_DEVICE | |
118 | }, | |
119 | }; | |
72d0f1c3 | 120 | #endif |
72d0f1c3 | 121 | #endif |
cc26b3b0 | 122 | |
a8eb7ca0 | 123 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 124 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 125 | { |
cc26b3b0 SMK |
126 | .virtual = L3_34XX_VIRT, |
127 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
128 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
129 | .type = MT_DEVICE |
130 | }, | |
131 | { | |
cc26b3b0 SMK |
132 | .virtual = L4_34XX_VIRT, |
133 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
134 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
135 | .type = MT_DEVICE |
136 | }, | |
cc26b3b0 SMK |
137 | { |
138 | .virtual = OMAP34XX_GPMC_VIRT, | |
139 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
140 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 141 | .type = MT_DEVICE |
cc26b3b0 SMK |
142 | }, |
143 | { | |
144 | .virtual = OMAP343X_SMS_VIRT, | |
145 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
146 | .length = OMAP343X_SMS_SIZE, | |
147 | .type = MT_DEVICE | |
148 | }, | |
149 | { | |
150 | .virtual = OMAP343X_SDRC_VIRT, | |
151 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
152 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 153 | .type = MT_DEVICE |
cc26b3b0 SMK |
154 | }, |
155 | { | |
156 | .virtual = L4_PER_34XX_VIRT, | |
157 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
158 | .length = L4_PER_34XX_SIZE, | |
159 | .type = MT_DEVICE | |
160 | }, | |
161 | { | |
162 | .virtual = L4_EMU_34XX_VIRT, | |
163 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
164 | .length = L4_EMU_34XX_SIZE, | |
165 | .type = MT_DEVICE | |
166 | }, | |
a4f57b81 TL |
167 | #if defined(CONFIG_DEBUG_LL) && \ |
168 | (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) | |
169 | { | |
170 | .virtual = ZOOM_UART_VIRT, | |
171 | .pfn = __phys_to_pfn(ZOOM_UART_BASE), | |
172 | .length = SZ_1M, | |
173 | .type = MT_DEVICE | |
174 | }, | |
175 | #endif | |
1dbae815 | 176 | }; |
cc26b3b0 | 177 | #endif |
01001712 | 178 | |
33959553 | 179 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 180 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
181 | { |
182 | .virtual = L4_34XX_VIRT, | |
183 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
184 | .length = L4_34XX_SIZE, | |
185 | .type = MT_DEVICE | |
186 | } | |
187 | }; | |
188 | #endif | |
189 | ||
bb6abcf4 | 190 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 | 191 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
192 | { |
193 | .virtual = L4_34XX_VIRT, | |
194 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
195 | .length = L4_34XX_SIZE, | |
196 | .type = MT_DEVICE | |
197 | }, | |
1e6cb146 AM |
198 | { |
199 | .virtual = L4_WK_AM33XX_VIRT, | |
200 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
201 | .length = L4_WK_AM33XX_SIZE, | |
202 | .type = MT_DEVICE | |
203 | } | |
01001712 HP |
204 | }; |
205 | #endif | |
206 | ||
44169075 SS |
207 | #ifdef CONFIG_ARCH_OMAP4 |
208 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
209 | { | |
210 | .virtual = L3_44XX_VIRT, | |
211 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
212 | .length = L3_44XX_SIZE, | |
213 | .type = MT_DEVICE, | |
214 | }, | |
215 | { | |
216 | .virtual = L4_44XX_VIRT, | |
217 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
218 | .length = L4_44XX_SIZE, | |
219 | .type = MT_DEVICE, | |
220 | }, | |
44169075 SS |
221 | { |
222 | .virtual = L4_PER_44XX_VIRT, | |
223 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
224 | .length = L4_PER_44XX_SIZE, | |
225 | .type = MT_DEVICE, | |
226 | }, | |
137d105d SS |
227 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
228 | { | |
229 | .virtual = OMAP4_SRAM_VA, | |
230 | .pfn = __phys_to_pfn(OMAP4_SRAM_PA), | |
231 | .length = PAGE_SIZE, | |
232 | .type = MT_MEMORY_SO, | |
233 | }, | |
234 | #endif | |
235 | ||
44169075 SS |
236 | }; |
237 | #endif | |
1dbae815 | 238 | |
05e152c7 S |
239 | #ifdef CONFIG_SOC_OMAP5 |
240 | static struct map_desc omap54xx_io_desc[] __initdata = { | |
241 | { | |
242 | .virtual = L3_54XX_VIRT, | |
243 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
244 | .length = L3_54XX_SIZE, | |
245 | .type = MT_DEVICE, | |
246 | }, | |
247 | { | |
248 | .virtual = L4_54XX_VIRT, | |
249 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
250 | .length = L4_54XX_SIZE, | |
251 | .type = MT_DEVICE, | |
252 | }, | |
253 | { | |
254 | .virtual = L4_WK_54XX_VIRT, | |
255 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
256 | .length = L4_WK_54XX_SIZE, | |
257 | .type = MT_DEVICE, | |
258 | }, | |
259 | { | |
260 | .virtual = L4_PER_54XX_VIRT, | |
261 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
262 | .length = L4_PER_54XX_SIZE, | |
263 | .type = MT_DEVICE, | |
264 | }, | |
265 | }; | |
266 | #endif | |
267 | ||
59b479e0 | 268 | #ifdef CONFIG_SOC_OMAP2420 |
8185e468 | 269 | void __init omap242x_map_common_io(void) |
1dbae815 | 270 | { |
cc26b3b0 SMK |
271 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
272 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 273 | } |
cc26b3b0 SMK |
274 | #endif |
275 | ||
59b479e0 | 276 | #ifdef CONFIG_SOC_OMAP2430 |
8185e468 | 277 | void __init omap243x_map_common_io(void) |
6fbd55d0 | 278 | { |
cc26b3b0 SMK |
279 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
280 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 281 | } |
cc26b3b0 SMK |
282 | #endif |
283 | ||
a8eb7ca0 | 284 | #ifdef CONFIG_ARCH_OMAP3 |
8185e468 | 285 | void __init omap34xx_map_common_io(void) |
6fbd55d0 | 286 | { |
cc26b3b0 | 287 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 288 | } |
cc26b3b0 | 289 | #endif |
120db2cb | 290 | |
33959553 | 291 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 292 | void __init omapti81xx_map_common_io(void) |
01001712 | 293 | { |
a920360f | 294 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
295 | } |
296 | #endif | |
297 | ||
bb6abcf4 | 298 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 | 299 | void __init omapam33xx_map_common_io(void) |
01001712 | 300 | { |
1e6cb146 | 301 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
302 | } |
303 | #endif | |
304 | ||
6fbd55d0 | 305 | #ifdef CONFIG_ARCH_OMAP4 |
8185e468 | 306 | void __init omap44xx_map_common_io(void) |
6fbd55d0 | 307 | { |
44169075 | 308 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
2ec1fc4e | 309 | omap_barriers_init(); |
120db2cb | 310 | } |
6fbd55d0 | 311 | #endif |
120db2cb | 312 | |
05e152c7 S |
313 | #ifdef CONFIG_SOC_OMAP5 |
314 | void __init omap5_map_common_io(void) | |
315 | { | |
316 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
317 | } | |
318 | #endif | |
2f135eaf PW |
319 | /* |
320 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
321 | * | |
322 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
323 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
324 | * registers to the values currently defined by the kernel. Currently | |
325 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
326 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
327 | * or passes along the return value of clk_set_rate(). | |
328 | */ | |
329 | static int __init _omap2_init_reprogram_sdrc(void) | |
330 | { | |
331 | struct clk *dpll3_m2_ck; | |
332 | int v = -EINVAL; | |
333 | long rate; | |
334 | ||
335 | if (!cpu_is_omap34xx()) | |
336 | return 0; | |
337 | ||
338 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 339 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
340 | return -EINVAL; |
341 | ||
342 | rate = clk_get_rate(dpll3_m2_ck); | |
343 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
344 | v = clk_set_rate(dpll3_m2_ck, rate); | |
345 | if (v) | |
346 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
347 | ||
348 | clk_put(dpll3_m2_ck); | |
349 | ||
350 | return v; | |
351 | } | |
352 | ||
2092e5cc PW |
353 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
354 | { | |
355 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
356 | } | |
357 | ||
7b250aff | 358 | static void __init omap_common_init_early(void) |
120db2cb | 359 | { |
df80442d | 360 | omap_init_consistent_dma_size(); |
7b250aff | 361 | } |
2092e5cc | 362 | |
7b250aff TL |
363 | static void __init omap_hwmod_init_postsetup(void) |
364 | { | |
365 | u8 postsetup_state; | |
2092e5cc PW |
366 | |
367 | /* Set the default postsetup state for all hwmods */ | |
368 | #ifdef CONFIG_PM_RUNTIME | |
369 | postsetup_state = _HWMOD_STATE_IDLE; | |
370 | #else | |
371 | postsetup_state = _HWMOD_STATE_ENABLED; | |
372 | #endif | |
373 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 374 | |
53da4ce2 | 375 | omap_pm_if_early_init(); |
4805734b PW |
376 | } |
377 | ||
16110798 | 378 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
379 | void __init omap2420_init_early(void) |
380 | { | |
4c3cf901 | 381 | omap2_set_globals_242x(); |
4de34f35 | 382 | omap2xxx_check_revision(); |
7b250aff TL |
383 | omap_common_init_early(); |
384 | omap2xxx_voltagedomains_init(); | |
385 | omap242x_powerdomains_init(); | |
386 | omap242x_clockdomains_init(); | |
387 | omap2420_hwmod_init(); | |
388 | omap_hwmod_init_postsetup(); | |
389 | omap2420_clk_init(); | |
8f5b5a41 | 390 | } |
bbd707ac SG |
391 | |
392 | void __init omap2420_init_late(void) | |
393 | { | |
394 | omap_mux_late_init(); | |
395 | omap2_common_pm_late_init(); | |
396 | omap2_pm_init(); | |
397 | } | |
16110798 | 398 | #endif |
8f5b5a41 | 399 | |
16110798 | 400 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
401 | void __init omap2430_init_early(void) |
402 | { | |
4c3cf901 | 403 | omap2_set_globals_243x(); |
4de34f35 | 404 | omap2xxx_check_revision(); |
7b250aff TL |
405 | omap_common_init_early(); |
406 | omap2xxx_voltagedomains_init(); | |
407 | omap243x_powerdomains_init(); | |
408 | omap243x_clockdomains_init(); | |
409 | omap2430_hwmod_init(); | |
410 | omap_hwmod_init_postsetup(); | |
411 | omap2430_clk_init(); | |
412 | } | |
bbd707ac SG |
413 | |
414 | void __init omap2430_init_late(void) | |
415 | { | |
416 | omap_mux_late_init(); | |
417 | omap2_common_pm_late_init(); | |
418 | omap2_pm_init(); | |
419 | } | |
c4e2d245 | 420 | #endif |
7b250aff TL |
421 | |
422 | /* | |
423 | * Currently only board-omap3beagle.c should call this because of the | |
424 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
425 | */ | |
c4e2d245 | 426 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
427 | void __init omap3_init_early(void) |
428 | { | |
4c3cf901 | 429 | omap2_set_globals_3xxx(); |
4de34f35 VH |
430 | omap3xxx_check_revision(); |
431 | omap3xxx_check_features(); | |
7b250aff TL |
432 | omap_common_init_early(); |
433 | omap3xxx_voltagedomains_init(); | |
434 | omap3xxx_powerdomains_init(); | |
435 | omap3xxx_clockdomains_init(); | |
436 | omap3xxx_hwmod_init(); | |
437 | omap_hwmod_init_postsetup(); | |
438 | omap3xxx_clk_init(); | |
8f5b5a41 TL |
439 | } |
440 | ||
441 | void __init omap3430_init_early(void) | |
442 | { | |
7b250aff | 443 | omap3_init_early(); |
8f5b5a41 TL |
444 | } |
445 | ||
446 | void __init omap35xx_init_early(void) | |
447 | { | |
7b250aff | 448 | omap3_init_early(); |
8f5b5a41 TL |
449 | } |
450 | ||
451 | void __init omap3630_init_early(void) | |
452 | { | |
7b250aff | 453 | omap3_init_early(); |
8f5b5a41 TL |
454 | } |
455 | ||
456 | void __init am35xx_init_early(void) | |
457 | { | |
7b250aff | 458 | omap3_init_early(); |
8f5b5a41 TL |
459 | } |
460 | ||
a920360f | 461 | void __init ti81xx_init_early(void) |
8f5b5a41 | 462 | { |
a920360f | 463 | omap2_set_globals_ti81xx(); |
4de34f35 VH |
464 | omap3xxx_check_revision(); |
465 | ti81xx_check_features(); | |
4c3cf901 TL |
466 | omap_common_init_early(); |
467 | omap3xxx_voltagedomains_init(); | |
468 | omap3xxx_powerdomains_init(); | |
469 | omap3xxx_clockdomains_init(); | |
470 | omap3xxx_hwmod_init(); | |
471 | omap_hwmod_init_postsetup(); | |
472 | omap3xxx_clk_init(); | |
8f5b5a41 | 473 | } |
bbd707ac SG |
474 | |
475 | void __init omap3_init_late(void) | |
476 | { | |
477 | omap_mux_late_init(); | |
478 | omap2_common_pm_late_init(); | |
479 | omap3_pm_init(); | |
480 | } | |
481 | ||
482 | void __init omap3430_init_late(void) | |
483 | { | |
484 | omap_mux_late_init(); | |
485 | omap2_common_pm_late_init(); | |
486 | omap3_pm_init(); | |
487 | } | |
488 | ||
489 | void __init omap35xx_init_late(void) | |
490 | { | |
491 | omap_mux_late_init(); | |
492 | omap2_common_pm_late_init(); | |
493 | omap3_pm_init(); | |
494 | } | |
495 | ||
496 | void __init omap3630_init_late(void) | |
497 | { | |
498 | omap_mux_late_init(); | |
499 | omap2_common_pm_late_init(); | |
500 | omap3_pm_init(); | |
501 | } | |
502 | ||
503 | void __init am35xx_init_late(void) | |
504 | { | |
505 | omap_mux_late_init(); | |
506 | omap2_common_pm_late_init(); | |
507 | omap3_pm_init(); | |
508 | } | |
509 | ||
510 | void __init ti81xx_init_late(void) | |
511 | { | |
512 | omap_mux_late_init(); | |
513 | omap2_common_pm_late_init(); | |
514 | omap3_pm_init(); | |
515 | } | |
c4e2d245 | 516 | #endif |
8f5b5a41 | 517 | |
08f30989 AM |
518 | #ifdef CONFIG_SOC_AM33XX |
519 | void __init am33xx_init_early(void) | |
520 | { | |
521 | omap2_set_globals_am33xx(); | |
522 | omap3xxx_check_revision(); | |
523 | ti81xx_check_features(); | |
524 | omap_common_init_early(); | |
ce3fc89a | 525 | am33xx_voltagedomains_init(); |
3f0ea764 | 526 | am33xx_powerdomains_init(); |
9c80f3aa | 527 | am33xx_clockdomains_init(); |
a2cfc509 VH |
528 | am33xx_hwmod_init(); |
529 | omap_hwmod_init_postsetup(); | |
e30384ab | 530 | am33xx_clk_init(); |
08f30989 AM |
531 | } |
532 | #endif | |
533 | ||
c4e2d245 | 534 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
535 | void __init omap4430_init_early(void) |
536 | { | |
4c3cf901 | 537 | omap2_set_globals_443x(); |
4de34f35 VH |
538 | omap4xxx_check_revision(); |
539 | omap4xxx_check_features(); | |
7b250aff TL |
540 | omap_common_init_early(); |
541 | omap44xx_voltagedomains_init(); | |
542 | omap44xx_powerdomains_init(); | |
543 | omap44xx_clockdomains_init(); | |
544 | omap44xx_hwmod_init(); | |
545 | omap_hwmod_init_postsetup(); | |
546 | omap4xxx_clk_init(); | |
8f5b5a41 | 547 | } |
bbd707ac SG |
548 | |
549 | void __init omap4430_init_late(void) | |
550 | { | |
551 | omap_mux_late_init(); | |
552 | omap2_common_pm_late_init(); | |
553 | omap4_pm_init(); | |
554 | } | |
c4e2d245 | 555 | #endif |
8f5b5a41 | 556 | |
05e152c7 S |
557 | #ifdef CONFIG_SOC_OMAP5 |
558 | void __init omap5_init_early(void) | |
559 | { | |
560 | omap2_set_globals_5xxx(); | |
561 | omap5xxx_check_revision(); | |
562 | omap_common_init_early(); | |
563 | } | |
564 | #endif | |
565 | ||
a4ca9dbe | 566 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
567 | struct omap_sdrc_params *sdrc_cs1) |
568 | { | |
a66cb345 TL |
569 | omap_sram_init(); |
570 | ||
01001712 | 571 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
572 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
573 | _omap2_init_reprogram_sdrc(); | |
574 | } | |
1dbae815 | 575 | } |