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ARM: AM43xx: hwmod: use OMAP4 hardreset ops instead of the AM33xx version
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
45c3eb7d 28#include <linux/omap-dma.h>
ee0839c2 29
dc843280 30#include "omap_hwmod.h"
dbc04161 31#include "soc.h"
ee0839c2 32#include "iomap.h"
81a60482 33#include "voltage.h"
72e06d08 34#include "powerdomain.h"
1540f214 35#include "clockdomain.h"
4e65331c 36#include "common.h"
e30384ab 37#include "clock.h"
ee0839c2
TL		 38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "clock44xx.h"
1d5aef49 41#include "omap-pm.h"
3e6ece13 42#include "sdrc.h"
b6a4226c 43#include "control.h"
3d82cbbb 44#include "serial.h"
bf027ca1 45#include "sram.h"
c4ceedcb
PW		 46#include "cm2xxx.h"
47#include "cm3xxx.h"
7632a02f 48#include "cm33xx.h"
d9a16f9a
PW		 49#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
53#include "cminst44xx.h"
63a293e0
PW		 54#include "prm2xxx.h"
55#include "prm3xxx.h"
56#include "prm44xx.h"
69a1e7a1 57#include "opp2xxx.h"
02bfc030 58
ff931c82 59/*
cfa9667d 60 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 61 * clock initializations
62 */
cfa9667d 63static int (*omap_clk_soc_init)(void);
ff931c82 64
1dbae815
TL		 65/*
66 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
cc26b3b0 69
e48f814e 70#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 71static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 72 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
09f21ed4 78 {
cc26b3b0
SMK		 79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
82 .type = MT_DEVICE
09f21ed4 83 },
cc26b3b0
SMK		 84};
85
59b479e0 86#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 87static struct map_desc omap242x_io_desc[] __initdata = {
88 {
7adb9987
PW		 89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 92 .type = MT_DEVICE
93 },
94 {
7adb9987
PW		 95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
cc26b3b0 98 .type = MT_DEVICE
09f21ed4 99 },
cc26b3b0 100 {
7adb9987
PW		 101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 104 .type = MT_DEVICE
105 },
106};
107
108#endif
109
59b479e0 110#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 111static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
cc26b3b0
SMK		 124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136};
72d0f1c3 137#endif
72d0f1c3 138#endif
cc26b3b0 139
a8eb7ca0 140#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 141static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 142 {
cc26b3b0
SMK		 143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
c40fae95
TL		 146 .type = MT_DEVICE
147 },
148 {
cc26b3b0
SMK		 149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
c40fae95
TL		 152 .type = MT_DEVICE
153 },
cc26b3b0
SMK		 154 {
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
1dbae815 158 .type = MT_DEVICE
cc26b3b0
SMK		 159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
1dbae815 170 .type = MT_DEVICE
cc26b3b0
SMK		 171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
1dbae815 184};
cc26b3b0 185#endif
01001712 186
33959553 187#ifdef CONFIG_SOC_TI81XX
a920360f 188static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 }
195};
196#endif
197
addb154a 198#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 199static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
1e6cb146
AM		 206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
01001712
HP		 212};
213#endif
214
44169075
SS		 215#ifdef CONFIG_ARCH_OMAP4
216static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
44169075
SS		 229 {
230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
44169075
SS		 235};
236#endif
1dbae815 237
a3a9384a 238#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
05e152c7
S		 239static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264};
265#endif
266
59b479e0 267#ifdef CONFIG_SOC_OMAP2420
b6a4226c 268void __init omap242x_map_io(void)
1dbae815 269{
cc26b3b0
SMK		 270 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
271 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 272}
cc26b3b0
SMK		 273#endif
274
59b479e0 275#ifdef CONFIG_SOC_OMAP2430
b6a4226c 276void __init omap243x_map_io(void)
6fbd55d0 277{
cc26b3b0
SMK		 278 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
279 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 280}
cc26b3b0
SMK		 281#endif
282
a8eb7ca0 283#ifdef CONFIG_ARCH_OMAP3
b6a4226c 284void __init omap3_map_io(void)
6fbd55d0 285{
cc26b3b0 286 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 287}
cc26b3b0 288#endif
120db2cb 289
33959553 290#ifdef CONFIG_SOC_TI81XX
b6a4226c 291void __init ti81xx_map_io(void)
01001712 292{
a920360f 293 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 294}
295#endif
296
addb154a 297#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 298void __init am33xx_map_io(void)
01001712 299{
1e6cb146 300 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 301}
302#endif
303
6fbd55d0 304#ifdef CONFIG_ARCH_OMAP4
b6a4226c 305void __init omap4_map_io(void)
6fbd55d0 306{
44169075 307 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e 308 omap_barriers_init();
120db2cb 309}
6fbd55d0 310#endif
120db2cb 311
a3a9384a 312#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
b6a4226c 313void __init omap5_map_io(void)
05e152c7
S		 314{
315 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
1348bbf9 316 omap_barriers_init();
05e152c7
S		 317}
318#endif
2f135eaf
PW		 319/*
320 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
321 *
322 * Sets the CORE DPLL3 M2 divider to the same value that it's at
323 * currently. This has the effect of setting the SDRC SDRAM AC timing
324 * registers to the values currently defined by the kernel. Currently
325 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
326 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
327 * or passes along the return value of clk_set_rate().
328 */
329static int __init _omap2_init_reprogram_sdrc(void)
330{
331 struct clk *dpll3_m2_ck;
332 int v = -EINVAL;
333 long rate;
334
335 if (!cpu_is_omap34xx())
336 return 0;
337
338 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 339 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 340 return -EINVAL;
341
342 rate = clk_get_rate(dpll3_m2_ck);
343 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
344 v = clk_set_rate(dpll3_m2_ck, rate);
345 if (v)
346 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
347
348 clk_put(dpll3_m2_ck);
349
350 return v;
351}
352
2092e5cc
PW		 353static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
354{
355 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
356}
357
7b250aff
TL		 358static void __init omap_hwmod_init_postsetup(void)
359{
360 u8 postsetup_state;
2092e5cc
PW		 361
362 /* Set the default postsetup state for all hwmods */
363#ifdef CONFIG_PM_RUNTIME
364 postsetup_state = _HWMOD_STATE_IDLE;
365#else
366 postsetup_state = _HWMOD_STATE_ENABLED;
367#endif
368 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 369
53da4ce2 370 omap_pm_if_early_init();
4805734b
PW		 371}
372
069d0a78 373static void __init __maybe_unused omap_common_late_init(void)
4ed12be0
RB		 374{
375 omap_mux_late_init();
376 omap2_common_pm_late_init();
6770b211 377 omap_soc_device_init();
4ed12be0
RB		 378}
379
16110798 380#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 381void __init omap2420_init_early(void)
382{
b6a4226c
PW		 383 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
384 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
385 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
386 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
387 NULL);
d9a16f9a
PW		 388 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
389 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
4de34f35 390 omap2xxx_check_revision();
63a293e0 391 omap2xxx_prm_init();
c4ceedcb 392 omap2xxx_cm_init();
7b250aff
TL		 393 omap2xxx_voltagedomains_init();
394 omap242x_powerdomains_init();
395 omap242x_clockdomains_init();
396 omap2420_hwmod_init();
397 omap_hwmod_init_postsetup();
6a194a6e
TK		 398 omap_clk_soc_init = omap2420_dt_clk_init;
399 rate_table = omap2420_rate_table;
8f5b5a41 400}
bbd707ac
SG		 401
402void __init omap2420_init_late(void)
403{
4ed12be0 404 omap_common_late_init();
bbd707ac 405 omap2_pm_init();
23fb8ba3 406 omap2_clk_enable_autoidle_all();
bbd707ac 407}
16110798 408#endif
8f5b5a41 409
16110798 410#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 411void __init omap2430_init_early(void)
412{
b6a4226c
PW		 413 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
414 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
415 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
416 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
417 NULL);
d9a16f9a
PW		 418 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
419 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
4de34f35 420 omap2xxx_check_revision();
63a293e0 421 omap2xxx_prm_init();
c4ceedcb 422 omap2xxx_cm_init();
7b250aff
TL		 423 omap2xxx_voltagedomains_init();
424 omap243x_powerdomains_init();
425 omap243x_clockdomains_init();
426 omap2430_hwmod_init();
427 omap_hwmod_init_postsetup();
6a194a6e
TK		 428 omap_clk_soc_init = omap2430_dt_clk_init;
429 rate_table = omap2430_rate_table;
7b250aff 430}
bbd707ac
SG		 431
432void __init omap2430_init_late(void)
433{
4ed12be0 434 omap_common_late_init();
bbd707ac 435 omap2_pm_init();
23fb8ba3 436 omap2_clk_enable_autoidle_all();
bbd707ac 437}
c4e2d245 438#endif
7b250aff
TL		 439
440/*
441 * Currently only board-omap3beagle.c should call this because of the
442 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
443 */
c4e2d245 444#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 445void __init omap3_init_early(void)
446{
b6a4226c
PW		 447 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
448 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
449 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
450 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
451 NULL);
d9a16f9a
PW		 452 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
453 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
4de34f35
VH		 454 omap3xxx_check_revision();
455 omap3xxx_check_features();
63a293e0 456 omap3xxx_prm_init();
c4ceedcb 457 omap3xxx_cm_init();
7b250aff
TL		 458 omap3xxx_voltagedomains_init();
459 omap3xxx_powerdomains_init();
460 omap3xxx_clockdomains_init();
461 omap3xxx_hwmod_init();
462 omap_hwmod_init_postsetup();
cfa9667d 463 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41
TL		 464}
465
466void __init omap3430_init_early(void)
467{
7b250aff 468 omap3_init_early();
3e049157
TK		 469 if (of_have_populated_dt())
470 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 471}
472
473void __init omap35xx_init_early(void)
474{
7b250aff 475 omap3_init_early();
3e049157
TK		 476 if (of_have_populated_dt())
477 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 478}
479
480void __init omap3630_init_early(void)
481{
7b250aff 482 omap3_init_early();
3e049157
TK		 483 if (of_have_populated_dt())
484 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 485}
486
487void __init am35xx_init_early(void)
488{
7b250aff 489 omap3_init_early();
3e049157
TK		 490 if (of_have_populated_dt())
491 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 492}
493
a920360f 494void __init ti81xx_init_early(void)
8f5b5a41 495{
b6a4226c
PW		 496 omap2_set_globals_tap(OMAP343X_CLASS,
497 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
498 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
499 NULL);
d9a16f9a
PW		 500 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
501 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
4de34f35
VH		 502 omap3xxx_check_revision();
503 ti81xx_check_features();
4c3cf901
TL		 504 omap3xxx_voltagedomains_init();
505 omap3xxx_powerdomains_init();
506 omap3xxx_clockdomains_init();
507 omap3xxx_hwmod_init();
508 omap_hwmod_init_postsetup();
3e049157
TK		 509 if (of_have_populated_dt())
510 omap_clk_soc_init = ti81xx_dt_clk_init;
511 else
512 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41 513}
bbd707ac
SG		 514
515void __init omap3_init_late(void)
516{
4ed12be0 517 omap_common_late_init();
bbd707ac 518 omap3_pm_init();
23fb8ba3 519 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 520}
521
522void __init omap3430_init_late(void)
523{
4ed12be0 524 omap_common_late_init();
bbd707ac 525 omap3_pm_init();
23fb8ba3 526 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 527}
528
529void __init omap35xx_init_late(void)
530{
4ed12be0 531 omap_common_late_init();
bbd707ac 532 omap3_pm_init();
23fb8ba3 533 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 534}
535
536void __init omap3630_init_late(void)
537{
4ed12be0 538 omap_common_late_init();
bbd707ac 539 omap3_pm_init();
23fb8ba3 540 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 541}
542
543void __init am35xx_init_late(void)
544{
4ed12be0 545 omap_common_late_init();
bbd707ac 546 omap3_pm_init();
23fb8ba3 547 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 548}
549
550void __init ti81xx_init_late(void)
551{
4ed12be0 552 omap_common_late_init();
bbd707ac 553 omap3_pm_init();
23fb8ba3 554 omap2_clk_enable_autoidle_all();
bbd707ac 555}
c4e2d245 556#endif
8f5b5a41 557
08f30989
AM		 558#ifdef CONFIG_SOC_AM33XX
559void __init am33xx_init_early(void)
560{
b6a4226c
PW		 561 omap2_set_globals_tap(AM335X_CLASS,
562 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
563 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
564 NULL);
d9a16f9a
PW		 565 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
566 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
08f30989 567 omap3xxx_check_revision();
7bcad170 568 am33xx_check_features();
7632a02f 569 am33xx_cm_init();
3f0ea764 570 am33xx_powerdomains_init();
9c80f3aa 571 am33xx_clockdomains_init();
a2cfc509
VH		 572 am33xx_hwmod_init();
573 omap_hwmod_init_postsetup();
149c09d3 574 omap_clk_soc_init = am33xx_dt_clk_init;
08f30989 575}
765e7a06
NM		 576
577void __init am33xx_init_late(void)
578{
579 omap_common_late_init();
580}
08f30989
AM		 581#endif
582
c5107027
AM		 583#ifdef CONFIG_SOC_AM43XX
584void __init am43xx_init_early(void)
585{
586 omap2_set_globals_tap(AM335X_CLASS,
587 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
588 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
589 NULL);
590 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
591 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
8835cf6e
A		 592 omap_prm_base_init();
593 omap_cm_base_init();
c5107027 594 omap3xxx_check_revision();
7a2e0513 595 am33xx_check_features();
8843b119 596 omap44xx_prm_init();
7632a02f 597 omap4_cm_init();
8835cf6e
A		 598 am43xx_powerdomains_init();
599 am43xx_clockdomains_init();
600 am43xx_hwmod_init();
601 omap_hwmod_init_postsetup();
d941f86f 602 omap_l2_cache_init();
d22031e2 603 omap_clk_soc_init = am43xx_dt_clk_init;
c5107027 604}
765e7a06
NM		 605
606void __init am43xx_init_late(void)
607{
608 omap_common_late_init();
609}
c5107027
AM		 610#endif
611
c4e2d245 612#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 613void __init omap4430_init_early(void)
614{
b6a4226c
PW		 615 omap2_set_globals_tap(OMAP443X_CLASS,
616 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
617 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
618 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
d9a16f9a
PW		 619 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
620 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
621 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
622 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
623 omap_prm_base_init();
624 omap_cm_base_init();
4de34f35
VH		 625 omap4xxx_check_revision();
626 omap4xxx_check_features();
7632a02f 627 omap4_cm_init();
de70af49 628 omap4_pm_init_early();
63a293e0 629 omap44xx_prm_init();
7b250aff
TL		 630 omap44xx_voltagedomains_init();
631 omap44xx_powerdomains_init();
632 omap44xx_clockdomains_init();
633 omap44xx_hwmod_init();
634 omap_hwmod_init_postsetup();
b39b14e6 635 omap_l2_cache_init();
c8c88d85 636 omap_clk_soc_init = omap4xxx_dt_clk_init;
8f5b5a41 637}
bbd707ac
SG		 638
639void __init omap4430_init_late(void)
640{
4ed12be0 641 omap_common_late_init();
bbd707ac 642 omap4_pm_init();
23fb8ba3 643 omap2_clk_enable_autoidle_all();
bbd707ac 644}
c4e2d245 645#endif
8f5b5a41 646
05e152c7
S		 647#ifdef CONFIG_SOC_OMAP5
648void __init omap5_init_early(void)
649{
b6a4226c
PW		 650 omap2_set_globals_tap(OMAP54XX_CLASS,
651 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
652 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
653 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
d9a16f9a
PW		 654 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
655 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
656 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
657 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
628ed471 658 omap4_pm_init_early();
d9a16f9a
PW		 659 omap_prm_base_init();
660 omap_cm_base_init();
e4020aa9 661 omap44xx_prm_init();
05e152c7 662 omap5xxx_check_revision();
7632a02f 663 omap4_cm_init();
e4020aa9
SS		 664 omap54xx_voltagedomains_init();
665 omap54xx_powerdomains_init();
666 omap54xx_clockdomains_init();
667 omap54xx_hwmod_init();
668 omap_hwmod_init_postsetup();
cfa9667d 669 omap_clk_soc_init = omap5xxx_dt_clk_init;
05e152c7 670}
765e7a06
NM		 671
672void __init omap5_init_late(void)
673{
674 omap_common_late_init();
628ed471
SS		 675 omap4_pm_init();
676 omap2_clk_enable_autoidle_all();
765e7a06 677}
05e152c7
S		 678#endif
679
a3a9384a
S		 680#ifdef CONFIG_SOC_DRA7XX
681void __init dra7xx_init_early(void)
682{
683 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
684 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
685 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
686 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
687 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
688 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
689 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
6af16a1d 690 omap4_pm_init_early();
a3a9384a
S		 691 omap_prm_base_init();
692 omap_cm_base_init();
7de516a6 693 omap44xx_prm_init();
733d20ee 694 dra7xxx_check_revision();
7632a02f 695 omap4_cm_init();
7de516a6
A		 696 dra7xx_powerdomains_init();
697 dra7xx_clockdomains_init();
698 dra7xx_hwmod_init();
699 omap_hwmod_init_postsetup();
f1cf498e 700 omap_clk_soc_init = dra7xx_dt_clk_init;
a3a9384a 701}
765e7a06
NM		 702
703void __init dra7xx_init_late(void)
704{
705 omap_common_late_init();
6af16a1d
RN		 706 omap4_pm_init();
707 omap2_clk_enable_autoidle_all();
765e7a06 708}
a3a9384a
S		 709#endif
710
711
a4ca9dbe 712void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 713 struct omap_sdrc_params *sdrc_cs1)
714{
a66cb345
TL		 715 omap_sram_init();
716
01001712 717 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 718 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
719 _omap2_init_reprogram_sdrc();
720 }
1dbae815 721}
cfa9667d
TK		 722
723int __init omap_clk_init(void)
724{
725 int ret = 0;
726
727 if (!omap_clk_soc_init)
728 return 0;
729
8111e010
TK		 730 ti_clk_init_features();
731
cfa9667d 732 ret = of_prcm_init();
c08ee14c
TK		 733 if (ret)
734 return ret;
735
736 of_clk_init(NULL);
737
738 ti_dt_clk_init_retry_clks();
739
740 ti_dt_clockdomains_setup();
741
742 ret = omap_clk_soc_init();
cfa9667d
TK		 743
744 return ret;
745}
Linux kernel - Deliverables
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