[deliverable/linux.git] / arch / arm / mach-omap2 / io.c

/*
 * linux/arch/arm/mach-omap2/io.c
 *
 * OMAP2 I/O mapping code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Copyright (C) 2007-2009 Texas Instruments
 *
 * Author:
 *	Juha Yrjola <juha.yrjola@nokia.com>
 *	Syed Khasim <x0khasim@ti.com>
 *
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <asm/tlb.h>

#include <asm/mach/map.h>

#include <mach/mux.h>
#include <mach/omapfb.h>
#include <mach/sram.h>
#include <mach/sdrc.h>
#include <mach/gpmc.h>

#ifndef CONFIG_ARCH_OMAP4	/* FIXME: Remove this once clkdev is ready */
#include "clock.h"

#include <mach/powerdomain.h>

#include "powerdomains.h"

#include <mach/clockdomain.h>
#include "clockdomains.h"
#endif
/*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
 */

#ifdef CONFIG_ARCH_OMAP24XX
static struct map_desc omap24xx_io_desc[] __initdata = {
	{
		.virtual	= L3_24XX_VIRT,
		.pfn		= __phys_to_pfn(L3_24XX_PHYS),
		.length		= L3_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_24XX_VIRT,
		.pfn		= __phys_to_pfn(L4_24XX_PHYS),
		.length		= L4_24XX_SIZE,
		.type		= MT_DEVICE
	},
};

#ifdef CONFIG_ARCH_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
	{
		.virtual	= DSP_MEM_24XX_VIRT,
		.pfn		= __phys_to_pfn(DSP_MEM_24XX_PHYS),
		.length		= DSP_MEM_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_IPI_24XX_VIRT,
		.pfn		= __phys_to_pfn(DSP_IPI_24XX_PHYS),
		.length		= DSP_IPI_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_MMU_24XX_VIRT,
		.pfn		= __phys_to_pfn(DSP_MMU_24XX_PHYS),
		.length		= DSP_MMU_24XX_SIZE,
		.type		= MT_DEVICE
	},
};

#endif

#ifdef CONFIG_ARCH_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
	{
		.virtual	= L4_WK_243X_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_243X_PHYS),
		.length		= L4_WK_243X_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_GPMC_PHYS),
		.length		= OMAP243X_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SDRC_PHYS),
		.length		= OMAP243X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SMS_PHYS),
		.length		= OMAP243X_SMS_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#endif

#ifdef	CONFIG_ARCH_OMAP34XX
static struct map_desc omap34xx_io_desc[] __initdata = {
	{
		.virtual	= L3_34XX_VIRT,
		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
		.length		= L3_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_WK_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_34XX_PHYS),
		.length		= L4_WK_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP34XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
		.length		= OMAP34XX_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
		.length		= OMAP343X_SMS_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
		.length		= OMAP343X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_PER_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_34XX_PHYS),
		.length		= L4_PER_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_EMU_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
		.length		= L4_EMU_34XX_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#ifdef	CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
	{
		.virtual	= L3_44XX_VIRT,
		.pfn		= __phys_to_pfn(L3_44XX_PHYS),
		.length		= L3_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_44XX_PHYS),
		.length		= L4_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_WK_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_44XX_PHYS),
		.length		= L4_WK_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_GPMC_PHYS),
		.length		= OMAP44XX_GPMC_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_PER_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_44XX_PHYS),
		.length		= L4_PER_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_EMU_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_44XX_PHYS),
		.length		= L4_EMU_44XX_SIZE,
		.type		= MT_DEVICE,
	},
};
#endif

void __init omap2_map_common_io(void)
{
#if defined(CONFIG_ARCH_OMAP2420)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP2430)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP4)
	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
#endif
	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
	omapfb_reserve_sdram();
}

/*
 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 *
 * Sets the CORE DPLL3 M2 divider to the same value that it's at
 * currently.  This has the effect of setting the SDRC SDRAM AC timing
 * registers to the values currently defined by the kernel.  Currently
 * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 * or passes along the return value of clk_set_rate().
 */
static int __init _omap2_init_reprogram_sdrc(void)
{
	struct clk *dpll3_m2_ck;
	int v = -EINVAL;
	long rate;

	if (!cpu_is_omap34xx())
		return 0;

	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	if (!dpll3_m2_ck)
		return -EINVAL;

	rate = clk_get_rate(dpll3_m2_ck);
	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	v = clk_set_rate(dpll3_m2_ck, rate);
	if (v)
		pr_err("dpll3_m2_clk rate change failed: %d\n", v);

	clk_put(dpll3_m2_ck);

	return v;
}

void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
{
	omap2_mux_init();
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
	pwrdm_init(powerdomains_omap);
	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
	omap2_clk_init();
	omap2_sdrc_init(sp);
	_omap2_init_reprogram_sdrc();
#endif
	gpmc_init();
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/io.c
	3	*
	4	* OMAP2 I/O mapping code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
44169075	7	* Copyright (C) 2007-2009 Texas Instruments
646e3ed1 TL	8	*
	9	* Author:
	10	* Juha Yrjola <juha.yrjola@nokia.com>
	11	* Syed Khasim <x0khasim@ti.com>
1dbae815	12	*
44169075 SS	13	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
44169075 SS	14	*
1dbae815 TL	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
1dbae815 TL	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
fced80c7	23	#include <linux/io.h>
2f135eaf	24	#include <linux/clk.h>
1dbae815	25
120db2cb	26	#include <asm/tlb.h>
120db2cb TL	27
	28	#include <asm/mach/map.h>
	29
a09e64fb RK	30	#include <mach/mux.h>
a09e64fb RK	31	#include <mach/omapfb.h>
646e3ed1	32	#include <mach/sram.h>
f8de9b2c PW	33	#include <mach/sdrc.h>
f8de9b2c PW	34	#include <mach/gpmc.h>
646e3ed1	35
44169075	36	#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
646e3ed1	37	#include "clock.h"
1dbae815	38
9717100f PW	39	#include <mach/powerdomain.h>
	40
	41	#include "powerdomains.h"
1dbae815	42
801954d3 PW	43	#include <mach/clockdomain.h>
801954d3 PW	44	#include "clockdomains.h"
44169075	45	#endif
1dbae815 TL	46	/*
	47	* The machine specific code may provide the extra mapping besides the
	48	* default mapping provided here.
	49	*/
cc26b3b0 SMK	50
	51	#ifdef CONFIG_ARCH_OMAP24XX
	52	static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815 TL	53	{
	54	.virtual = L3_24XX_VIRT,
	55	.pfn = __phys_to_pfn(L3_24XX_PHYS),
	56	.length = L3_24XX_SIZE,
	57	.type = MT_DEVICE
	58	},
09f21ed4	59	{
cc26b3b0 SMK	60	.virtual = L4_24XX_VIRT,
	61	.pfn = __phys_to_pfn(L4_24XX_PHYS),
	62	.length = L4_24XX_SIZE,
	63	.type = MT_DEVICE
09f21ed4	64	},
cc26b3b0 SMK	65	};
	66
	67	#ifdef CONFIG_ARCH_OMAP2420
	68	static struct map_desc omap242x_io_desc[] __initdata = {
	69	{
	70	.virtual = DSP_MEM_24XX_VIRT,
	71	.pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
	72	.length = DSP_MEM_24XX_SIZE,
	73	.type = MT_DEVICE
	74	},
	75	{
	76	.virtual = DSP_IPI_24XX_VIRT,
	77	.pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
	78	.length = DSP_IPI_24XX_SIZE,
	79	.type = MT_DEVICE
09f21ed4	80	},
cc26b3b0 SMK	81	{
	82	.virtual = DSP_MMU_24XX_VIRT,
	83	.pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
	84	.length = DSP_MMU_24XX_SIZE,
	85	.type = MT_DEVICE
	86	},
	87	};
	88
	89	#endif
	90
72d0f1c3	91	#ifdef CONFIG_ARCH_OMAP2430
cc26b3b0	92	static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3 SMK	93	{
	94	.virtual = L4_WK_243X_VIRT,
	95	.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
	96	.length = L4_WK_243X_SIZE,
	97	.type = MT_DEVICE
	98	},
	99	{
	100	.virtual = OMAP243X_GPMC_VIRT,
	101	.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
	102	.length = OMAP243X_GPMC_SIZE,
	103	.type = MT_DEVICE
	104	},
cc26b3b0 SMK	105	{
	106	.virtual = OMAP243X_SDRC_VIRT,
	107	.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
	108	.length = OMAP243X_SDRC_SIZE,
	109	.type = MT_DEVICE
	110	},
	111	{
	112	.virtual = OMAP243X_SMS_VIRT,
	113	.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
	114	.length = OMAP243X_SMS_SIZE,
	115	.type = MT_DEVICE
	116	},
	117	};
72d0f1c3	118	#endif
72d0f1c3	119	#endif
cc26b3b0 SMK	120
	121	#ifdef CONFIG_ARCH_OMAP34XX
	122	static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815	123	{
cc26b3b0 SMK	124	.virtual = L3_34XX_VIRT,
	125	.pfn = __phys_to_pfn(L3_34XX_PHYS),
	126	.length = L3_34XX_SIZE,
c40fae95 TL	127	.type = MT_DEVICE
	128	},
	129	{
cc26b3b0 SMK	130	.virtual = L4_34XX_VIRT,
	131	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	132	.length = L4_34XX_SIZE,
c40fae95 TL	133	.type = MT_DEVICE
	134	},
	135	{
cc26b3b0 SMK	136	.virtual = L4_WK_34XX_VIRT,
	137	.pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
	138	.length = L4_WK_34XX_SIZE,
	139	.type = MT_DEVICE
	140	},
	141	{
	142	.virtual = OMAP34XX_GPMC_VIRT,
	143	.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
	144	.length = OMAP34XX_GPMC_SIZE,
1dbae815	145	.type = MT_DEVICE
cc26b3b0 SMK	146	},
	147	{
	148	.virtual = OMAP343X_SMS_VIRT,
	149	.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
	150	.length = OMAP343X_SMS_SIZE,
	151	.type = MT_DEVICE
	152	},
	153	{
	154	.virtual = OMAP343X_SDRC_VIRT,
	155	.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
	156	.length = OMAP343X_SDRC_SIZE,
1dbae815	157	.type = MT_DEVICE
cc26b3b0 SMK	158	},
	159	{
	160	.virtual = L4_PER_34XX_VIRT,
	161	.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
	162	.length = L4_PER_34XX_SIZE,
	163	.type = MT_DEVICE
	164	},
	165	{
	166	.virtual = L4_EMU_34XX_VIRT,
	167	.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
	168	.length = L4_EMU_34XX_SIZE,
	169	.type = MT_DEVICE
	170	},
1dbae815	171	};
cc26b3b0	172	#endif
44169075 SS	173	#ifdef CONFIG_ARCH_OMAP4
	174	static struct map_desc omap44xx_io_desc[] __initdata = {
	175	{
	176	.virtual = L3_44XX_VIRT,
	177	.pfn = __phys_to_pfn(L3_44XX_PHYS),
	178	.length = L3_44XX_SIZE,
	179	.type = MT_DEVICE,
	180	},
	181	{
	182	.virtual = L4_44XX_VIRT,
	183	.pfn = __phys_to_pfn(L4_44XX_PHYS),
	184	.length = L4_44XX_SIZE,
	185	.type = MT_DEVICE,
	186	},
	187	{
	188	.virtual = L4_WK_44XX_VIRT,
	189	.pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
	190	.length = L4_WK_44XX_SIZE,
	191	.type = MT_DEVICE,
	192	},
	193	{
	194	.virtual = OMAP44XX_GPMC_VIRT,
	195	.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
	196	.length = OMAP44XX_GPMC_SIZE,
	197	.type = MT_DEVICE,
	198	},
	199	{
	200	.virtual = L4_PER_44XX_VIRT,
	201	.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
	202	.length = L4_PER_44XX_SIZE,
	203	.type = MT_DEVICE,
	204	},
	205	{
	206	.virtual = L4_EMU_44XX_VIRT,
	207	.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
	208	.length = L4_EMU_44XX_SIZE,
	209	.type = MT_DEVICE,
	210	},
	211	};
	212	#endif
1dbae815	213
120db2cb	214	void __init omap2_map_common_io(void)
1dbae815	215	{
cc26b3b0 SMK	216	#if defined(CONFIG_ARCH_OMAP2420)
	217	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	218	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
	219	#endif
	220
	221	#if defined(CONFIG_ARCH_OMAP2430)
	222	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	223	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
	224	#endif
	225
	226	#if defined(CONFIG_ARCH_OMAP34XX)
	227	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
	228	#endif
120db2cb	229
44169075 SS	230	#if defined(CONFIG_ARCH_OMAP4)
	231	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
	232	#endif
120db2cb TL	233	/* Normally devicemaps_init() would flush caches and tlb after
	234	* mdesc->map_io(), but we must also do it here because of the CPU
	235	* revision check below.
	236	*/
	237	local_flush_tlb_all();
	238	flush_cache_all();
	239
1dbae815 TL	240	omap2_check_revision();
1dbae815 TL	241	omap_sram_init();
b7cc6d46	242	omapfb_reserve_sdram();
120db2cb TL	243	}
120db2cb TL	244
2f135eaf PW	245	/*
	246	* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
	247	*
	248	* Sets the CORE DPLL3 M2 divider to the same value that it's at
	249	* currently. This has the effect of setting the SDRC SDRAM AC timing
	250	* registers to the values currently defined by the kernel. Currently
	251	* only defined for OMAP3; will return 0 if called on OMAP2. Returns
	252	* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
	253	* or passes along the return value of clk_set_rate().
	254	*/
	255	static int __init _omap2_init_reprogram_sdrc(void)
	256	{
	257	struct clk *dpll3_m2_ck;
	258	int v = -EINVAL;
	259	long rate;
	260
	261	if (!cpu_is_omap34xx())
	262	return 0;
	263
	264	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	265	if (!dpll3_m2_ck)
	266	return -EINVAL;
	267
	268	rate = clk_get_rate(dpll3_m2_ck);
	269	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	270	v = clk_set_rate(dpll3_m2_ck, rate);
	271	if (v)
	272	pr_err("dpll3_m2_clk rate change failed: %d\n", v);
	273
	274	clk_put(dpll3_m2_ck);
	275
	276	return v;
	277	}
	278
87246b75	279	void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
120db2cb	280	{
1dbae815	281	omap2_mux_init();
44169075	282	#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
9717100f	283	pwrdm_init(powerdomains_omap);
801954d3	284	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
1dbae815	285	omap2_clk_init();
87246b75	286	omap2_sdrc_init(sp);
2f135eaf	287	_omap2_init_reprogram_sdrc();
44169075	288	#endif
4bbbc1ad	289	gpmc_init();
1dbae815	290	}