[deliverable/linux.git] / arch / arm / mach-omap2 / io.c

/*
 * linux/arch/arm/mach-omap2/io.c
 *
 * OMAP2 I/O mapping code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Copyright (C) 2007-2009 Texas Instruments
 *
 * Author:
 *	Juha Yrjola <juha.yrjola@nokia.com>
 *	Syed Khasim <x0khasim@ti.com>
 *
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <asm/tlb.h>

#include <asm/mach/map.h>

#include <mach/mux.h>
#include <mach/omapfb.h>
#include <mach/sram.h>
#include <mach/sdrc.h>
#include <mach/gpmc.h>
#include <mach/serial.h>

#ifndef CONFIG_ARCH_OMAP4	/* FIXME: Remove this once clkdev is ready */
#include "clock.h"

#include <mach/omap-pm.h>
#include <mach/powerdomain.h>

#include "powerdomains.h"

#include <mach/clockdomain.h>
#include "clockdomains.h"
#endif
/*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
 */

#ifdef CONFIG_ARCH_OMAP24XX
static struct map_desc omap24xx_io_desc[] __initdata = {
	{
		.virtual	= L3_24XX_VIRT,
		.pfn		= __phys_to_pfn(L3_24XX_PHYS),
		.length		= L3_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_24XX_VIRT,
		.pfn		= __phys_to_pfn(L4_24XX_PHYS),
		.length		= L4_24XX_SIZE,
		.type		= MT_DEVICE
	},
};

#ifdef CONFIG_ARCH_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
	{
		.virtual	= DSP_MEM_24XX_VIRT,
		.pfn		= __phys_to_pfn(DSP_MEM_24XX_PHYS),
		.length		= DSP_MEM_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_IPI_24XX_VIRT,
		.pfn		= __phys_to_pfn(DSP_IPI_24XX_PHYS),
		.length		= DSP_IPI_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_MMU_24XX_VIRT,
		.pfn		= __phys_to_pfn(DSP_MMU_24XX_PHYS),
		.length		= DSP_MMU_24XX_SIZE,
		.type		= MT_DEVICE
	},
};

#endif

#ifdef CONFIG_ARCH_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
	{
		.virtual	= L4_WK_243X_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_243X_PHYS),
		.length		= L4_WK_243X_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_GPMC_PHYS),
		.length		= OMAP243X_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SDRC_PHYS),
		.length		= OMAP243X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SMS_PHYS),
		.length		= OMAP243X_SMS_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#endif

#ifdef	CONFIG_ARCH_OMAP34XX
static struct map_desc omap34xx_io_desc[] __initdata = {
	{
		.virtual	= L3_34XX_VIRT,
		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
		.length		= L3_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_WK_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_34XX_PHYS),
		.length		= L4_WK_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP34XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
		.length		= OMAP34XX_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
		.length		= OMAP343X_SMS_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
		.length		= OMAP343X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_PER_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_34XX_PHYS),
		.length		= L4_PER_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_EMU_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
		.length		= L4_EMU_34XX_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#ifdef	CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
	{
		.virtual	= L3_44XX_VIRT,
		.pfn		= __phys_to_pfn(L3_44XX_PHYS),
		.length		= L3_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_44XX_PHYS),
		.length		= L4_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_WK_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_44XX_PHYS),
		.length		= L4_WK_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_GPMC_PHYS),
		.length		= OMAP44XX_GPMC_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_PER_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_44XX_PHYS),
		.length		= L4_PER_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_EMU_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_44XX_PHYS),
		.length		= L4_EMU_44XX_SIZE,
		.type		= MT_DEVICE,
	},
};
#endif

void __init omap2_map_common_io(void)
{
#if defined(CONFIG_ARCH_OMAP2420)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP2430)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP4)
	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
#endif
	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
	omapfb_reserve_sdram();
}

/*
 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 *
 * Sets the CORE DPLL3 M2 divider to the same value that it's at
 * currently.  This has the effect of setting the SDRC SDRAM AC timing
 * registers to the values currently defined by the kernel.  Currently
 * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 * or passes along the return value of clk_set_rate().
 */
static int __init _omap2_init_reprogram_sdrc(void)
{
	struct clk *dpll3_m2_ck;
	int v = -EINVAL;
	long rate;

	if (!cpu_is_omap34xx())
		return 0;

	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	if (!dpll3_m2_ck)
		return -EINVAL;

	rate = clk_get_rate(dpll3_m2_ck);
	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	v = clk_set_rate(dpll3_m2_ck, rate);
	if (v)
		pr_err("dpll3_m2_clk rate change failed: %d\n", v);

	clk_put(dpll3_m2_ck);

	return v;
}

void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
				 struct omap_sdrc_params *sdrc_cs1)
{
	omap2_mux_init();
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
	/* The OPP tables have to be registered before a clk init */
	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
	pwrdm_init(powerdomains_omap);
	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
	omap2_clk_init();
	omap_serial_early_init();
	omap_pm_if_init();
	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
	_omap2_init_reprogram_sdrc();
#endif
	gpmc_init();
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/io.c
	3	*
	4	* OMAP2 I/O mapping code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
44169075	7	* Copyright (C) 2007-2009 Texas Instruments
646e3ed1 TL	8	*
	9	* Author:
	10	* Juha Yrjola <juha.yrjola@nokia.com>
	11	* Syed Khasim <x0khasim@ti.com>
1dbae815	12	*
44169075 SS	13	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
44169075 SS	14	*
1dbae815 TL	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
1dbae815 TL	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
fced80c7	23	#include <linux/io.h>
2f135eaf	24	#include <linux/clk.h>
1dbae815	25
120db2cb	26	#include <asm/tlb.h>
120db2cb TL	27
	28	#include <asm/mach/map.h>
	29
a09e64fb RK	30	#include <mach/mux.h>
a09e64fb RK	31	#include <mach/omapfb.h>
646e3ed1	32	#include <mach/sram.h>
f8de9b2c PW	33	#include <mach/sdrc.h>
f8de9b2c PW	34	#include <mach/gpmc.h>
b3c6df3a	35	#include <mach/serial.h>
646e3ed1	36
44169075	37	#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
646e3ed1	38	#include "clock.h"
1dbae815	39
c0407a96	40	#include <mach/omap-pm.h>
9717100f PW	41	#include <mach/powerdomain.h>
	42
	43	#include "powerdomains.h"
1dbae815	44
801954d3 PW	45	#include <mach/clockdomain.h>
801954d3 PW	46	#include "clockdomains.h"
44169075	47	#endif
1dbae815 TL	48	/*
	49	* The machine specific code may provide the extra mapping besides the
	50	* default mapping provided here.
	51	*/
cc26b3b0 SMK	52
	53	#ifdef CONFIG_ARCH_OMAP24XX
	54	static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815 TL	55	{
	56	.virtual = L3_24XX_VIRT,
	57	.pfn = __phys_to_pfn(L3_24XX_PHYS),
	58	.length = L3_24XX_SIZE,
	59	.type = MT_DEVICE
	60	},
09f21ed4	61	{
cc26b3b0 SMK	62	.virtual = L4_24XX_VIRT,
	63	.pfn = __phys_to_pfn(L4_24XX_PHYS),
	64	.length = L4_24XX_SIZE,
	65	.type = MT_DEVICE
09f21ed4	66	},
cc26b3b0 SMK	67	};
	68
	69	#ifdef CONFIG_ARCH_OMAP2420
	70	static struct map_desc omap242x_io_desc[] __initdata = {
	71	{
	72	.virtual = DSP_MEM_24XX_VIRT,
	73	.pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
	74	.length = DSP_MEM_24XX_SIZE,
	75	.type = MT_DEVICE
	76	},
	77	{
	78	.virtual = DSP_IPI_24XX_VIRT,
	79	.pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
	80	.length = DSP_IPI_24XX_SIZE,
	81	.type = MT_DEVICE
09f21ed4	82	},
cc26b3b0 SMK	83	{
	84	.virtual = DSP_MMU_24XX_VIRT,
	85	.pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
	86	.length = DSP_MMU_24XX_SIZE,
	87	.type = MT_DEVICE
	88	},
	89	};
	90
	91	#endif
	92
72d0f1c3	93	#ifdef CONFIG_ARCH_OMAP2430
cc26b3b0	94	static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3 SMK	95	{
	96	.virtual = L4_WK_243X_VIRT,
	97	.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
	98	.length = L4_WK_243X_SIZE,
	99	.type = MT_DEVICE
	100	},
	101	{
	102	.virtual = OMAP243X_GPMC_VIRT,
	103	.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
	104	.length = OMAP243X_GPMC_SIZE,
	105	.type = MT_DEVICE
	106	},
cc26b3b0 SMK	107	{
	108	.virtual = OMAP243X_SDRC_VIRT,
	109	.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
	110	.length = OMAP243X_SDRC_SIZE,
	111	.type = MT_DEVICE
	112	},
	113	{
	114	.virtual = OMAP243X_SMS_VIRT,
	115	.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
	116	.length = OMAP243X_SMS_SIZE,
	117	.type = MT_DEVICE
	118	},
	119	};
72d0f1c3	120	#endif
72d0f1c3	121	#endif
cc26b3b0 SMK	122
	123	#ifdef CONFIG_ARCH_OMAP34XX
	124	static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815	125	{
cc26b3b0 SMK	126	.virtual = L3_34XX_VIRT,
	127	.pfn = __phys_to_pfn(L3_34XX_PHYS),
	128	.length = L3_34XX_SIZE,
c40fae95 TL	129	.type = MT_DEVICE
	130	},
	131	{
cc26b3b0 SMK	132	.virtual = L4_34XX_VIRT,
	133	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	134	.length = L4_34XX_SIZE,
c40fae95 TL	135	.type = MT_DEVICE
	136	},
	137	{
cc26b3b0 SMK	138	.virtual = L4_WK_34XX_VIRT,
	139	.pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
	140	.length = L4_WK_34XX_SIZE,
	141	.type = MT_DEVICE
	142	},
	143	{
	144	.virtual = OMAP34XX_GPMC_VIRT,
	145	.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
	146	.length = OMAP34XX_GPMC_SIZE,
1dbae815	147	.type = MT_DEVICE
cc26b3b0 SMK	148	},
	149	{
	150	.virtual = OMAP343X_SMS_VIRT,
	151	.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
	152	.length = OMAP343X_SMS_SIZE,
	153	.type = MT_DEVICE
	154	},
	155	{
	156	.virtual = OMAP343X_SDRC_VIRT,
	157	.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
	158	.length = OMAP343X_SDRC_SIZE,
1dbae815	159	.type = MT_DEVICE
cc26b3b0 SMK	160	},
	161	{
	162	.virtual = L4_PER_34XX_VIRT,
	163	.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
	164	.length = L4_PER_34XX_SIZE,
	165	.type = MT_DEVICE
	166	},
	167	{
	168	.virtual = L4_EMU_34XX_VIRT,
	169	.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
	170	.length = L4_EMU_34XX_SIZE,
	171	.type = MT_DEVICE
	172	},
1dbae815	173	};
cc26b3b0	174	#endif
44169075 SS	175	#ifdef CONFIG_ARCH_OMAP4
	176	static struct map_desc omap44xx_io_desc[] __initdata = {
	177	{
	178	.virtual = L3_44XX_VIRT,
	179	.pfn = __phys_to_pfn(L3_44XX_PHYS),
	180	.length = L3_44XX_SIZE,
	181	.type = MT_DEVICE,
	182	},
	183	{
	184	.virtual = L4_44XX_VIRT,
	185	.pfn = __phys_to_pfn(L4_44XX_PHYS),
	186	.length = L4_44XX_SIZE,
	187	.type = MT_DEVICE,
	188	},
	189	{
	190	.virtual = L4_WK_44XX_VIRT,
	191	.pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
	192	.length = L4_WK_44XX_SIZE,
	193	.type = MT_DEVICE,
	194	},
	195	{
	196	.virtual = OMAP44XX_GPMC_VIRT,
	197	.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
	198	.length = OMAP44XX_GPMC_SIZE,
	199	.type = MT_DEVICE,
	200	},
	201	{
	202	.virtual = L4_PER_44XX_VIRT,
	203	.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
	204	.length = L4_PER_44XX_SIZE,
	205	.type = MT_DEVICE,
	206	},
	207	{
	208	.virtual = L4_EMU_44XX_VIRT,
	209	.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
	210	.length = L4_EMU_44XX_SIZE,
	211	.type = MT_DEVICE,
	212	},
	213	};
	214	#endif
1dbae815	215
120db2cb	216	void __init omap2_map_common_io(void)
1dbae815	217	{
cc26b3b0 SMK	218	#if defined(CONFIG_ARCH_OMAP2420)
	219	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	220	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
	221	#endif
	222
	223	#if defined(CONFIG_ARCH_OMAP2430)
	224	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	225	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
	226	#endif
	227
	228	#if defined(CONFIG_ARCH_OMAP34XX)
	229	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
	230	#endif
120db2cb	231
44169075 SS	232	#if defined(CONFIG_ARCH_OMAP4)
	233	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
	234	#endif
120db2cb TL	235	/* Normally devicemaps_init() would flush caches and tlb after
	236	* mdesc->map_io(), but we must also do it here because of the CPU
	237	* revision check below.
	238	*/
	239	local_flush_tlb_all();
	240	flush_cache_all();
	241
1dbae815 TL	242	omap2_check_revision();
1dbae815 TL	243	omap_sram_init();
b7cc6d46	244	omapfb_reserve_sdram();
120db2cb TL	245	}
120db2cb TL	246
2f135eaf PW	247	/*
	248	* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
	249	*
	250	* Sets the CORE DPLL3 M2 divider to the same value that it's at
	251	* currently. This has the effect of setting the SDRC SDRAM AC timing
	252	* registers to the values currently defined by the kernel. Currently
	253	* only defined for OMAP3; will return 0 if called on OMAP2. Returns
	254	* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
	255	* or passes along the return value of clk_set_rate().
	256	*/
	257	static int __init _omap2_init_reprogram_sdrc(void)
	258	{
	259	struct clk *dpll3_m2_ck;
	260	int v = -EINVAL;
	261	long rate;
	262
	263	if (!cpu_is_omap34xx())
	264	return 0;
	265
	266	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	267	if (!dpll3_m2_ck)
	268	return -EINVAL;
	269
	270	rate = clk_get_rate(dpll3_m2_ck);
	271	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	272	v = clk_set_rate(dpll3_m2_ck, rate);
	273	if (v)
	274	pr_err("dpll3_m2_clk rate change failed: %d\n", v);
	275
	276	clk_put(dpll3_m2_ck);
	277
	278	return v;
	279	}
	280
58cda884 JP	281	void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
58cda884 JP	282	struct omap_sdrc_params *sdrc_cs1)
120db2cb	283	{
1dbae815	284	omap2_mux_init();
44169075	285	#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
c0407a96 PW	286	/* The OPP tables have to be registered before a clk init */
c0407a96 PW	287	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
9717100f	288	pwrdm_init(powerdomains_omap);
801954d3	289	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
1dbae815	290	omap2_clk_init();
b3c6df3a	291	omap_serial_early_init();
c0407a96	292	omap_pm_if_init();
58cda884	293	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
2f135eaf	294	_omap2_init_reprogram_sdrc();
44169075	295	#endif
4bbbc1ad	296	gpmc_init();
1dbae815	297	}