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ARM: OMAP4: hwmod data: Add names for DMIC memory address space
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
91773a00 24#include <linux/omapfb.h>
1dbae815 25
120db2cb 26#include <asm/tlb.h>
120db2cb
TL		 27
28#include <asm/mach/map.h>
29
ce491cf8
TL		 30#include <plat/sram.h>
31#include <plat/sdrc.h>
ce491cf8 32#include <plat/serial.h>
646e3ed1 33
e80a9729 34#include "clock2xxx.h"
657ebfad 35#include "clock3xxx.h"
e80a9729 36#include "clock44xx.h"
1dbae815 37
4e65331c 38#include "common.h"
ce491cf8 39#include <plat/omap-pm.h>
81a60482 40#include "voltage.h"
72e06d08 41#include "powerdomain.h"
1dbae815 42
1540f214 43#include "clockdomain.h"
ce491cf8 44#include <plat/omap_hwmod.h>
5d190c40 45#include <plat/multi.h>
4e65331c 46#include "common.h"
02bfc030 47
1dbae815
TL		 48/*
49 * The machine specific code may provide the extra mapping besides the
50 * default mapping provided here.
51 */
cc26b3b0 52
088ef950 53#ifdef CONFIG_ARCH_OMAP2
cc26b3b0 54static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 55 {
56 .virtual = L3_24XX_VIRT,
57 .pfn = __phys_to_pfn(L3_24XX_PHYS),
58 .length = L3_24XX_SIZE,
59 .type = MT_DEVICE
60 },
09f21ed4 61 {
cc26b3b0
SMK		 62 .virtual = L4_24XX_VIRT,
63 .pfn = __phys_to_pfn(L4_24XX_PHYS),
64 .length = L4_24XX_SIZE,
65 .type = MT_DEVICE
09f21ed4 66 },
cc26b3b0
SMK		 67};
68
59b479e0 69#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 70static struct map_desc omap242x_io_desc[] __initdata = {
71 {
7adb9987
PW		 72 .virtual = DSP_MEM_2420_VIRT,
73 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
74 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 75 .type = MT_DEVICE
76 },
77 {
7adb9987
PW		 78 .virtual = DSP_IPI_2420_VIRT,
79 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
80 .length = DSP_IPI_2420_SIZE,
cc26b3b0 81 .type = MT_DEVICE
09f21ed4 82 },
cc26b3b0 83 {
7adb9987
PW		 84 .virtual = DSP_MMU_2420_VIRT,
85 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
86 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 87 .type = MT_DEVICE
88 },
89};
90
91#endif
92
59b479e0 93#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 94static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 95 {
96 .virtual = L4_WK_243X_VIRT,
97 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
98 .length = L4_WK_243X_SIZE,
99 .type = MT_DEVICE
100 },
101 {
102 .virtual = OMAP243X_GPMC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
104 .length = OMAP243X_GPMC_SIZE,
105 .type = MT_DEVICE
106 },
cc26b3b0
SMK		 107 {
108 .virtual = OMAP243X_SDRC_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
110 .length = OMAP243X_SDRC_SIZE,
111 .type = MT_DEVICE
112 },
113 {
114 .virtual = OMAP243X_SMS_VIRT,
115 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
116 .length = OMAP243X_SMS_SIZE,
117 .type = MT_DEVICE
118 },
119};
72d0f1c3 120#endif
72d0f1c3 121#endif
cc26b3b0 122
a8eb7ca0 123#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 124static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 125 {
cc26b3b0
SMK		 126 .virtual = L3_34XX_VIRT,
127 .pfn = __phys_to_pfn(L3_34XX_PHYS),
128 .length = L3_34XX_SIZE,
c40fae95
TL		 129 .type = MT_DEVICE
130 },
131 {
cc26b3b0
SMK		 132 .virtual = L4_34XX_VIRT,
133 .pfn = __phys_to_pfn(L4_34XX_PHYS),
134 .length = L4_34XX_SIZE,
c40fae95
TL		 135 .type = MT_DEVICE
136 },
cc26b3b0
SMK		 137 {
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
1dbae815 141 .type = MT_DEVICE
cc26b3b0
SMK		 142 },
143 {
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
1dbae815 153 .type = MT_DEVICE
cc26b3b0
SMK		 154 },
155 {
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
165 .type = MT_DEVICE
166 },
a4f57b81
TL		 167#if defined(CONFIG_DEBUG_LL) && \
168 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
169 {
170 .virtual = ZOOM_UART_VIRT,
171 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
172 .length = SZ_1M,
173 .type = MT_DEVICE
174 },
175#endif
1dbae815 176};
cc26b3b0 177#endif
01001712 178
a920360f
HP		 179#ifdef CONFIG_SOC_OMAPTI81XX
180static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 181 {
182 .virtual = L4_34XX_VIRT,
183 .pfn = __phys_to_pfn(L4_34XX_PHYS),
184 .length = L4_34XX_SIZE,
185 .type = MT_DEVICE
186 }
187};
188#endif
189
190#ifdef CONFIG_SOC_OMAPAM33XX
191static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 192 {
193 .virtual = L4_34XX_VIRT,
194 .pfn = __phys_to_pfn(L4_34XX_PHYS),
195 .length = L4_34XX_SIZE,
196 .type = MT_DEVICE
197 },
1e6cb146
AM		 198 {
199 .virtual = L4_WK_AM33XX_VIRT,
200 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
201 .length = L4_WK_AM33XX_SIZE,
202 .type = MT_DEVICE
203 }
01001712
HP		 204};
205#endif
206
44169075
SS		 207#ifdef CONFIG_ARCH_OMAP4
208static struct map_desc omap44xx_io_desc[] __initdata = {
209 {
210 .virtual = L3_44XX_VIRT,
211 .pfn = __phys_to_pfn(L3_44XX_PHYS),
212 .length = L3_44XX_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = L4_44XX_VIRT,
217 .pfn = __phys_to_pfn(L4_44XX_PHYS),
218 .length = L4_44XX_SIZE,
219 .type = MT_DEVICE,
220 },
44169075
SS		 221 {
222 .virtual = OMAP44XX_GPMC_VIRT,
223 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
224 .length = OMAP44XX_GPMC_SIZE,
225 .type = MT_DEVICE,
226 },
f5d2d659
SS		 227 {
228 .virtual = OMAP44XX_EMIF1_VIRT,
229 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
230 .length = OMAP44XX_EMIF1_SIZE,
231 .type = MT_DEVICE,
232 },
233 {
234 .virtual = OMAP44XX_EMIF2_VIRT,
235 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
236 .length = OMAP44XX_EMIF2_SIZE,
237 .type = MT_DEVICE,
238 },
239 {
240 .virtual = OMAP44XX_DMM_VIRT,
241 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
242 .length = OMAP44XX_DMM_SIZE,
243 .type = MT_DEVICE,
244 },
44169075
SS		 245 {
246 .virtual = L4_PER_44XX_VIRT,
247 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
248 .length = L4_PER_44XX_SIZE,
249 .type = MT_DEVICE,
250 },
251 {
252 .virtual = L4_EMU_44XX_VIRT,
253 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
254 .length = L4_EMU_44XX_SIZE,
255 .type = MT_DEVICE,
256 },
137d105d
SS		 257#ifdef CONFIG_OMAP4_ERRATA_I688
258 {
259 .virtual = OMAP4_SRAM_VA,
260 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
261 .length = PAGE_SIZE,
262 .type = MT_MEMORY_SO,
263 },
264#endif
265
44169075
SS		 266};
267#endif
1dbae815 268
59b479e0 269#ifdef CONFIG_SOC_OMAP2420
8185e468 270void __init omap242x_map_common_io(void)
1dbae815 271{
cc26b3b0
SMK		 272 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
273 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 274}
cc26b3b0
SMK		 275#endif
276
59b479e0 277#ifdef CONFIG_SOC_OMAP2430
8185e468 278void __init omap243x_map_common_io(void)
6fbd55d0 279{
cc26b3b0
SMK		 280 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
281 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 282}
cc26b3b0
SMK		 283#endif
284
a8eb7ca0 285#ifdef CONFIG_ARCH_OMAP3
8185e468 286void __init omap34xx_map_common_io(void)
6fbd55d0 287{
cc26b3b0 288 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 289}
cc26b3b0 290#endif
120db2cb 291
a920360f
HP		 292#ifdef CONFIG_SOC_OMAPTI81XX
293void __init omapti81xx_map_common_io(void)
01001712 294{
a920360f 295 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 296}
297#endif
298
1e6cb146
AM		 299#ifdef CONFIG_SOC_OMAPAM33XX
300void __init omapam33xx_map_common_io(void)
01001712 301{
1e6cb146 302 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 303}
304#endif
305
6fbd55d0 306#ifdef CONFIG_ARCH_OMAP4
8185e468 307void __init omap44xx_map_common_io(void)
6fbd55d0 308{
44169075 309 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
120db2cb 310}
6fbd55d0 311#endif
120db2cb 312
2f135eaf
PW		 313/*
314 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
315 *
316 * Sets the CORE DPLL3 M2 divider to the same value that it's at
317 * currently. This has the effect of setting the SDRC SDRAM AC timing
318 * registers to the values currently defined by the kernel. Currently
319 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
320 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
321 * or passes along the return value of clk_set_rate().
322 */
323static int __init _omap2_init_reprogram_sdrc(void)
324{
325 struct clk *dpll3_m2_ck;
326 int v = -EINVAL;
327 long rate;
328
329 if (!cpu_is_omap34xx())
330 return 0;
331
332 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 333 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 334 return -EINVAL;
335
336 rate = clk_get_rate(dpll3_m2_ck);
337 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
338 v = clk_set_rate(dpll3_m2_ck, rate);
339 if (v)
340 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
341
342 clk_put(dpll3_m2_ck);
343
344 return v;
345}
346
2092e5cc
PW		 347static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
348{
349 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
350}
351
7b250aff 352static void __init omap_common_init_early(void)
120db2cb 353{
7b250aff 354 omap2_check_revision();
df80442d 355 omap_init_consistent_dma_size();
7b250aff 356}
2092e5cc 357
7b250aff
TL		 358static void __init omap_hwmod_init_postsetup(void)
359{
360 u8 postsetup_state;
2092e5cc
PW		 361
362 /* Set the default postsetup state for all hwmods */
363#ifdef CONFIG_PM_RUNTIME
364 postsetup_state = _HWMOD_STATE_IDLE;
365#else
366 postsetup_state = _HWMOD_STATE_ENABLED;
367#endif
368 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 369
ff2516fb
PW		 370 /*
371 * Set the default postsetup state for unusual modules (like
372 * MPU WDT).
373 *
374 * The postsetup_state is not actually used until
375 * omap_hwmod_late_init(), so boards that desire full watchdog
376 * coverage of kernel initialization can reprogram the
377 * postsetup_state between the calls to
a4ca9dbe 378 * omap2_init_common_infra() and omap_sdrc_init().
ff2516fb
PW		 379 *
380 * XXX ideally we could detect whether the MPU WDT was currently
381 * enabled here and make this conditional
382 */
383 postsetup_state = _HWMOD_STATE_DISABLED;
384 omap_hwmod_for_each_by_class("wd_timer",
385 _set_hwmod_postsetup_state,
386 &postsetup_state);
387
53da4ce2 388 omap_pm_if_early_init();
4805734b
PW		 389}
390
c4e2d245 391#ifdef CONFIG_ARCH_OMAP2
8f5b5a41
TL		 392void __init omap2420_init_early(void)
393{
4c3cf901 394 omap2_set_globals_242x();
7b250aff
TL		 395 omap_common_init_early();
396 omap2xxx_voltagedomains_init();
397 omap242x_powerdomains_init();
398 omap242x_clockdomains_init();
399 omap2420_hwmod_init();
400 omap_hwmod_init_postsetup();
401 omap2420_clk_init();
8f5b5a41
TL		 402}
403
404void __init omap2430_init_early(void)
405{
4c3cf901 406 omap2_set_globals_243x();
7b250aff
TL		 407 omap_common_init_early();
408 omap2xxx_voltagedomains_init();
409 omap243x_powerdomains_init();
410 omap243x_clockdomains_init();
411 omap2430_hwmod_init();
412 omap_hwmod_init_postsetup();
413 omap2430_clk_init();
414}
c4e2d245 415#endif
7b250aff
TL		 416
417/*
418 * Currently only board-omap3beagle.c should call this because of the
419 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
420 */
c4e2d245 421#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 422void __init omap3_init_early(void)
423{
4c3cf901 424 omap2_set_globals_3xxx();
7b250aff
TL		 425 omap_common_init_early();
426 omap3xxx_voltagedomains_init();
427 omap3xxx_powerdomains_init();
428 omap3xxx_clockdomains_init();
429 omap3xxx_hwmod_init();
430 omap_hwmod_init_postsetup();
431 omap3xxx_clk_init();
8f5b5a41
TL		 432}
433
434void __init omap3430_init_early(void)
435{
7b250aff 436 omap3_init_early();
8f5b5a41
TL		 437}
438
439void __init omap35xx_init_early(void)
440{
7b250aff 441 omap3_init_early();
8f5b5a41
TL		 442}
443
444void __init omap3630_init_early(void)
445{
7b250aff 446 omap3_init_early();
8f5b5a41
TL		 447}
448
449void __init am35xx_init_early(void)
450{
7b250aff 451 omap3_init_early();
8f5b5a41
TL		 452}
453
a920360f 454void __init ti81xx_init_early(void)
8f5b5a41 455{
a920360f 456 omap2_set_globals_ti81xx();
4c3cf901
TL		 457 omap_common_init_early();
458 omap3xxx_voltagedomains_init();
459 omap3xxx_powerdomains_init();
460 omap3xxx_clockdomains_init();
461 omap3xxx_hwmod_init();
462 omap_hwmod_init_postsetup();
463 omap3xxx_clk_init();
8f5b5a41 464}
c4e2d245 465#endif
8f5b5a41 466
c4e2d245 467#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 468void __init omap4430_init_early(void)
469{
4c3cf901 470 omap2_set_globals_443x();
7b250aff
TL		 471 omap_common_init_early();
472 omap44xx_voltagedomains_init();
473 omap44xx_powerdomains_init();
474 omap44xx_clockdomains_init();
475 omap44xx_hwmod_init();
476 omap_hwmod_init_postsetup();
477 omap4xxx_clk_init();
8f5b5a41 478}
c4e2d245 479#endif
8f5b5a41 480
a4ca9dbe 481void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 482 struct omap_sdrc_params *sdrc_cs1)
483{
a66cb345
TL		 484 omap_sram_init();
485
01001712 486 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 487 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
488 _omap2_init_reprogram_sdrc();
489 }
1dbae815 490}
df1e9d1c
TL		 491
492/*
493 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
494 */
495
496u8 omap_readb(u32 pa)
497{
498 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
499}
500EXPORT_SYMBOL(omap_readb);
501
502u16 omap_readw(u32 pa)
503{
504 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
505}
506EXPORT_SYMBOL(omap_readw);
507
508u32 omap_readl(u32 pa)
509{
510 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
511}
512EXPORT_SYMBOL(omap_readl);
513
514void omap_writeb(u8 v, u32 pa)
515{
516 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
517}
518EXPORT_SYMBOL(omap_writeb);
519
520void omap_writew(u16 v, u32 pa)
521{
522 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
523}
524EXPORT_SYMBOL(omap_writew);
525
526void omap_writel(u32 v, u32 pa)
527{
528 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
529}
530EXPORT_SYMBOL(omap_writel);
Linux kernel - Deliverables
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