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ARM: OMAP2xxx: clock: add APLL rate recalculation functions
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
2b6c4e73 28#include <plat-omap/dma-omap.h>
ee0839c2 29
622297fd
TL		 30#include "../plat-omap/sram.h"
31
dc843280 32#include "omap_hwmod.h"
dbc04161 33#include "soc.h"
ee0839c2 34#include "iomap.h"
81a60482 35#include "voltage.h"
72e06d08 36#include "powerdomain.h"
1540f214 37#include "clockdomain.h"
4e65331c 38#include "common.h"
e30384ab 39#include "clock.h"
ee0839c2
TL		 40#include "clock2xxx.h"
41#include "clock3xxx.h"
42#include "clock44xx.h"
1d5aef49 43#include "omap-pm.h"
3e6ece13 44#include "sdrc.h"
b6a4226c 45#include "control.h"
3d82cbbb 46#include "serial.h"
c4ceedcb
PW		 47#include "cm2xxx.h"
48#include "cm3xxx.h"
d9a16f9a
PW		 49#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
53#include "cminst44xx.h"
1dbae815
TL		 54/*
55 * The machine specific code may provide the extra mapping besides the
56 * default mapping provided here.
57 */
cc26b3b0 58
e48f814e 59#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 60static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 61 {
62 .virtual = L3_24XX_VIRT,
63 .pfn = __phys_to_pfn(L3_24XX_PHYS),
64 .length = L3_24XX_SIZE,
65 .type = MT_DEVICE
66 },
09f21ed4 67 {
cc26b3b0
SMK		 68 .virtual = L4_24XX_VIRT,
69 .pfn = __phys_to_pfn(L4_24XX_PHYS),
70 .length = L4_24XX_SIZE,
71 .type = MT_DEVICE
09f21ed4 72 },
cc26b3b0
SMK		 73};
74
59b479e0 75#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 76static struct map_desc omap242x_io_desc[] __initdata = {
77 {
7adb9987
PW		 78 .virtual = DSP_MEM_2420_VIRT,
79 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
80 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 81 .type = MT_DEVICE
82 },
83 {
7adb9987
PW		 84 .virtual = DSP_IPI_2420_VIRT,
85 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
86 .length = DSP_IPI_2420_SIZE,
cc26b3b0 87 .type = MT_DEVICE
09f21ed4 88 },
cc26b3b0 89 {
7adb9987
PW		 90 .virtual = DSP_MMU_2420_VIRT,
91 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
92 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 93 .type = MT_DEVICE
94 },
95};
96
97#endif
98
59b479e0 99#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 100static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 101 {
102 .virtual = L4_WK_243X_VIRT,
103 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
104 .length = L4_WK_243X_SIZE,
105 .type = MT_DEVICE
106 },
107 {
108 .virtual = OMAP243X_GPMC_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
110 .length = OMAP243X_GPMC_SIZE,
111 .type = MT_DEVICE
112 },
cc26b3b0
SMK		 113 {
114 .virtual = OMAP243X_SDRC_VIRT,
115 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
116 .length = OMAP243X_SDRC_SIZE,
117 .type = MT_DEVICE
118 },
119 {
120 .virtual = OMAP243X_SMS_VIRT,
121 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
122 .length = OMAP243X_SMS_SIZE,
123 .type = MT_DEVICE
124 },
125};
72d0f1c3 126#endif
72d0f1c3 127#endif
cc26b3b0 128
a8eb7ca0 129#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 130static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 131 {
cc26b3b0
SMK		 132 .virtual = L3_34XX_VIRT,
133 .pfn = __phys_to_pfn(L3_34XX_PHYS),
134 .length = L3_34XX_SIZE,
c40fae95
TL		 135 .type = MT_DEVICE
136 },
137 {
cc26b3b0
SMK		 138 .virtual = L4_34XX_VIRT,
139 .pfn = __phys_to_pfn(L4_34XX_PHYS),
140 .length = L4_34XX_SIZE,
c40fae95
TL		 141 .type = MT_DEVICE
142 },
cc26b3b0
SMK		 143 {
144 .virtual = OMAP34XX_GPMC_VIRT,
145 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
146 .length = OMAP34XX_GPMC_SIZE,
1dbae815 147 .type = MT_DEVICE
cc26b3b0
SMK		 148 },
149 {
150 .virtual = OMAP343X_SMS_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
152 .length = OMAP343X_SMS_SIZE,
153 .type = MT_DEVICE
154 },
155 {
156 .virtual = OMAP343X_SDRC_VIRT,
157 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
158 .length = OMAP343X_SDRC_SIZE,
1dbae815 159 .type = MT_DEVICE
cc26b3b0
SMK		 160 },
161 {
162 .virtual = L4_PER_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
164 .length = L4_PER_34XX_SIZE,
165 .type = MT_DEVICE
166 },
167 {
168 .virtual = L4_EMU_34XX_VIRT,
169 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
170 .length = L4_EMU_34XX_SIZE,
171 .type = MT_DEVICE
172 },
a4f57b81
TL		 173#if defined(CONFIG_DEBUG_LL) && \
174 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
175 {
176 .virtual = ZOOM_UART_VIRT,
177 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
178 .length = SZ_1M,
179 .type = MT_DEVICE
180 },
181#endif
1dbae815 182};
cc26b3b0 183#endif
01001712 184
33959553 185#ifdef CONFIG_SOC_TI81XX
a920360f 186static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 187 {
188 .virtual = L4_34XX_VIRT,
189 .pfn = __phys_to_pfn(L4_34XX_PHYS),
190 .length = L4_34XX_SIZE,
191 .type = MT_DEVICE
192 }
193};
194#endif
195
bb6abcf4 196#ifdef CONFIG_SOC_AM33XX
1e6cb146 197static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 198 {
199 .virtual = L4_34XX_VIRT,
200 .pfn = __phys_to_pfn(L4_34XX_PHYS),
201 .length = L4_34XX_SIZE,
202 .type = MT_DEVICE
203 },
1e6cb146
AM		 204 {
205 .virtual = L4_WK_AM33XX_VIRT,
206 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
207 .length = L4_WK_AM33XX_SIZE,
208 .type = MT_DEVICE
209 }
01001712
HP		 210};
211#endif
212
44169075
SS		 213#ifdef CONFIG_ARCH_OMAP4
214static struct map_desc omap44xx_io_desc[] __initdata = {
215 {
216 .virtual = L3_44XX_VIRT,
217 .pfn = __phys_to_pfn(L3_44XX_PHYS),
218 .length = L3_44XX_SIZE,
219 .type = MT_DEVICE,
220 },
221 {
222 .virtual = L4_44XX_VIRT,
223 .pfn = __phys_to_pfn(L4_44XX_PHYS),
224 .length = L4_44XX_SIZE,
225 .type = MT_DEVICE,
226 },
44169075
SS		 227 {
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
137d105d
SS		 233#ifdef CONFIG_OMAP4_ERRATA_I688
234 {
235 .virtual = OMAP4_SRAM_VA,
236 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
237 .length = PAGE_SIZE,
238 .type = MT_MEMORY_SO,
239 },
240#endif
241
44169075
SS		 242};
243#endif
1dbae815 244
05e152c7
S		 245#ifdef CONFIG_SOC_OMAP5
246static struct map_desc omap54xx_io_desc[] __initdata = {
247 {
248 .virtual = L3_54XX_VIRT,
249 .pfn = __phys_to_pfn(L3_54XX_PHYS),
250 .length = L3_54XX_SIZE,
251 .type = MT_DEVICE,
252 },
253 {
254 .virtual = L4_54XX_VIRT,
255 .pfn = __phys_to_pfn(L4_54XX_PHYS),
256 .length = L4_54XX_SIZE,
257 .type = MT_DEVICE,
258 },
259 {
260 .virtual = L4_WK_54XX_VIRT,
261 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
262 .length = L4_WK_54XX_SIZE,
263 .type = MT_DEVICE,
264 },
265 {
266 .virtual = L4_PER_54XX_VIRT,
267 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
268 .length = L4_PER_54XX_SIZE,
269 .type = MT_DEVICE,
270 },
271};
272#endif
273
59b479e0 274#ifdef CONFIG_SOC_OMAP2420
b6a4226c 275void __init omap242x_map_io(void)
1dbae815 276{
cc26b3b0
SMK		 277 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
278 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 279}
cc26b3b0
SMK		 280#endif
281
59b479e0 282#ifdef CONFIG_SOC_OMAP2430
b6a4226c 283void __init omap243x_map_io(void)
6fbd55d0 284{
cc26b3b0
SMK		 285 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
286 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 287}
cc26b3b0
SMK		 288#endif
289
a8eb7ca0 290#ifdef CONFIG_ARCH_OMAP3
b6a4226c 291void __init omap3_map_io(void)
6fbd55d0 292{
cc26b3b0 293 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 294}
cc26b3b0 295#endif
120db2cb 296
33959553 297#ifdef CONFIG_SOC_TI81XX
b6a4226c 298void __init ti81xx_map_io(void)
01001712 299{
a920360f 300 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 301}
302#endif
303
bb6abcf4 304#ifdef CONFIG_SOC_AM33XX
b6a4226c 305void __init am33xx_map_io(void)
01001712 306{
1e6cb146 307 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 308}
309#endif
310
6fbd55d0 311#ifdef CONFIG_ARCH_OMAP4
b6a4226c 312void __init omap4_map_io(void)
6fbd55d0 313{
44169075 314 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e 315 omap_barriers_init();
120db2cb 316}
6fbd55d0 317#endif
120db2cb 318
05e152c7 319#ifdef CONFIG_SOC_OMAP5
b6a4226c 320void __init omap5_map_io(void)
05e152c7
S		 321{
322 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
323}
324#endif
2f135eaf
PW		 325/*
326 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
327 *
328 * Sets the CORE DPLL3 M2 divider to the same value that it's at
329 * currently. This has the effect of setting the SDRC SDRAM AC timing
330 * registers to the values currently defined by the kernel. Currently
331 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
332 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
333 * or passes along the return value of clk_set_rate().
334 */
335static int __init _omap2_init_reprogram_sdrc(void)
336{
337 struct clk *dpll3_m2_ck;
338 int v = -EINVAL;
339 long rate;
340
341 if (!cpu_is_omap34xx())
342 return 0;
343
344 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 345 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 346 return -EINVAL;
347
348 rate = clk_get_rate(dpll3_m2_ck);
349 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
350 v = clk_set_rate(dpll3_m2_ck, rate);
351 if (v)
352 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
353
354 clk_put(dpll3_m2_ck);
355
356 return v;
357}
358
2092e5cc
PW		 359static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
360{
361 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
362}
363
7b250aff 364static void __init omap_common_init_early(void)
120db2cb 365{
df80442d 366 omap_init_consistent_dma_size();
7b250aff 367}
2092e5cc 368
7b250aff
TL		 369static void __init omap_hwmod_init_postsetup(void)
370{
371 u8 postsetup_state;
2092e5cc
PW		 372
373 /* Set the default postsetup state for all hwmods */
374#ifdef CONFIG_PM_RUNTIME
375 postsetup_state = _HWMOD_STATE_IDLE;
376#else
377 postsetup_state = _HWMOD_STATE_ENABLED;
378#endif
379 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 380
53da4ce2 381 omap_pm_if_early_init();
4805734b
PW		 382}
383
16110798 384#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 385void __init omap2420_init_early(void)
386{
b6a4226c
PW		 387 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
388 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
389 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
390 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
391 NULL);
d9a16f9a
PW		 392 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
393 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
4de34f35 394 omap2xxx_check_revision();
c4ceedcb 395 omap2xxx_cm_init();
7b250aff
TL		 396 omap_common_init_early();
397 omap2xxx_voltagedomains_init();
398 omap242x_powerdomains_init();
399 omap242x_clockdomains_init();
400 omap2420_hwmod_init();
401 omap_hwmod_init_postsetup();
402 omap2420_clk_init();
8f5b5a41 403}
bbd707ac
SG		 404
405void __init omap2420_init_late(void)
406{
407 omap_mux_late_init();
408 omap2_common_pm_late_init();
409 omap2_pm_init();
410}
16110798 411#endif
8f5b5a41 412
16110798 413#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 414void __init omap2430_init_early(void)
415{
b6a4226c
PW		 416 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
417 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
418 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
419 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
420 NULL);
d9a16f9a
PW		 421 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
422 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
4de34f35 423 omap2xxx_check_revision();
c4ceedcb 424 omap2xxx_cm_init();
7b250aff
TL		 425 omap_common_init_early();
426 omap2xxx_voltagedomains_init();
427 omap243x_powerdomains_init();
428 omap243x_clockdomains_init();
429 omap2430_hwmod_init();
430 omap_hwmod_init_postsetup();
431 omap2430_clk_init();
432}
bbd707ac
SG		 433
434void __init omap2430_init_late(void)
435{
436 omap_mux_late_init();
437 omap2_common_pm_late_init();
438 omap2_pm_init();
439}
c4e2d245 440#endif
7b250aff
TL		 441
442/*
443 * Currently only board-omap3beagle.c should call this because of the
444 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
445 */
c4e2d245 446#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 447void __init omap3_init_early(void)
448{
b6a4226c
PW		 449 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
450 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
451 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
452 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
453 NULL);
d9a16f9a
PW		 454 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
455 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
4de34f35
VH		 456 omap3xxx_check_revision();
457 omap3xxx_check_features();
c4ceedcb 458 omap3xxx_cm_init();
7b250aff
TL		 459 omap_common_init_early();
460 omap3xxx_voltagedomains_init();
461 omap3xxx_powerdomains_init();
462 omap3xxx_clockdomains_init();
463 omap3xxx_hwmod_init();
464 omap_hwmod_init_postsetup();
465 omap3xxx_clk_init();
8f5b5a41
TL		 466}
467
468void __init omap3430_init_early(void)
469{
7b250aff 470 omap3_init_early();
8f5b5a41
TL		 471}
472
473void __init omap35xx_init_early(void)
474{
7b250aff 475 omap3_init_early();
8f5b5a41
TL		 476}
477
478void __init omap3630_init_early(void)
479{
7b250aff 480 omap3_init_early();
8f5b5a41
TL		 481}
482
483void __init am35xx_init_early(void)
484{
7b250aff 485 omap3_init_early();
8f5b5a41
TL		 486}
487
a920360f 488void __init ti81xx_init_early(void)
8f5b5a41 489{
b6a4226c
PW		 490 omap2_set_globals_tap(OMAP343X_CLASS,
491 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
492 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
493 NULL);
d9a16f9a
PW		 494 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
495 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
4de34f35
VH		 496 omap3xxx_check_revision();
497 ti81xx_check_features();
4c3cf901
TL		 498 omap_common_init_early();
499 omap3xxx_voltagedomains_init();
500 omap3xxx_powerdomains_init();
501 omap3xxx_clockdomains_init();
502 omap3xxx_hwmod_init();
503 omap_hwmod_init_postsetup();
504 omap3xxx_clk_init();
8f5b5a41 505}
bbd707ac
SG		 506
507void __init omap3_init_late(void)
508{
509 omap_mux_late_init();
510 omap2_common_pm_late_init();
511 omap3_pm_init();
512}
513
514void __init omap3430_init_late(void)
515{
516 omap_mux_late_init();
517 omap2_common_pm_late_init();
518 omap3_pm_init();
519}
520
521void __init omap35xx_init_late(void)
522{
523 omap_mux_late_init();
524 omap2_common_pm_late_init();
525 omap3_pm_init();
526}
527
528void __init omap3630_init_late(void)
529{
530 omap_mux_late_init();
531 omap2_common_pm_late_init();
532 omap3_pm_init();
533}
534
535void __init am35xx_init_late(void)
536{
537 omap_mux_late_init();
538 omap2_common_pm_late_init();
539 omap3_pm_init();
540}
541
542void __init ti81xx_init_late(void)
543{
544 omap_mux_late_init();
545 omap2_common_pm_late_init();
546 omap3_pm_init();
547}
c4e2d245 548#endif
8f5b5a41 549
08f30989
AM		 550#ifdef CONFIG_SOC_AM33XX
551void __init am33xx_init_early(void)
552{
b6a4226c
PW		 553 omap2_set_globals_tap(AM335X_CLASS,
554 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
555 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
556 NULL);
d9a16f9a
PW		 557 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
558 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
08f30989
AM		 559 omap3xxx_check_revision();
560 ti81xx_check_features();
561 omap_common_init_early();
ce3fc89a 562 am33xx_voltagedomains_init();
3f0ea764 563 am33xx_powerdomains_init();
9c80f3aa 564 am33xx_clockdomains_init();
a2cfc509
VH		 565 am33xx_hwmod_init();
566 omap_hwmod_init_postsetup();
e30384ab 567 am33xx_clk_init();
08f30989
AM		 568}
569#endif
570
c4e2d245 571#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 572void __init omap4430_init_early(void)
573{
b6a4226c
PW		 574 omap2_set_globals_tap(OMAP443X_CLASS,
575 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
576 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
577 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
d9a16f9a
PW		 578 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
579 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
580 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
581 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
582 omap_prm_base_init();
583 omap_cm_base_init();
4de34f35
VH		 584 omap4xxx_check_revision();
585 omap4xxx_check_features();
7b250aff
TL		 586 omap_common_init_early();
587 omap44xx_voltagedomains_init();
588 omap44xx_powerdomains_init();
589 omap44xx_clockdomains_init();
590 omap44xx_hwmod_init();
591 omap_hwmod_init_postsetup();
592 omap4xxx_clk_init();
8f5b5a41 593}
bbd707ac
SG		 594
595void __init omap4430_init_late(void)
596{
597 omap_mux_late_init();
598 omap2_common_pm_late_init();
599 omap4_pm_init();
600}
c4e2d245 601#endif
8f5b5a41 602
05e152c7
S		 603#ifdef CONFIG_SOC_OMAP5
604void __init omap5_init_early(void)
605{
b6a4226c
PW		 606 omap2_set_globals_tap(OMAP54XX_CLASS,
607 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
608 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
609 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
d9a16f9a
PW		 610 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
611 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
612 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
613 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
614 omap_prm_base_init();
615 omap_cm_base_init();
05e152c7
S		 616 omap5xxx_check_revision();
617 omap_common_init_early();
618}
619#endif
620
a4ca9dbe 621void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 622 struct omap_sdrc_params *sdrc_cs1)
623{
a66cb345
TL		 624 omap_sram_init();
625
01001712 626 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 627 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
628 _omap2_init_reprogram_sdrc();
629 }
1dbae815 630}
Linux kernel - Deliverables
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