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Linux 3.17-rc1
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
45c3eb7d 28#include <linux/omap-dma.h>
ee0839c2 29
dc843280 30#include "omap_hwmod.h"
dbc04161 31#include "soc.h"
ee0839c2 32#include "iomap.h"
81a60482 33#include "voltage.h"
72e06d08 34#include "powerdomain.h"
1540f214 35#include "clockdomain.h"
4e65331c 36#include "common.h"
e30384ab 37#include "clock.h"
ee0839c2
TL		 38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "clock44xx.h"
1d5aef49 41#include "omap-pm.h"
3e6ece13 42#include "sdrc.h"
b6a4226c 43#include "control.h"
3d82cbbb 44#include "serial.h"
bf027ca1 45#include "sram.h"
c4ceedcb
PW		 46#include "cm2xxx.h"
47#include "cm3xxx.h"
d9a16f9a
PW		 48#include "prm.h"
49#include "cm.h"
50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h"
52#include "cminst44xx.h"
63a293e0
PW		 53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"
69a1e7a1 56#include "opp2xxx.h"
02bfc030 57
ff931c82 58/*
cfa9667d 59 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 60 * clock initializations
61 */
cfa9667d 62static int (*omap_clk_soc_init)(void);
ff931c82 63
1dbae815
TL		 64/*
65 * The machine specific code may provide the extra mapping besides the
66 * default mapping provided here.
67 */
cc26b3b0 68
e48f814e 69#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 70static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 71 {
72 .virtual = L3_24XX_VIRT,
73 .pfn = __phys_to_pfn(L3_24XX_PHYS),
74 .length = L3_24XX_SIZE,
75 .type = MT_DEVICE
76 },
09f21ed4 77 {
cc26b3b0
SMK		 78 .virtual = L4_24XX_VIRT,
79 .pfn = __phys_to_pfn(L4_24XX_PHYS),
80 .length = L4_24XX_SIZE,
81 .type = MT_DEVICE
09f21ed4 82 },
cc26b3b0
SMK		 83};
84
59b479e0 85#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 86static struct map_desc omap242x_io_desc[] __initdata = {
87 {
7adb9987
PW		 88 .virtual = DSP_MEM_2420_VIRT,
89 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
90 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 91 .type = MT_DEVICE
92 },
93 {
7adb9987
PW		 94 .virtual = DSP_IPI_2420_VIRT,
95 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
96 .length = DSP_IPI_2420_SIZE,
cc26b3b0 97 .type = MT_DEVICE
09f21ed4 98 },
cc26b3b0 99 {
7adb9987
PW		 100 .virtual = DSP_MMU_2420_VIRT,
101 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
102 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 103 .type = MT_DEVICE
104 },
105};
106
107#endif
108
59b479e0 109#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 110static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 111 {
112 .virtual = L4_WK_243X_VIRT,
113 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
114 .length = L4_WK_243X_SIZE,
115 .type = MT_DEVICE
116 },
117 {
118 .virtual = OMAP243X_GPMC_VIRT,
119 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
120 .length = OMAP243X_GPMC_SIZE,
121 .type = MT_DEVICE
122 },
cc26b3b0
SMK		 123 {
124 .virtual = OMAP243X_SDRC_VIRT,
125 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
126 .length = OMAP243X_SDRC_SIZE,
127 .type = MT_DEVICE
128 },
129 {
130 .virtual = OMAP243X_SMS_VIRT,
131 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
132 .length = OMAP243X_SMS_SIZE,
133 .type = MT_DEVICE
134 },
135};
72d0f1c3 136#endif
72d0f1c3 137#endif
cc26b3b0 138
a8eb7ca0 139#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 140static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 141 {
cc26b3b0
SMK		 142 .virtual = L3_34XX_VIRT,
143 .pfn = __phys_to_pfn(L3_34XX_PHYS),
144 .length = L3_34XX_SIZE,
c40fae95
TL		 145 .type = MT_DEVICE
146 },
147 {
cc26b3b0
SMK		 148 .virtual = L4_34XX_VIRT,
149 .pfn = __phys_to_pfn(L4_34XX_PHYS),
150 .length = L4_34XX_SIZE,
c40fae95
TL		 151 .type = MT_DEVICE
152 },
cc26b3b0
SMK		 153 {
154 .virtual = OMAP34XX_GPMC_VIRT,
155 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
156 .length = OMAP34XX_GPMC_SIZE,
1dbae815 157 .type = MT_DEVICE
cc26b3b0
SMK		 158 },
159 {
160 .virtual = OMAP343X_SMS_VIRT,
161 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
162 .length = OMAP343X_SMS_SIZE,
163 .type = MT_DEVICE
164 },
165 {
166 .virtual = OMAP343X_SDRC_VIRT,
167 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
168 .length = OMAP343X_SDRC_SIZE,
1dbae815 169 .type = MT_DEVICE
cc26b3b0
SMK		 170 },
171 {
172 .virtual = L4_PER_34XX_VIRT,
173 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
174 .length = L4_PER_34XX_SIZE,
175 .type = MT_DEVICE
176 },
177 {
178 .virtual = L4_EMU_34XX_VIRT,
179 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
180 .length = L4_EMU_34XX_SIZE,
181 .type = MT_DEVICE
182 },
1dbae815 183};
cc26b3b0 184#endif
01001712 185
33959553 186#ifdef CONFIG_SOC_TI81XX
a920360f 187static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 188 {
189 .virtual = L4_34XX_VIRT,
190 .pfn = __phys_to_pfn(L4_34XX_PHYS),
191 .length = L4_34XX_SIZE,
192 .type = MT_DEVICE
193 }
194};
195#endif
196
addb154a 197#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 198static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 199 {
200 .virtual = L4_34XX_VIRT,
201 .pfn = __phys_to_pfn(L4_34XX_PHYS),
202 .length = L4_34XX_SIZE,
203 .type = MT_DEVICE
204 },
1e6cb146
AM		 205 {
206 .virtual = L4_WK_AM33XX_VIRT,
207 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
208 .length = L4_WK_AM33XX_SIZE,
209 .type = MT_DEVICE
210 }
01001712
HP		 211};
212#endif
213
44169075
SS		 214#ifdef CONFIG_ARCH_OMAP4
215static struct map_desc omap44xx_io_desc[] __initdata = {
216 {
217 .virtual = L3_44XX_VIRT,
218 .pfn = __phys_to_pfn(L3_44XX_PHYS),
219 .length = L3_44XX_SIZE,
220 .type = MT_DEVICE,
221 },
222 {
223 .virtual = L4_44XX_VIRT,
224 .pfn = __phys_to_pfn(L4_44XX_PHYS),
225 .length = L4_44XX_SIZE,
226 .type = MT_DEVICE,
227 },
44169075
SS		 228 {
229 .virtual = L4_PER_44XX_VIRT,
230 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
231 .length = L4_PER_44XX_SIZE,
232 .type = MT_DEVICE,
233 },
137d105d
SS		 234#ifdef CONFIG_OMAP4_ERRATA_I688
235 {
236 .virtual = OMAP4_SRAM_VA,
237 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
238 .length = PAGE_SIZE,
2e2c9de2 239 .type = MT_MEMORY_RW_SO,
137d105d
SS		 240 },
241#endif
242
44169075
SS		 243};
244#endif
1dbae815 245
a3a9384a 246#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
05e152c7
S		 247static struct map_desc omap54xx_io_desc[] __initdata = {
248 {
249 .virtual = L3_54XX_VIRT,
250 .pfn = __phys_to_pfn(L3_54XX_PHYS),
251 .length = L3_54XX_SIZE,
252 .type = MT_DEVICE,
253 },
254 {
255 .virtual = L4_54XX_VIRT,
256 .pfn = __phys_to_pfn(L4_54XX_PHYS),
257 .length = L4_54XX_SIZE,
258 .type = MT_DEVICE,
259 },
260 {
261 .virtual = L4_WK_54XX_VIRT,
262 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
263 .length = L4_WK_54XX_SIZE,
264 .type = MT_DEVICE,
265 },
266 {
267 .virtual = L4_PER_54XX_VIRT,
268 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
269 .length = L4_PER_54XX_SIZE,
270 .type = MT_DEVICE,
271 },
1348bbf9
SS		 272#ifdef CONFIG_OMAP4_ERRATA_I688
273 {
274 .virtual = OMAP4_SRAM_VA,
275 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
276 .length = PAGE_SIZE,
2e2c9de2 277 .type = MT_MEMORY_RW_SO,
1348bbf9
SS		 278 },
279#endif
05e152c7
S		 280};
281#endif
282
59b479e0 283#ifdef CONFIG_SOC_OMAP2420
b6a4226c 284void __init omap242x_map_io(void)
1dbae815 285{
cc26b3b0
SMK		 286 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
287 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 288}
cc26b3b0
SMK		 289#endif
290
59b479e0 291#ifdef CONFIG_SOC_OMAP2430
b6a4226c 292void __init omap243x_map_io(void)
6fbd55d0 293{
cc26b3b0
SMK		 294 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
295 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 296}
cc26b3b0
SMK		 297#endif
298
a8eb7ca0 299#ifdef CONFIG_ARCH_OMAP3
b6a4226c 300void __init omap3_map_io(void)
6fbd55d0 301{
cc26b3b0 302 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 303}
cc26b3b0 304#endif
120db2cb 305
33959553 306#ifdef CONFIG_SOC_TI81XX
b6a4226c 307void __init ti81xx_map_io(void)
01001712 308{
a920360f 309 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 310}
311#endif
312
addb154a 313#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 314void __init am33xx_map_io(void)
01001712 315{
1e6cb146 316 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 317}
318#endif
319
6fbd55d0 320#ifdef CONFIG_ARCH_OMAP4
b6a4226c 321void __init omap4_map_io(void)
6fbd55d0 322{
44169075 323 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e 324 omap_barriers_init();
120db2cb 325}
6fbd55d0 326#endif
120db2cb 327
a3a9384a 328#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
b6a4226c 329void __init omap5_map_io(void)
05e152c7
S		 330{
331 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
1348bbf9 332 omap_barriers_init();
05e152c7
S		 333}
334#endif
2f135eaf
PW		 335/*
336 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
337 *
338 * Sets the CORE DPLL3 M2 divider to the same value that it's at
339 * currently. This has the effect of setting the SDRC SDRAM AC timing
340 * registers to the values currently defined by the kernel. Currently
341 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
342 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
343 * or passes along the return value of clk_set_rate().
344 */
345static int __init _omap2_init_reprogram_sdrc(void)
346{
347 struct clk *dpll3_m2_ck;
348 int v = -EINVAL;
349 long rate;
350
351 if (!cpu_is_omap34xx())
352 return 0;
353
354 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 355 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 356 return -EINVAL;
357
358 rate = clk_get_rate(dpll3_m2_ck);
359 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
360 v = clk_set_rate(dpll3_m2_ck, rate);
361 if (v)
362 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
363
364 clk_put(dpll3_m2_ck);
365
366 return v;
367}
368
2092e5cc
PW		 369static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
370{
371 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
372}
373
7b250aff
TL		 374static void __init omap_hwmod_init_postsetup(void)
375{
376 u8 postsetup_state;
2092e5cc
PW		 377
378 /* Set the default postsetup state for all hwmods */
379#ifdef CONFIG_PM_RUNTIME
380 postsetup_state = _HWMOD_STATE_IDLE;
381#else
382 postsetup_state = _HWMOD_STATE_ENABLED;
383#endif
384 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 385
53da4ce2 386 omap_pm_if_early_init();
4805734b
PW		 387}
388
069d0a78 389static void __init __maybe_unused omap_common_late_init(void)
4ed12be0
RB		 390{
391 omap_mux_late_init();
392 omap2_common_pm_late_init();
6770b211 393 omap_soc_device_init();
4ed12be0
RB		 394}
395
16110798 396#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 397void __init omap2420_init_early(void)
398{
b6a4226c
PW		 399 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
400 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
401 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
402 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
403 NULL);
d9a16f9a
PW		 404 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
405 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
4de34f35 406 omap2xxx_check_revision();
63a293e0 407 omap2xxx_prm_init();
c4ceedcb 408 omap2xxx_cm_init();
7b250aff
TL		 409 omap2xxx_voltagedomains_init();
410 omap242x_powerdomains_init();
411 omap242x_clockdomains_init();
412 omap2420_hwmod_init();
413 omap_hwmod_init_postsetup();
6a194a6e
TK		 414 omap_clk_soc_init = omap2420_dt_clk_init;
415 rate_table = omap2420_rate_table;
8f5b5a41 416}
bbd707ac
SG		 417
418void __init omap2420_init_late(void)
419{
4ed12be0 420 omap_common_late_init();
bbd707ac 421 omap2_pm_init();
23fb8ba3 422 omap2_clk_enable_autoidle_all();
bbd707ac 423}
16110798 424#endif
8f5b5a41 425
16110798 426#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 427void __init omap2430_init_early(void)
428{
b6a4226c
PW		 429 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
430 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
431 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
432 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
433 NULL);
d9a16f9a
PW		 434 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
435 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
4de34f35 436 omap2xxx_check_revision();
63a293e0 437 omap2xxx_prm_init();
c4ceedcb 438 omap2xxx_cm_init();
7b250aff
TL		 439 omap2xxx_voltagedomains_init();
440 omap243x_powerdomains_init();
441 omap243x_clockdomains_init();
442 omap2430_hwmod_init();
443 omap_hwmod_init_postsetup();
6a194a6e
TK		 444 omap_clk_soc_init = omap2430_dt_clk_init;
445 rate_table = omap2430_rate_table;
7b250aff 446}
bbd707ac
SG		 447
448void __init omap2430_init_late(void)
449{
4ed12be0 450 omap_common_late_init();
bbd707ac 451 omap2_pm_init();
23fb8ba3 452 omap2_clk_enable_autoidle_all();
bbd707ac 453}
c4e2d245 454#endif
7b250aff
TL		 455
456/*
457 * Currently only board-omap3beagle.c should call this because of the
458 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
459 */
c4e2d245 460#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 461void __init omap3_init_early(void)
462{
b6a4226c
PW		 463 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
464 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
465 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
466 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
467 NULL);
d9a16f9a
PW		 468 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
469 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
4de34f35
VH		 470 omap3xxx_check_revision();
471 omap3xxx_check_features();
63a293e0 472 omap3xxx_prm_init();
c4ceedcb 473 omap3xxx_cm_init();
7b250aff
TL		 474 omap3xxx_voltagedomains_init();
475 omap3xxx_powerdomains_init();
476 omap3xxx_clockdomains_init();
477 omap3xxx_hwmod_init();
478 omap_hwmod_init_postsetup();
cfa9667d 479 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41
TL		 480}
481
482void __init omap3430_init_early(void)
483{
7b250aff 484 omap3_init_early();
3e049157
TK		 485 if (of_have_populated_dt())
486 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 487}
488
489void __init omap35xx_init_early(void)
490{
7b250aff 491 omap3_init_early();
3e049157
TK		 492 if (of_have_populated_dt())
493 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 494}
495
496void __init omap3630_init_early(void)
497{
7b250aff 498 omap3_init_early();
3e049157
TK		 499 if (of_have_populated_dt())
500 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 501}
502
503void __init am35xx_init_early(void)
504{
7b250aff 505 omap3_init_early();
3e049157
TK		 506 if (of_have_populated_dt())
507 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 508}
509
a920360f 510void __init ti81xx_init_early(void)
8f5b5a41 511{
b6a4226c
PW		 512 omap2_set_globals_tap(OMAP343X_CLASS,
513 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
514 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
515 NULL);
d9a16f9a
PW		 516 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
517 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
4de34f35
VH		 518 omap3xxx_check_revision();
519 ti81xx_check_features();
4c3cf901
TL		 520 omap3xxx_voltagedomains_init();
521 omap3xxx_powerdomains_init();
522 omap3xxx_clockdomains_init();
523 omap3xxx_hwmod_init();
524 omap_hwmod_init_postsetup();
3e049157
TK		 525 if (of_have_populated_dt())
526 omap_clk_soc_init = ti81xx_dt_clk_init;
527 else
528 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41 529}
bbd707ac
SG		 530
531void __init omap3_init_late(void)
532{
4ed12be0 533 omap_common_late_init();
bbd707ac 534 omap3_pm_init();
23fb8ba3 535 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 536}
537
538void __init omap3430_init_late(void)
539{
4ed12be0 540 omap_common_late_init();
bbd707ac 541 omap3_pm_init();
23fb8ba3 542 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 543}
544
545void __init omap35xx_init_late(void)
546{
4ed12be0 547 omap_common_late_init();
bbd707ac 548 omap3_pm_init();
23fb8ba3 549 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 550}
551
552void __init omap3630_init_late(void)
553{
4ed12be0 554 omap_common_late_init();
bbd707ac 555 omap3_pm_init();
23fb8ba3 556 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 557}
558
559void __init am35xx_init_late(void)
560{
4ed12be0 561 omap_common_late_init();
bbd707ac 562 omap3_pm_init();
23fb8ba3 563 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 564}
565
566void __init ti81xx_init_late(void)
567{
4ed12be0 568 omap_common_late_init();
bbd707ac 569 omap3_pm_init();
23fb8ba3 570 omap2_clk_enable_autoidle_all();
bbd707ac 571}
c4e2d245 572#endif
8f5b5a41 573
08f30989
AM		 574#ifdef CONFIG_SOC_AM33XX
575void __init am33xx_init_early(void)
576{
b6a4226c
PW		 577 omap2_set_globals_tap(AM335X_CLASS,
578 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
579 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
580 NULL);
d9a16f9a
PW		 581 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
582 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
08f30989 583 omap3xxx_check_revision();
7bcad170 584 am33xx_check_features();
3f0ea764 585 am33xx_powerdomains_init();
9c80f3aa 586 am33xx_clockdomains_init();
a2cfc509
VH		 587 am33xx_hwmod_init();
588 omap_hwmod_init_postsetup();
149c09d3 589 omap_clk_soc_init = am33xx_dt_clk_init;
08f30989 590}
765e7a06
NM		 591
592void __init am33xx_init_late(void)
593{
594 omap_common_late_init();
595}
08f30989
AM		 596#endif
597
c5107027
AM		 598#ifdef CONFIG_SOC_AM43XX
599void __init am43xx_init_early(void)
600{
601 omap2_set_globals_tap(AM335X_CLASS,
602 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
603 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
604 NULL);
605 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
606 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
8835cf6e
A		 607 omap_prm_base_init();
608 omap_cm_base_init();
c5107027 609 omap3xxx_check_revision();
7a2e0513 610 am33xx_check_features();
8835cf6e
A		 611 am43xx_powerdomains_init();
612 am43xx_clockdomains_init();
613 am43xx_hwmod_init();
614 omap_hwmod_init_postsetup();
d941f86f 615 omap_l2_cache_init();
d22031e2 616 omap_clk_soc_init = am43xx_dt_clk_init;
c5107027 617}
765e7a06
NM		 618
619void __init am43xx_init_late(void)
620{
621 omap_common_late_init();
622}
c5107027
AM		 623#endif
624
c4e2d245 625#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 626void __init omap4430_init_early(void)
627{
b6a4226c
PW		 628 omap2_set_globals_tap(OMAP443X_CLASS,
629 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
630 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
631 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
d9a16f9a
PW		 632 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
633 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
634 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
635 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
636 omap_prm_base_init();
637 omap_cm_base_init();
4de34f35
VH		 638 omap4xxx_check_revision();
639 omap4xxx_check_features();
de70af49 640 omap4_pm_init_early();
63a293e0 641 omap44xx_prm_init();
7b250aff
TL		 642 omap44xx_voltagedomains_init();
643 omap44xx_powerdomains_init();
644 omap44xx_clockdomains_init();
645 omap44xx_hwmod_init();
646 omap_hwmod_init_postsetup();
b39b14e6 647 omap_l2_cache_init();
c8c88d85 648 omap_clk_soc_init = omap4xxx_dt_clk_init;
8f5b5a41 649}
bbd707ac
SG		 650
651void __init omap4430_init_late(void)
652{
4ed12be0 653 omap_common_late_init();
bbd707ac 654 omap4_pm_init();
23fb8ba3 655 omap2_clk_enable_autoidle_all();
bbd707ac 656}
c4e2d245 657#endif
8f5b5a41 658
05e152c7
S		 659#ifdef CONFIG_SOC_OMAP5
660void __init omap5_init_early(void)
661{
b6a4226c
PW		 662 omap2_set_globals_tap(OMAP54XX_CLASS,
663 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
664 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
665 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
d9a16f9a
PW		 666 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
667 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
668 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
669 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
670 omap_prm_base_init();
671 omap_cm_base_init();
e4020aa9 672 omap44xx_prm_init();
05e152c7 673 omap5xxx_check_revision();
e4020aa9
SS		 674 omap54xx_voltagedomains_init();
675 omap54xx_powerdomains_init();
676 omap54xx_clockdomains_init();
677 omap54xx_hwmod_init();
678 omap_hwmod_init_postsetup();
cfa9667d 679 omap_clk_soc_init = omap5xxx_dt_clk_init;
05e152c7 680}
765e7a06
NM		 681
682void __init omap5_init_late(void)
683{
684 omap_common_late_init();
685}
05e152c7
S		 686#endif
687
a3a9384a
S		 688#ifdef CONFIG_SOC_DRA7XX
689void __init dra7xx_init_early(void)
690{
691 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
692 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
693 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
694 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
695 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
696 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
697 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
698 omap_prm_base_init();
699 omap_cm_base_init();
7de516a6 700 omap44xx_prm_init();
733d20ee 701 dra7xxx_check_revision();
7de516a6
A		 702 dra7xx_powerdomains_init();
703 dra7xx_clockdomains_init();
704 dra7xx_hwmod_init();
705 omap_hwmod_init_postsetup();
f1cf498e 706 omap_clk_soc_init = dra7xx_dt_clk_init;
a3a9384a 707}
765e7a06
NM		 708
709void __init dra7xx_init_late(void)
710{
711 omap_common_late_init();
712}
a3a9384a
S		 713#endif
714
715
a4ca9dbe 716void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 717 struct omap_sdrc_params *sdrc_cs1)
718{
a66cb345
TL		 719 omap_sram_init();
720
01001712 721 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 722 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
723 _omap2_init_reprogram_sdrc();
724 }
1dbae815 725}
cfa9667d
TK		 726
727int __init omap_clk_init(void)
728{
729 int ret = 0;
730
731 if (!omap_clk_soc_init)
732 return 0;
733
8111e010
TK		 734 ti_clk_init_features();
735
cfa9667d
TK		 736 ret = of_prcm_init();
737 if (!ret)
738 ret = omap_clk_soc_init();
739
740 return ret;
741}
Linux kernel - Deliverables
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