Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
45c3eb7d | 28 | #include <linux/omap-dma.h> |
ee0839c2 | 29 | |
dc843280 | 30 | #include "omap_hwmod.h" |
dbc04161 | 31 | #include "soc.h" |
ee0839c2 | 32 | #include "iomap.h" |
81a60482 | 33 | #include "voltage.h" |
72e06d08 | 34 | #include "powerdomain.h" |
1540f214 | 35 | #include "clockdomain.h" |
4e65331c | 36 | #include "common.h" |
e30384ab | 37 | #include "clock.h" |
ee0839c2 TL |
38 | #include "clock2xxx.h" |
39 | #include "clock3xxx.h" | |
40 | #include "clock44xx.h" | |
1d5aef49 | 41 | #include "omap-pm.h" |
3e6ece13 | 42 | #include "sdrc.h" |
b6a4226c | 43 | #include "control.h" |
3d82cbbb | 44 | #include "serial.h" |
bf027ca1 | 45 | #include "sram.h" |
c4ceedcb PW |
46 | #include "cm2xxx.h" |
47 | #include "cm3xxx.h" | |
7632a02f | 48 | #include "cm33xx.h" |
ab6c9bbf | 49 | #include "cm44xx.h" |
d9a16f9a PW |
50 | #include "prm.h" |
51 | #include "cm.h" | |
52 | #include "prcm_mpu44xx.h" | |
53 | #include "prminst44xx.h" | |
63a293e0 PW |
54 | #include "prm2xxx.h" |
55 | #include "prm3xxx.h" | |
d9bbe84f | 56 | #include "prm33xx.h" |
63a293e0 | 57 | #include "prm44xx.h" |
69a1e7a1 | 58 | #include "opp2xxx.h" |
02bfc030 | 59 | |
ff931c82 | 60 | /* |
cfa9667d | 61 | * omap_clk_soc_init: points to a function that does the SoC-specific |
ff931c82 RN |
62 | * clock initializations |
63 | */ | |
cfa9667d | 64 | static int (*omap_clk_soc_init)(void); |
ff931c82 | 65 | |
1dbae815 TL |
66 | /* |
67 | * The machine specific code may provide the extra mapping besides the | |
68 | * default mapping provided here. | |
69 | */ | |
cc26b3b0 | 70 | |
e48f814e | 71 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 72 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
73 | { |
74 | .virtual = L3_24XX_VIRT, | |
75 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
76 | .length = L3_24XX_SIZE, | |
77 | .type = MT_DEVICE | |
78 | }, | |
09f21ed4 | 79 | { |
cc26b3b0 SMK |
80 | .virtual = L4_24XX_VIRT, |
81 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
82 | .length = L4_24XX_SIZE, | |
83 | .type = MT_DEVICE | |
09f21ed4 | 84 | }, |
cc26b3b0 SMK |
85 | }; |
86 | ||
59b479e0 | 87 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
88 | static struct map_desc omap242x_io_desc[] __initdata = { |
89 | { | |
7adb9987 PW |
90 | .virtual = DSP_MEM_2420_VIRT, |
91 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
92 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
93 | .type = MT_DEVICE |
94 | }, | |
95 | { | |
7adb9987 PW |
96 | .virtual = DSP_IPI_2420_VIRT, |
97 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
98 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 99 | .type = MT_DEVICE |
09f21ed4 | 100 | }, |
cc26b3b0 | 101 | { |
7adb9987 PW |
102 | .virtual = DSP_MMU_2420_VIRT, |
103 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
104 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
105 | .type = MT_DEVICE |
106 | }, | |
107 | }; | |
108 | ||
109 | #endif | |
110 | ||
59b479e0 | 111 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 112 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
113 | { |
114 | .virtual = L4_WK_243X_VIRT, | |
115 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
116 | .length = L4_WK_243X_SIZE, | |
117 | .type = MT_DEVICE | |
118 | }, | |
119 | { | |
120 | .virtual = OMAP243X_GPMC_VIRT, | |
121 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
122 | .length = OMAP243X_GPMC_SIZE, | |
123 | .type = MT_DEVICE | |
124 | }, | |
cc26b3b0 SMK |
125 | { |
126 | .virtual = OMAP243X_SDRC_VIRT, | |
127 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
128 | .length = OMAP243X_SDRC_SIZE, | |
129 | .type = MT_DEVICE | |
130 | }, | |
131 | { | |
132 | .virtual = OMAP243X_SMS_VIRT, | |
133 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
134 | .length = OMAP243X_SMS_SIZE, | |
135 | .type = MT_DEVICE | |
136 | }, | |
137 | }; | |
72d0f1c3 | 138 | #endif |
72d0f1c3 | 139 | #endif |
cc26b3b0 | 140 | |
a8eb7ca0 | 141 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 142 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 143 | { |
cc26b3b0 SMK |
144 | .virtual = L3_34XX_VIRT, |
145 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
146 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
147 | .type = MT_DEVICE |
148 | }, | |
149 | { | |
cc26b3b0 SMK |
150 | .virtual = L4_34XX_VIRT, |
151 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
152 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
153 | .type = MT_DEVICE |
154 | }, | |
cc26b3b0 SMK |
155 | { |
156 | .virtual = OMAP34XX_GPMC_VIRT, | |
157 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
158 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 159 | .type = MT_DEVICE |
cc26b3b0 SMK |
160 | }, |
161 | { | |
162 | .virtual = OMAP343X_SMS_VIRT, | |
163 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
164 | .length = OMAP343X_SMS_SIZE, | |
165 | .type = MT_DEVICE | |
166 | }, | |
167 | { | |
168 | .virtual = OMAP343X_SDRC_VIRT, | |
169 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
170 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 171 | .type = MT_DEVICE |
cc26b3b0 SMK |
172 | }, |
173 | { | |
174 | .virtual = L4_PER_34XX_VIRT, | |
175 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
176 | .length = L4_PER_34XX_SIZE, | |
177 | .type = MT_DEVICE | |
178 | }, | |
179 | { | |
180 | .virtual = L4_EMU_34XX_VIRT, | |
181 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
182 | .length = L4_EMU_34XX_SIZE, | |
183 | .type = MT_DEVICE | |
184 | }, | |
1dbae815 | 185 | }; |
cc26b3b0 | 186 | #endif |
01001712 | 187 | |
33959553 | 188 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 189 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
190 | { |
191 | .virtual = L4_34XX_VIRT, | |
192 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
193 | .length = L4_34XX_SIZE, | |
194 | .type = MT_DEVICE | |
195 | } | |
196 | }; | |
197 | #endif | |
198 | ||
addb154a | 199 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
1e6cb146 | 200 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
201 | { |
202 | .virtual = L4_34XX_VIRT, | |
203 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
204 | .length = L4_34XX_SIZE, | |
205 | .type = MT_DEVICE | |
206 | }, | |
1e6cb146 AM |
207 | { |
208 | .virtual = L4_WK_AM33XX_VIRT, | |
209 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
210 | .length = L4_WK_AM33XX_SIZE, | |
211 | .type = MT_DEVICE | |
212 | } | |
01001712 HP |
213 | }; |
214 | #endif | |
215 | ||
44169075 SS |
216 | #ifdef CONFIG_ARCH_OMAP4 |
217 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
218 | { | |
219 | .virtual = L3_44XX_VIRT, | |
220 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
221 | .length = L3_44XX_SIZE, | |
222 | .type = MT_DEVICE, | |
223 | }, | |
224 | { | |
225 | .virtual = L4_44XX_VIRT, | |
226 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
227 | .length = L4_44XX_SIZE, | |
228 | .type = MT_DEVICE, | |
229 | }, | |
44169075 SS |
230 | { |
231 | .virtual = L4_PER_44XX_VIRT, | |
232 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
233 | .length = L4_PER_44XX_SIZE, | |
234 | .type = MT_DEVICE, | |
235 | }, | |
44169075 SS |
236 | }; |
237 | #endif | |
1dbae815 | 238 | |
a3a9384a | 239 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
05e152c7 S |
240 | static struct map_desc omap54xx_io_desc[] __initdata = { |
241 | { | |
242 | .virtual = L3_54XX_VIRT, | |
243 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
244 | .length = L3_54XX_SIZE, | |
245 | .type = MT_DEVICE, | |
246 | }, | |
247 | { | |
248 | .virtual = L4_54XX_VIRT, | |
249 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
250 | .length = L4_54XX_SIZE, | |
251 | .type = MT_DEVICE, | |
252 | }, | |
253 | { | |
254 | .virtual = L4_WK_54XX_VIRT, | |
255 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
256 | .length = L4_WK_54XX_SIZE, | |
257 | .type = MT_DEVICE, | |
258 | }, | |
259 | { | |
260 | .virtual = L4_PER_54XX_VIRT, | |
261 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
262 | .length = L4_PER_54XX_SIZE, | |
263 | .type = MT_DEVICE, | |
264 | }, | |
265 | }; | |
266 | #endif | |
267 | ||
59b479e0 | 268 | #ifdef CONFIG_SOC_OMAP2420 |
b6a4226c | 269 | void __init omap242x_map_io(void) |
1dbae815 | 270 | { |
cc26b3b0 SMK |
271 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
272 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 273 | } |
cc26b3b0 SMK |
274 | #endif |
275 | ||
59b479e0 | 276 | #ifdef CONFIG_SOC_OMAP2430 |
b6a4226c | 277 | void __init omap243x_map_io(void) |
6fbd55d0 | 278 | { |
cc26b3b0 SMK |
279 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
280 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 281 | } |
cc26b3b0 SMK |
282 | #endif |
283 | ||
a8eb7ca0 | 284 | #ifdef CONFIG_ARCH_OMAP3 |
b6a4226c | 285 | void __init omap3_map_io(void) |
6fbd55d0 | 286 | { |
cc26b3b0 | 287 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 288 | } |
cc26b3b0 | 289 | #endif |
120db2cb | 290 | |
33959553 | 291 | #ifdef CONFIG_SOC_TI81XX |
b6a4226c | 292 | void __init ti81xx_map_io(void) |
01001712 | 293 | { |
a920360f | 294 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
295 | } |
296 | #endif | |
297 | ||
addb154a | 298 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
b6a4226c | 299 | void __init am33xx_map_io(void) |
01001712 | 300 | { |
1e6cb146 | 301 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
302 | } |
303 | #endif | |
304 | ||
6fbd55d0 | 305 | #ifdef CONFIG_ARCH_OMAP4 |
b6a4226c | 306 | void __init omap4_map_io(void) |
6fbd55d0 | 307 | { |
44169075 | 308 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
120db2cb | 309 | } |
6fbd55d0 | 310 | #endif |
120db2cb | 311 | |
a3a9384a | 312 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
b6a4226c | 313 | void __init omap5_map_io(void) |
05e152c7 S |
314 | { |
315 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
316 | } | |
317 | #endif | |
2f135eaf PW |
318 | /* |
319 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
320 | * | |
321 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
322 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
323 | * registers to the values currently defined by the kernel. Currently | |
324 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
325 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
326 | * or passes along the return value of clk_set_rate(). | |
327 | */ | |
328 | static int __init _omap2_init_reprogram_sdrc(void) | |
329 | { | |
330 | struct clk *dpll3_m2_ck; | |
331 | int v = -EINVAL; | |
332 | long rate; | |
333 | ||
334 | if (!cpu_is_omap34xx()) | |
335 | return 0; | |
336 | ||
337 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 338 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
339 | return -EINVAL; |
340 | ||
341 | rate = clk_get_rate(dpll3_m2_ck); | |
342 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
343 | v = clk_set_rate(dpll3_m2_ck, rate); | |
344 | if (v) | |
345 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
346 | ||
347 | clk_put(dpll3_m2_ck); | |
348 | ||
349 | return v; | |
350 | } | |
351 | ||
2092e5cc PW |
352 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
353 | { | |
354 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
355 | } | |
356 | ||
7b250aff TL |
357 | static void __init omap_hwmod_init_postsetup(void) |
358 | { | |
359 | u8 postsetup_state; | |
2092e5cc PW |
360 | |
361 | /* Set the default postsetup state for all hwmods */ | |
bf7c5449 | 362 | #ifdef CONFIG_PM |
2092e5cc PW |
363 | postsetup_state = _HWMOD_STATE_IDLE; |
364 | #else | |
365 | postsetup_state = _HWMOD_STATE_ENABLED; | |
366 | #endif | |
367 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 368 | |
53da4ce2 | 369 | omap_pm_if_early_init(); |
4805734b PW |
370 | } |
371 | ||
069d0a78 | 372 | static void __init __maybe_unused omap_common_late_init(void) |
4ed12be0 RB |
373 | { |
374 | omap_mux_late_init(); | |
375 | omap2_common_pm_late_init(); | |
6770b211 | 376 | omap_soc_device_init(); |
4ed12be0 RB |
377 | } |
378 | ||
16110798 | 379 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
380 | void __init omap2420_init_early(void) |
381 | { | |
b6a4226c PW |
382 | omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); |
383 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | |
384 | OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); | |
2208bf11 | 385 | omap2_control_base_init(); |
4de34f35 | 386 | omap2xxx_check_revision(); |
ab7b2ffc | 387 | omap2_prcm_base_init(); |
7b250aff TL |
388 | omap2xxx_voltagedomains_init(); |
389 | omap242x_powerdomains_init(); | |
390 | omap242x_clockdomains_init(); | |
391 | omap2420_hwmod_init(); | |
392 | omap_hwmod_init_postsetup(); | |
6a194a6e TK |
393 | omap_clk_soc_init = omap2420_dt_clk_init; |
394 | rate_table = omap2420_rate_table; | |
8f5b5a41 | 395 | } |
bbd707ac SG |
396 | |
397 | void __init omap2420_init_late(void) | |
398 | { | |
4ed12be0 | 399 | omap_common_late_init(); |
bbd707ac | 400 | omap2_pm_init(); |
23fb8ba3 | 401 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 402 | } |
16110798 | 403 | #endif |
8f5b5a41 | 404 | |
16110798 | 405 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
406 | void __init omap2430_init_early(void) |
407 | { | |
b6a4226c PW |
408 | omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); |
409 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | |
410 | OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); | |
2208bf11 | 411 | omap2_control_base_init(); |
4de34f35 | 412 | omap2xxx_check_revision(); |
ab7b2ffc | 413 | omap2_prcm_base_init(); |
7b250aff TL |
414 | omap2xxx_voltagedomains_init(); |
415 | omap243x_powerdomains_init(); | |
416 | omap243x_clockdomains_init(); | |
417 | omap2430_hwmod_init(); | |
418 | omap_hwmod_init_postsetup(); | |
6a194a6e TK |
419 | omap_clk_soc_init = omap2430_dt_clk_init; |
420 | rate_table = omap2430_rate_table; | |
7b250aff | 421 | } |
bbd707ac SG |
422 | |
423 | void __init omap2430_init_late(void) | |
424 | { | |
4ed12be0 | 425 | omap_common_late_init(); |
bbd707ac | 426 | omap2_pm_init(); |
23fb8ba3 | 427 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 428 | } |
c4e2d245 | 429 | #endif |
7b250aff TL |
430 | |
431 | /* | |
432 | * Currently only board-omap3beagle.c should call this because of the | |
433 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
434 | */ | |
c4e2d245 | 435 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
436 | void __init omap3_init_early(void) |
437 | { | |
b6a4226c PW |
438 | omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); |
439 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | |
440 | OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); | |
2208bf11 TK |
441 | /* XXX: remove these once OMAP3 is DT only */ |
442 | if (!of_have_populated_dt()) { | |
443 | omap2_set_globals_control( | |
efde2346 | 444 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE)); |
2208bf11 TK |
445 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); |
446 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), | |
447 | NULL); | |
448 | } | |
449 | omap2_control_base_init(); | |
4de34f35 VH |
450 | omap3xxx_check_revision(); |
451 | omap3xxx_check_features(); | |
ab7b2ffc | 452 | omap2_prcm_base_init(); |
425dc8b2 TK |
453 | /* XXX: remove these once OMAP3 is DT only */ |
454 | if (!of_have_populated_dt()) { | |
455 | omap3xxx_prm_init(NULL); | |
456 | omap3xxx_cm_init(NULL); | |
457 | } | |
7b250aff TL |
458 | omap3xxx_voltagedomains_init(); |
459 | omap3xxx_powerdomains_init(); | |
460 | omap3xxx_clockdomains_init(); | |
461 | omap3xxx_hwmod_init(); | |
462 | omap_hwmod_init_postsetup(); | |
eded36fe | 463 | if (!of_have_populated_dt()) { |
2208bf11 | 464 | omap3_control_legacy_iomap_init(); |
eded36fe TK |
465 | if (soc_is_am35xx()) |
466 | omap_clk_soc_init = am35xx_clk_legacy_init; | |
467 | else if (cpu_is_omap3630()) | |
468 | omap_clk_soc_init = omap36xx_clk_legacy_init; | |
469 | else if (omap_rev() == OMAP3430_REV_ES1_0) | |
470 | omap_clk_soc_init = omap3430es1_clk_legacy_init; | |
471 | else | |
472 | omap_clk_soc_init = omap3430_clk_legacy_init; | |
473 | } | |
8f5b5a41 TL |
474 | } |
475 | ||
476 | void __init omap3430_init_early(void) | |
477 | { | |
7b250aff | 478 | omap3_init_early(); |
3e049157 TK |
479 | if (of_have_populated_dt()) |
480 | omap_clk_soc_init = omap3430_dt_clk_init; | |
8f5b5a41 TL |
481 | } |
482 | ||
483 | void __init omap35xx_init_early(void) | |
484 | { | |
7b250aff | 485 | omap3_init_early(); |
3e049157 TK |
486 | if (of_have_populated_dt()) |
487 | omap_clk_soc_init = omap3430_dt_clk_init; | |
8f5b5a41 TL |
488 | } |
489 | ||
490 | void __init omap3630_init_early(void) | |
491 | { | |
7b250aff | 492 | omap3_init_early(); |
3e049157 TK |
493 | if (of_have_populated_dt()) |
494 | omap_clk_soc_init = omap3630_dt_clk_init; | |
8f5b5a41 TL |
495 | } |
496 | ||
497 | void __init am35xx_init_early(void) | |
498 | { | |
7b250aff | 499 | omap3_init_early(); |
3e049157 TK |
500 | if (of_have_populated_dt()) |
501 | omap_clk_soc_init = am35xx_dt_clk_init; | |
8f5b5a41 TL |
502 | } |
503 | ||
bbd707ac SG |
504 | void __init omap3_init_late(void) |
505 | { | |
4ed12be0 | 506 | omap_common_late_init(); |
bbd707ac | 507 | omap3_pm_init(); |
23fb8ba3 | 508 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
509 | } |
510 | ||
511 | void __init omap3430_init_late(void) | |
512 | { | |
4ed12be0 | 513 | omap_common_late_init(); |
bbd707ac | 514 | omap3_pm_init(); |
23fb8ba3 | 515 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
516 | } |
517 | ||
518 | void __init omap35xx_init_late(void) | |
519 | { | |
4ed12be0 | 520 | omap_common_late_init(); |
bbd707ac | 521 | omap3_pm_init(); |
23fb8ba3 | 522 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
523 | } |
524 | ||
525 | void __init omap3630_init_late(void) | |
526 | { | |
4ed12be0 | 527 | omap_common_late_init(); |
bbd707ac | 528 | omap3_pm_init(); |
23fb8ba3 | 529 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
530 | } |
531 | ||
532 | void __init am35xx_init_late(void) | |
533 | { | |
4ed12be0 | 534 | omap_common_late_init(); |
bbd707ac | 535 | omap3_pm_init(); |
23fb8ba3 | 536 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
537 | } |
538 | ||
539 | void __init ti81xx_init_late(void) | |
540 | { | |
4ed12be0 | 541 | omap_common_late_init(); |
23fb8ba3 | 542 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 543 | } |
c4e2d245 | 544 | #endif |
8f5b5a41 | 545 | |
a64459c4 AM |
546 | #ifdef CONFIG_SOC_TI81XX |
547 | void __init ti814x_init_early(void) | |
548 | { | |
549 | omap2_set_globals_tap(TI814X_CLASS, | |
550 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
2208bf11 | 551 | omap2_control_base_init(); |
a64459c4 AM |
552 | omap3xxx_check_revision(); |
553 | ti81xx_check_features(); | |
ab7b2ffc | 554 | omap2_prcm_base_init(); |
a64459c4 AM |
555 | omap3xxx_voltagedomains_init(); |
556 | omap3xxx_powerdomains_init(); | |
185fde6d | 557 | ti814x_clockdomains_init(); |
4d38bd12 | 558 | ti81xx_hwmod_init(); |
a64459c4 AM |
559 | omap_hwmod_init_postsetup(); |
560 | if (of_have_populated_dt()) | |
9cf705de | 561 | omap_clk_soc_init = dm814x_dt_clk_init; |
a64459c4 AM |
562 | } |
563 | ||
564 | void __init ti816x_init_early(void) | |
565 | { | |
566 | omap2_set_globals_tap(TI816X_CLASS, | |
567 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
2208bf11 | 568 | omap2_control_base_init(); |
a64459c4 AM |
569 | omap3xxx_check_revision(); |
570 | ti81xx_check_features(); | |
ab7b2ffc | 571 | omap2_prcm_base_init(); |
a64459c4 AM |
572 | omap3xxx_voltagedomains_init(); |
573 | omap3xxx_powerdomains_init(); | |
185fde6d | 574 | ti816x_clockdomains_init(); |
4d38bd12 | 575 | ti81xx_hwmod_init(); |
a64459c4 AM |
576 | omap_hwmod_init_postsetup(); |
577 | if (of_have_populated_dt()) | |
9cf705de | 578 | omap_clk_soc_init = dm816x_dt_clk_init; |
a64459c4 AM |
579 | } |
580 | #endif | |
581 | ||
08f30989 AM |
582 | #ifdef CONFIG_SOC_AM33XX |
583 | void __init am33xx_init_early(void) | |
584 | { | |
b6a4226c PW |
585 | omap2_set_globals_tap(AM335X_CLASS, |
586 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
2208bf11 | 587 | omap2_control_base_init(); |
08f30989 | 588 | omap3xxx_check_revision(); |
7bcad170 | 589 | am33xx_check_features(); |
ab7b2ffc | 590 | omap2_prcm_base_init(); |
3f0ea764 | 591 | am33xx_powerdomains_init(); |
9c80f3aa | 592 | am33xx_clockdomains_init(); |
a2cfc509 VH |
593 | am33xx_hwmod_init(); |
594 | omap_hwmod_init_postsetup(); | |
149c09d3 | 595 | omap_clk_soc_init = am33xx_dt_clk_init; |
08f30989 | 596 | } |
765e7a06 NM |
597 | |
598 | void __init am33xx_init_late(void) | |
599 | { | |
600 | omap_common_late_init(); | |
601 | } | |
08f30989 AM |
602 | #endif |
603 | ||
c5107027 AM |
604 | #ifdef CONFIG_SOC_AM43XX |
605 | void __init am43xx_init_early(void) | |
606 | { | |
607 | omap2_set_globals_tap(AM335X_CLASS, | |
608 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
2208bf11 | 609 | omap2_control_base_init(); |
c5107027 | 610 | omap3xxx_check_revision(); |
7a2e0513 | 611 | am33xx_check_features(); |
ab7b2ffc | 612 | omap2_prcm_base_init(); |
8835cf6e A |
613 | am43xx_powerdomains_init(); |
614 | am43xx_clockdomains_init(); | |
615 | am43xx_hwmod_init(); | |
616 | omap_hwmod_init_postsetup(); | |
d941f86f | 617 | omap_l2_cache_init(); |
d22031e2 | 618 | omap_clk_soc_init = am43xx_dt_clk_init; |
c5107027 | 619 | } |
765e7a06 NM |
620 | |
621 | void __init am43xx_init_late(void) | |
622 | { | |
623 | omap_common_late_init(); | |
624 | } | |
c5107027 AM |
625 | #endif |
626 | ||
c4e2d245 | 627 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
628 | void __init omap4430_init_early(void) |
629 | { | |
b6a4226c PW |
630 | omap2_set_globals_tap(OMAP443X_CLASS, |
631 | OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); | |
d9a16f9a | 632 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); |
ca125b5e | 633 | omap2_control_base_init(); |
4de34f35 VH |
634 | omap4xxx_check_revision(); |
635 | omap4xxx_check_features(); | |
ab7b2ffc | 636 | omap2_prcm_base_init(); |
de70af49 | 637 | omap4_pm_init_early(); |
7b250aff TL |
638 | omap44xx_voltagedomains_init(); |
639 | omap44xx_powerdomains_init(); | |
640 | omap44xx_clockdomains_init(); | |
641 | omap44xx_hwmod_init(); | |
642 | omap_hwmod_init_postsetup(); | |
b39b14e6 | 643 | omap_l2_cache_init(); |
c8c88d85 | 644 | omap_clk_soc_init = omap4xxx_dt_clk_init; |
8f5b5a41 | 645 | } |
bbd707ac SG |
646 | |
647 | void __init omap4430_init_late(void) | |
648 | { | |
4ed12be0 | 649 | omap_common_late_init(); |
bbd707ac | 650 | omap4_pm_init(); |
23fb8ba3 | 651 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 652 | } |
c4e2d245 | 653 | #endif |
8f5b5a41 | 654 | |
05e152c7 S |
655 | #ifdef CONFIG_SOC_OMAP5 |
656 | void __init omap5_init_early(void) | |
657 | { | |
b6a4226c PW |
658 | omap2_set_globals_tap(OMAP54XX_CLASS, |
659 | OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); | |
d9a16f9a | 660 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); |
ca125b5e | 661 | omap2_control_base_init(); |
628ed471 | 662 | omap4_pm_init_early(); |
ab7b2ffc | 663 | omap2_prcm_base_init(); |
05e152c7 | 664 | omap5xxx_check_revision(); |
e4020aa9 SS |
665 | omap54xx_voltagedomains_init(); |
666 | omap54xx_powerdomains_init(); | |
667 | omap54xx_clockdomains_init(); | |
668 | omap54xx_hwmod_init(); | |
669 | omap_hwmod_init_postsetup(); | |
cfa9667d | 670 | omap_clk_soc_init = omap5xxx_dt_clk_init; |
05e152c7 | 671 | } |
765e7a06 NM |
672 | |
673 | void __init omap5_init_late(void) | |
674 | { | |
675 | omap_common_late_init(); | |
628ed471 SS |
676 | omap4_pm_init(); |
677 | omap2_clk_enable_autoidle_all(); | |
765e7a06 | 678 | } |
05e152c7 S |
679 | #endif |
680 | ||
a3a9384a S |
681 | #ifdef CONFIG_SOC_DRA7XX |
682 | void __init dra7xx_init_early(void) | |
683 | { | |
684 | omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); | |
a3a9384a | 685 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); |
ca125b5e | 686 | omap2_control_base_init(); |
6af16a1d | 687 | omap4_pm_init_early(); |
ab7b2ffc | 688 | omap2_prcm_base_init(); |
733d20ee | 689 | dra7xxx_check_revision(); |
7de516a6 A |
690 | dra7xx_powerdomains_init(); |
691 | dra7xx_clockdomains_init(); | |
692 | dra7xx_hwmod_init(); | |
693 | omap_hwmod_init_postsetup(); | |
f1cf498e | 694 | omap_clk_soc_init = dra7xx_dt_clk_init; |
a3a9384a | 695 | } |
765e7a06 NM |
696 | |
697 | void __init dra7xx_init_late(void) | |
698 | { | |
699 | omap_common_late_init(); | |
6af16a1d RN |
700 | omap4_pm_init(); |
701 | omap2_clk_enable_autoidle_all(); | |
765e7a06 | 702 | } |
a3a9384a S |
703 | #endif |
704 | ||
705 | ||
a4ca9dbe | 706 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
707 | struct omap_sdrc_params *sdrc_cs1) |
708 | { | |
a66cb345 TL |
709 | omap_sram_init(); |
710 | ||
01001712 | 711 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
712 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
713 | _omap2_init_reprogram_sdrc(); | |
714 | } | |
1dbae815 | 715 | } |
cfa9667d TK |
716 | |
717 | int __init omap_clk_init(void) | |
718 | { | |
719 | int ret = 0; | |
720 | ||
721 | if (!omap_clk_soc_init) | |
722 | return 0; | |
723 | ||
8111e010 TK |
724 | ti_clk_init_features(); |
725 | ||
eded36fe | 726 | if (of_have_populated_dt()) { |
fe87414f TK |
727 | ret = omap_control_init(); |
728 | if (ret) | |
729 | return ret; | |
730 | ||
3a1a388e | 731 | ret = omap_prcm_init(); |
eded36fe TK |
732 | if (ret) |
733 | return ret; | |
c08ee14c | 734 | |
eded36fe | 735 | of_clk_init(NULL); |
c08ee14c | 736 | |
eded36fe | 737 | ti_dt_clk_init_retry_clks(); |
c08ee14c | 738 | |
eded36fe TK |
739 | ti_dt_clockdomains_setup(); |
740 | } | |
c08ee14c TK |
741 | |
742 | ret = omap_clk_soc_init(); | |
cfa9667d TK |
743 | |
744 | return ret; | |
745 | } |